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162 lines
4.5 KiB
162 lines
4.5 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* PPC64 Huge TLB Page Support for hash based MMUs (POWER4 and later) |
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* |
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* Copyright (C) 2003 David Gibson, IBM Corporation. |
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* |
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* Based on the IA-32 version: |
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* Copyright (C) 2002, Rohit Seth <[email protected]> |
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*/ |
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#include <linux/mm.h> |
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#include <linux/hugetlb.h> |
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#include <asm/cacheflush.h> |
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#include <asm/machdep.h> |
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unsigned int hpage_shift; |
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EXPORT_SYMBOL(hpage_shift); |
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int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid, |
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pte_t *ptep, unsigned long trap, unsigned long flags, |
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int ssize, unsigned int shift, unsigned int mmu_psize) |
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{ |
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real_pte_t rpte; |
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unsigned long vpn; |
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unsigned long old_pte, new_pte; |
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unsigned long rflags, pa; |
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long slot, offset; |
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BUG_ON(shift != mmu_psize_defs[mmu_psize].shift); |
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/* Search the Linux page table for a match with va */ |
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vpn = hpt_vpn(ea, vsid, ssize); |
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/* |
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* At this point, we have a pte (old_pte) which can be used to build |
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* or update an HPTE. There are 2 cases: |
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* |
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* 1. There is a valid (present) pte with no associated HPTE (this is |
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* the most common case) |
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* 2. There is a valid (present) pte with an associated HPTE. The |
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* current values of the pp bits in the HPTE prevent access |
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* because we are doing software DIRTY bit management and the |
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* page is currently not DIRTY. |
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*/ |
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do { |
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old_pte = pte_val(*ptep); |
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/* If PTE busy, retry the access */ |
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if (unlikely(old_pte & H_PAGE_BUSY)) |
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return 0; |
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/* If PTE permissions don't match, take page fault */ |
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if (unlikely(!check_pte_access(access, old_pte))) |
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return 1; |
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/* |
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* Try to lock the PTE, add ACCESSED and DIRTY if it was |
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* a write access |
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*/ |
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new_pte = old_pte | H_PAGE_BUSY | _PAGE_ACCESSED; |
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if (access & _PAGE_WRITE) |
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new_pte |= _PAGE_DIRTY; |
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} while(!pte_xchg(ptep, __pte(old_pte), __pte(new_pte))); |
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/* Make sure this is a hugetlb entry */ |
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if (old_pte & (H_PAGE_THP_HUGE | _PAGE_DEVMAP)) |
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return 0; |
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rflags = htab_convert_pte_flags(new_pte, flags); |
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if (unlikely(mmu_psize == MMU_PAGE_16G)) |
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offset = PTRS_PER_PUD; |
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else |
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offset = PTRS_PER_PMD; |
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rpte = __real_pte(__pte(old_pte), ptep, offset); |
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if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) |
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/* |
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* No CPU has hugepages but lacks no execute, so we |
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* don't need to worry about that case |
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*/ |
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rflags = hash_page_do_lazy_icache(rflags, __pte(old_pte), trap); |
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/* Check if pte already has an hpte (case 2) */ |
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if (unlikely(old_pte & H_PAGE_HASHPTE)) { |
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/* There MIGHT be an HPTE for this pte */ |
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unsigned long gslot; |
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gslot = pte_get_hash_gslot(vpn, shift, ssize, rpte, 0); |
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if (mmu_hash_ops.hpte_updatepp(gslot, rflags, vpn, mmu_psize, |
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mmu_psize, ssize, flags) == -1) |
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old_pte &= ~_PAGE_HPTEFLAGS; |
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} |
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if (likely(!(old_pte & H_PAGE_HASHPTE))) { |
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unsigned long hash = hpt_hash(vpn, shift, ssize); |
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pa = pte_pfn(__pte(old_pte)) << PAGE_SHIFT; |
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/* clear HPTE slot informations in new PTE */ |
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new_pte = (new_pte & ~_PAGE_HPTEFLAGS) | H_PAGE_HASHPTE; |
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slot = hpte_insert_repeating(hash, vpn, pa, rflags, 0, |
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mmu_psize, ssize); |
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/* |
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* Hypervisor failure. Restore old pte and return -1 |
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* similar to __hash_page_* |
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*/ |
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if (unlikely(slot == -2)) { |
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*ptep = __pte(old_pte); |
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hash_failure_debug(ea, access, vsid, trap, ssize, |
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mmu_psize, mmu_psize, old_pte); |
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return -1; |
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} |
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new_pte |= pte_set_hidx(ptep, rpte, 0, slot, offset); |
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} |
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/* |
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* No need to use ldarx/stdcx here |
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*/ |
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*ptep = __pte(new_pte & ~H_PAGE_BUSY); |
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return 0; |
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} |
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pte_t huge_ptep_modify_prot_start(struct vm_area_struct *vma, |
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unsigned long addr, pte_t *ptep) |
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{ |
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unsigned long pte_val; |
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/* |
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* Clear the _PAGE_PRESENT so that no hardware parallel update is |
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* possible. Also keep the pte_present true so that we don't take |
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* wrong fault. |
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*/ |
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pte_val = pte_update(vma->vm_mm, addr, ptep, |
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_PAGE_PRESENT, _PAGE_INVALID, 1); |
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return __pte(pte_val); |
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} |
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void huge_ptep_modify_prot_commit(struct vm_area_struct *vma, unsigned long addr, |
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pte_t *ptep, pte_t old_pte, pte_t pte) |
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{ |
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if (radix_enabled()) |
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return radix__huge_ptep_modify_prot_commit(vma, addr, ptep, |
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old_pte, pte); |
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set_huge_pte_at(vma->vm_mm, addr, ptep, pte); |
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} |
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void hugetlbpage_init_default(void) |
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{ |
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/* Set default large page size. Currently, we pick 16M or 1M |
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* depending on what is available |
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*/ |
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if (mmu_psize_defs[MMU_PAGE_16M].shift) |
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hpage_shift = mmu_psize_defs[MMU_PAGE_16M].shift; |
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else if (mmu_psize_defs[MMU_PAGE_1M].shift) |
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hpage_shift = mmu_psize_defs[MMU_PAGE_1M].shift; |
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else if (mmu_psize_defs[MMU_PAGE_2M].shift) |
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hpage_shift = mmu_psize_defs[MMU_PAGE_2M].shift; |
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}
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