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247 lines
6.0 KiB
247 lines
6.0 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* spu_csa.h: Definitions for SPU context save area (CSA). |
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* |
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* (C) Copyright IBM 2005 |
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* |
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* Author: Mark Nutter <[email protected]> |
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*/ |
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#ifndef _SPU_CSA_H_ |
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#define _SPU_CSA_H_ |
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#ifdef __KERNEL__ |
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/* |
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* Total number of 128-bit registers. |
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*/ |
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#define NR_SPU_GPRS 128 |
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#define NR_SPU_SPRS 9 |
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#define NR_SPU_REGS_PAD 7 |
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#define NR_SPU_SPILL_REGS 144 /* GPRS + SPRS + PAD */ |
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#define SIZEOF_SPU_SPILL_REGS NR_SPU_SPILL_REGS * 16 |
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#define SPU_SAVE_COMPLETE 0x3FFB |
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#define SPU_RESTORE_COMPLETE 0x3FFC |
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/* |
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* Definitions for various 'stopped' status conditions, |
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* to be recreated during context restore. |
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*/ |
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#define SPU_STOPPED_STATUS_P 1 |
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#define SPU_STOPPED_STATUS_I 2 |
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#define SPU_STOPPED_STATUS_H 3 |
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#define SPU_STOPPED_STATUS_S 4 |
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#define SPU_STOPPED_STATUS_S_I 5 |
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#define SPU_STOPPED_STATUS_S_P 6 |
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#define SPU_STOPPED_STATUS_P_H 7 |
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#define SPU_STOPPED_STATUS_P_I 8 |
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#define SPU_STOPPED_STATUS_R 9 |
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/* |
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* Definitions for software decrementer status flag. |
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*/ |
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#define SPU_DECR_STATUS_RUNNING 0x1 |
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#define SPU_DECR_STATUS_WRAPPED 0x2 |
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#ifndef __ASSEMBLY__ |
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/** |
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* spu_reg128 - generic 128-bit register definition. |
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*/ |
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struct spu_reg128 { |
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u32 slot[4]; |
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}; |
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/** |
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* struct spu_lscsa - Local Store Context Save Area. |
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* @gprs: Array of saved registers. |
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* @fpcr: Saved floating point status control register. |
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* @decr: Saved decrementer value. |
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* @decr_status: Indicates software decrementer status flags. |
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* @ppu_mb: Saved PPU mailbox data. |
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* @ppuint_mb: Saved PPU interrupting mailbox data. |
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* @tag_mask: Saved tag group mask. |
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* @event_mask: Saved event mask. |
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* @srr0: Saved SRR0. |
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* @stopped_status: Conditions to be recreated by restore. |
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* @ls: Saved contents of Local Storage Area. |
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* |
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* The LSCSA represents state that is primarily saved and |
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* restored by SPU-side code. |
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*/ |
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struct spu_lscsa { |
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struct spu_reg128 gprs[128]; |
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struct spu_reg128 fpcr; |
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struct spu_reg128 decr; |
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struct spu_reg128 decr_status; |
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struct spu_reg128 ppu_mb; |
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struct spu_reg128 ppuint_mb; |
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struct spu_reg128 tag_mask; |
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struct spu_reg128 event_mask; |
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struct spu_reg128 srr0; |
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struct spu_reg128 stopped_status; |
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/* |
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* 'ls' must be page-aligned on all configurations. |
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* Since we don't want to rely on having the spu-gcc |
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* installed to build the kernel and this structure |
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* is used in the SPU-side code, make it 64k-page |
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* aligned for now. |
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*/ |
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unsigned char ls[LS_SIZE] __attribute__((aligned(65536))); |
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}; |
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#ifndef __SPU__ |
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/* |
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* struct spu_problem_collapsed - condensed problem state area, w/o pads. |
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*/ |
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struct spu_problem_collapsed { |
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u64 spc_mssync_RW; |
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u32 mfc_lsa_W; |
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u32 unused_pad0; |
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u64 mfc_ea_W; |
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union mfc_tag_size_class_cmd mfc_union_W; |
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u32 dma_qstatus_R; |
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u32 dma_querytype_RW; |
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u32 dma_querymask_RW; |
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u32 dma_tagstatus_R; |
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u32 pu_mb_R; |
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u32 spu_mb_W; |
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u32 mb_stat_R; |
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u32 spu_runcntl_RW; |
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u32 spu_status_R; |
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u32 spu_spc_R; |
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u32 spu_npc_RW; |
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u32 signal_notify1; |
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u32 signal_notify2; |
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u32 unused_pad1; |
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}; |
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/* |
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* struct spu_priv1_collapsed - condensed privileged 1 area, w/o pads. |
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*/ |
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struct spu_priv1_collapsed { |
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u64 mfc_sr1_RW; |
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u64 mfc_lpid_RW; |
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u64 spu_idr_RW; |
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u64 mfc_vr_RO; |
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u64 spu_vr_RO; |
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u64 int_mask_class0_RW; |
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u64 int_mask_class1_RW; |
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u64 int_mask_class2_RW; |
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u64 int_stat_class0_RW; |
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u64 int_stat_class1_RW; |
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u64 int_stat_class2_RW; |
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u64 int_route_RW; |
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u64 mfc_atomic_flush_RW; |
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u64 resource_allocation_groupID_RW; |
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u64 resource_allocation_enable_RW; |
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u64 mfc_fir_R; |
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u64 mfc_fir_status_or_W; |
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u64 mfc_fir_status_and_W; |
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u64 mfc_fir_mask_R; |
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u64 mfc_fir_mask_or_W; |
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u64 mfc_fir_mask_and_W; |
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u64 mfc_fir_chkstp_enable_RW; |
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u64 smf_sbi_signal_sel; |
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u64 smf_ato_signal_sel; |
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u64 tlb_index_hint_RO; |
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u64 tlb_index_W; |
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u64 tlb_vpn_RW; |
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u64 tlb_rpn_RW; |
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u64 tlb_invalidate_entry_W; |
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u64 tlb_invalidate_all_W; |
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u64 smm_hid; |
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u64 mfc_accr_RW; |
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u64 mfc_dsisr_RW; |
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u64 mfc_dar_RW; |
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u64 rmt_index_RW; |
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u64 rmt_data1_RW; |
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u64 mfc_dsir_R; |
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u64 mfc_lsacr_RW; |
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u64 mfc_lscrr_R; |
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u64 mfc_tclass_id_RW; |
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u64 mfc_rm_boundary; |
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u64 smf_dma_signal_sel; |
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u64 smm_signal_sel; |
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u64 mfc_cer_R; |
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u64 pu_ecc_cntl_RW; |
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u64 pu_ecc_stat_RW; |
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u64 spu_ecc_addr_RW; |
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u64 spu_err_mask_RW; |
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u64 spu_trig0_sel; |
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u64 spu_trig1_sel; |
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u64 spu_trig2_sel; |
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u64 spu_trig3_sel; |
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u64 spu_trace_sel; |
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u64 spu_event0_sel; |
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u64 spu_event1_sel; |
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u64 spu_event2_sel; |
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u64 spu_event3_sel; |
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u64 spu_trace_cntl; |
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}; |
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/* |
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* struct spu_priv2_collapsed - condensed privileged 2 area, w/o pads. |
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*/ |
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struct spu_priv2_collapsed { |
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u64 slb_index_W; |
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u64 slb_esid_RW; |
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u64 slb_vsid_RW; |
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u64 slb_invalidate_entry_W; |
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u64 slb_invalidate_all_W; |
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struct mfc_cq_sr spuq[16]; |
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struct mfc_cq_sr puq[8]; |
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u64 mfc_control_RW; |
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u64 puint_mb_R; |
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u64 spu_privcntl_RW; |
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u64 spu_lslr_RW; |
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u64 spu_chnlcntptr_RW; |
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u64 spu_chnlcnt_RW; |
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u64 spu_chnldata_RW; |
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u64 spu_cfg_RW; |
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u64 spu_tag_status_query_RW; |
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u64 spu_cmd_buf1_RW; |
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u64 spu_cmd_buf2_RW; |
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u64 spu_atomic_status_RW; |
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}; |
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/** |
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* struct spu_state |
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* @lscsa: Local Store Context Save Area. |
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* @prob: Collapsed Problem State Area, w/o pads. |
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* @priv1: Collapsed Privileged 1 Area, w/o pads. |
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* @priv2: Collapsed Privileged 2 Area, w/o pads. |
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* @spu_chnlcnt_RW: Array of saved channel counts. |
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* @spu_chnldata_RW: Array of saved channel data. |
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* @suspend_time: Time stamp when decrementer disabled. |
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* |
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* Structure representing the whole of the SPU |
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* context save area (CSA). This struct contains |
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* all of the state necessary to suspend and then |
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* later optionally resume execution of an SPU |
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* context. |
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* |
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* The @lscsa region is by far the largest, and is |
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* allocated separately so that it may either be |
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* pinned or mapped to/from application memory, as |
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* appropriate for the OS environment. |
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*/ |
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struct spu_state { |
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struct spu_lscsa *lscsa; |
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struct spu_problem_collapsed prob; |
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struct spu_priv1_collapsed priv1; |
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struct spu_priv2_collapsed priv2; |
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u64 spu_chnlcnt_RW[32]; |
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u64 spu_chnldata_RW[32]; |
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u32 spu_mailbox_data[4]; |
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u32 pu_mailbox_data[1]; |
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u64 class_0_dar, class_0_pending; |
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u64 class_1_dar, class_1_dsisr; |
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unsigned long suspend_time; |
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spinlock_t register_lock; |
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}; |
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#endif /* !__SPU__ */ |
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#endif /* __KERNEL__ */ |
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#endif /* !__ASSEMBLY__ */ |
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#endif /* _SPU_CSA_H_ */
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