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76 lines
3.1 KiB
76 lines
3.1 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* IPIC external definitions and structure. |
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* |
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* Maintainer: Kumar Gala <[email protected]> |
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* |
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* Copyright 2005 Freescale Semiconductor, Inc |
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*/ |
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#ifdef __KERNEL__ |
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#ifndef __ASM_IPIC_H__ |
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#define __ASM_IPIC_H__ |
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#include <linux/irq.h> |
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/* Flags when we init the IPIC */ |
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#define IPIC_SPREADMODE_GRP_A 0x00000001 |
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#define IPIC_SPREADMODE_GRP_B 0x00000002 |
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#define IPIC_SPREADMODE_GRP_C 0x00000004 |
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#define IPIC_SPREADMODE_GRP_D 0x00000008 |
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#define IPIC_SPREADMODE_MIX_A 0x00000010 |
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#define IPIC_SPREADMODE_MIX_B 0x00000020 |
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#define IPIC_DISABLE_MCP_OUT 0x00000040 |
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#define IPIC_IRQ0_MCP 0x00000080 |
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/* IPIC registers offsets */ |
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#define IPIC_SICFR 0x00 /* System Global Interrupt Configuration Register */ |
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#define IPIC_SIVCR 0x04 /* System Global Interrupt Vector Register */ |
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#define IPIC_SIPNR_H 0x08 /* System Internal Interrupt Pending Register (HIGH) */ |
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#define IPIC_SIPNR_L 0x0C /* System Internal Interrupt Pending Register (LOW) */ |
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#define IPIC_SIPRR_A 0x10 /* System Internal Interrupt group A Priority Register */ |
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#define IPIC_SIPRR_B 0x14 /* System Internal Interrupt group B Priority Register */ |
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#define IPIC_SIPRR_C 0x18 /* System Internal Interrupt group C Priority Register */ |
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#define IPIC_SIPRR_D 0x1C /* System Internal Interrupt group D Priority Register */ |
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#define IPIC_SIMSR_H 0x20 /* System Internal Interrupt Mask Register (HIGH) */ |
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#define IPIC_SIMSR_L 0x24 /* System Internal Interrupt Mask Register (LOW) */ |
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#define IPIC_SICNR 0x28 /* System Internal Interrupt Control Register */ |
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#define IPIC_SEPNR 0x2C /* System External Interrupt Pending Register */ |
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#define IPIC_SMPRR_A 0x30 /* System Mixed Interrupt group A Priority Register */ |
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#define IPIC_SMPRR_B 0x34 /* System Mixed Interrupt group B Priority Register */ |
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#define IPIC_SEMSR 0x38 /* System External Interrupt Mask Register */ |
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#define IPIC_SECNR 0x3C /* System External Interrupt Control Register */ |
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#define IPIC_SERSR 0x40 /* System Error Status Register */ |
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#define IPIC_SERMR 0x44 /* System Error Mask Register */ |
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#define IPIC_SERCR 0x48 /* System Error Control Register */ |
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#define IPIC_SIFCR_H 0x50 /* System Internal Interrupt Force Register (HIGH) */ |
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#define IPIC_SIFCR_L 0x54 /* System Internal Interrupt Force Register (LOW) */ |
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#define IPIC_SEFCR 0x58 /* System External Interrupt Force Register */ |
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#define IPIC_SERFR 0x5C /* System Error Force Register */ |
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#define IPIC_SCVCR 0x60 /* System Critical Interrupt Vector Register */ |
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#define IPIC_SMVCR 0x64 /* System Management Interrupt Vector Register */ |
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enum ipic_prio_grp { |
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IPIC_INT_GRP_A = IPIC_SIPRR_A, |
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IPIC_INT_GRP_D = IPIC_SIPRR_D, |
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IPIC_MIX_GRP_A = IPIC_SMPRR_A, |
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IPIC_MIX_GRP_B = IPIC_SMPRR_B, |
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}; |
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enum ipic_mcp_irq { |
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IPIC_MCP_IRQ0 = 0, |
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IPIC_MCP_WDT = 1, |
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IPIC_MCP_SBA = 2, |
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IPIC_MCP_PCI1 = 5, |
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IPIC_MCP_PCI2 = 6, |
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IPIC_MCP_MU = 7, |
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}; |
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extern void ipic_set_default_priority(void); |
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extern u32 ipic_get_mcp_status(void); |
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extern void ipic_clear_mcp_status(u32 mask); |
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extern struct ipic * ipic_init(struct device_node *node, unsigned int flags); |
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extern unsigned int ipic_get_irq(void); |
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#endif /* __ASM_IPIC_H__ */ |
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#endif /* __KERNEL__ */
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