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144 lines
3.8 KiB
144 lines
3.8 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp. |
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* <[email protected]> |
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*/ |
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#ifndef _ASM_POWERPC_DCR_NATIVE_H |
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#define _ASM_POWERPC_DCR_NATIVE_H |
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#ifdef __KERNEL__ |
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#ifndef __ASSEMBLY__ |
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#include <linux/spinlock.h> |
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#include <asm/cputable.h> |
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#include <asm/cpu_has_feature.h> |
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#include <linux/stringify.h> |
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typedef struct { |
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unsigned int base; |
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} dcr_host_native_t; |
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static inline bool dcr_map_ok_native(dcr_host_native_t host) |
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{ |
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return true; |
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} |
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#define dcr_map_native(dev, dcr_n, dcr_c) \ |
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((dcr_host_native_t){ .base = (dcr_n) }) |
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#define dcr_unmap_native(host, dcr_c) do {} while (0) |
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#define dcr_read_native(host, dcr_n) mfdcr(dcr_n + host.base) |
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#define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n + host.base, value) |
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/* Table based DCR accessors */ |
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extern void __mtdcr(unsigned int reg, unsigned int val); |
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extern unsigned int __mfdcr(unsigned int reg); |
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/* mfdcrx/mtdcrx instruction based accessors. We hand code |
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* the opcodes in order not to depend on newer binutils |
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*/ |
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static inline unsigned int mfdcrx(unsigned int reg) |
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{ |
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unsigned int ret; |
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asm volatile(".long 0x7c000206 | (%0 << 21) | (%1 << 16)" |
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: "=r" (ret) : "r" (reg)); |
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return ret; |
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} |
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static inline void mtdcrx(unsigned int reg, unsigned int val) |
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{ |
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asm volatile(".long 0x7c000306 | (%0 << 21) | (%1 << 16)" |
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: : "r" (val), "r" (reg)); |
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} |
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#define mfdcr(rn) \ |
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({unsigned int rval; \ |
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if (__builtin_constant_p(rn) && rn < 1024) \ |
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asm volatile("mfdcr %0, %1" : "=r" (rval) \ |
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: "n" (rn)); \ |
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else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR))) \ |
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rval = mfdcrx(rn); \ |
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else \ |
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rval = __mfdcr(rn); \ |
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rval;}) |
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#define mtdcr(rn, v) \ |
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do { \ |
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if (__builtin_constant_p(rn) && rn < 1024) \ |
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asm volatile("mtdcr %0, %1" \ |
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: : "n" (rn), "r" (v)); \ |
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else if (likely(cpu_has_feature(CPU_FTR_INDEXED_DCR))) \ |
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mtdcrx(rn, v); \ |
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else \ |
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__mtdcr(rn, v); \ |
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} while (0) |
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/* R/W of indirect DCRs make use of standard naming conventions for DCRs */ |
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extern spinlock_t dcr_ind_lock; |
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static inline unsigned __mfdcri(int base_addr, int base_data, int reg) |
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{ |
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unsigned long flags; |
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unsigned int val; |
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spin_lock_irqsave(&dcr_ind_lock, flags); |
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if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) { |
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mtdcrx(base_addr, reg); |
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val = mfdcrx(base_data); |
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} else { |
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__mtdcr(base_addr, reg); |
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val = __mfdcr(base_data); |
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} |
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spin_unlock_irqrestore(&dcr_ind_lock, flags); |
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return val; |
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} |
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static inline void __mtdcri(int base_addr, int base_data, int reg, |
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unsigned val) |
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{ |
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unsigned long flags; |
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spin_lock_irqsave(&dcr_ind_lock, flags); |
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if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) { |
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mtdcrx(base_addr, reg); |
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mtdcrx(base_data, val); |
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} else { |
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__mtdcr(base_addr, reg); |
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__mtdcr(base_data, val); |
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} |
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spin_unlock_irqrestore(&dcr_ind_lock, flags); |
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} |
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static inline void __dcri_clrset(int base_addr, int base_data, int reg, |
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unsigned clr, unsigned set) |
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{ |
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unsigned long flags; |
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unsigned int val; |
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spin_lock_irqsave(&dcr_ind_lock, flags); |
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if (cpu_has_feature(CPU_FTR_INDEXED_DCR)) { |
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mtdcrx(base_addr, reg); |
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val = (mfdcrx(base_data) & ~clr) | set; |
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mtdcrx(base_data, val); |
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} else { |
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__mtdcr(base_addr, reg); |
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val = (__mfdcr(base_data) & ~clr) | set; |
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__mtdcr(base_data, val); |
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} |
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spin_unlock_irqrestore(&dcr_ind_lock, flags); |
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} |
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#define mfdcri(base, reg) __mfdcri(DCRN_ ## base ## _CONFIG_ADDR, \ |
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DCRN_ ## base ## _CONFIG_DATA, \ |
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reg) |
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#define mtdcri(base, reg, data) __mtdcri(DCRN_ ## base ## _CONFIG_ADDR, \ |
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DCRN_ ## base ## _CONFIG_DATA, \ |
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reg, data) |
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#define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \ |
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DCRN_ ## base ## _CONFIG_DATA, \ |
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reg, clr, set) |
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#endif /* __ASSEMBLY__ */ |
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#endif /* __KERNEL__ */ |
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#endif /* _ASM_POWERPC_DCR_NATIVE_H */
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