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183 lines
3.6 KiB
183 lines
3.6 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* phyCORE-MPC5200B-IO (pcm032) board Device Tree Source |
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* |
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* Copyright (C) 2006-2009 Pengutronix |
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* Sascha Hauer, Juergen Beisert, Wolfram Sang <[email protected]> |
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*/ |
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/include/ "mpc5200b.dtsi" |
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&gpt0 { fsl,has-wdt; }; |
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&gpt2 { gpio-controller; }; |
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&gpt3 { gpio-controller; }; |
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&gpt4 { gpio-controller; }; |
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&gpt5 { gpio-controller; }; |
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&gpt6 { gpio-controller; }; |
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&gpt7 { gpio-controller; }; |
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/ { |
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model = "phytec,pcm032"; |
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compatible = "phytec,pcm032"; |
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memory { |
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reg = <0x00000000 0x08000000>; // 128MB |
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}; |
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soc5200@f0000000 { |
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psc@2000 { /* PSC1 is ac97 */ |
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compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97"; |
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cell-index = <0>; |
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}; |
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/* PSC2 port is used by CAN1/2 */ |
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psc@2200 { |
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status = "disabled"; |
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}; |
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psc@2400 { /* PSC3 in UART mode */ |
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; |
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}; |
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/* PSC4 is ??? */ |
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psc@2600 { |
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status = "disabled"; |
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}; |
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/* PSC5 is ??? */ |
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psc@2800 { |
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status = "disabled"; |
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}; |
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psc@2c00 { /* PSC6 in UART mode */ |
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compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; |
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}; |
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ethernet@3000 { |
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phy-handle = <&phy0>; |
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}; |
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mdio@3000 { |
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phy0: ethernet-phy@0 { |
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reg = <0>; |
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}; |
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}; |
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i2c@3d40 { |
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rtc@51 { |
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compatible = "nxp,pcf8563"; |
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reg = <0x51>; |
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}; |
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eeprom@52 { |
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compatible = "catalyst,24c32", "atmel,24c32"; |
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reg = <0x52>; |
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pagesize = <32>; |
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}; |
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}; |
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}; |
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pci@f0000d00 { |
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interrupt-map-mask = <0xf800 0 0 7>; |
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interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot |
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0xc000 0 0 2 &mpc5200_pic 1 1 3 |
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0xc000 0 0 3 &mpc5200_pic 1 2 3 |
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0xc000 0 0 4 &mpc5200_pic 1 3 3 |
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0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot |
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0xc800 0 0 2 &mpc5200_pic 1 2 3 |
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0xc800 0 0 3 &mpc5200_pic 1 3 3 |
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0xc800 0 0 4 &mpc5200_pic 0 0 3>; |
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ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 |
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0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 |
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0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; |
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}; |
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localbus { |
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ranges = <0 0 0xfe000000 0x02000000 |
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1 0 0xfc000000 0x02000000 |
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2 0 0xfbe00000 0x00200000 |
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3 0 0xf9e00000 0x02000000 |
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4 0 0xf7e00000 0x02000000 |
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5 0 0xe6000000 0x02000000 |
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6 0 0xe8000000 0x02000000 |
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7 0 0xea000000 0x02000000>; |
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flash@0,0 { |
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compatible = "cfi-flash"; |
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reg = <0 0 0x02000000>; |
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bank-width = <4>; |
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#size-cells = <1>; |
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#address-cells = <1>; |
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partition@0 { |
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label = "ubootl"; |
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reg = <0x00000000 0x00040000>; |
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}; |
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partition@40000 { |
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label = "kernel"; |
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reg = <0x00040000 0x001c0000>; |
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}; |
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partition@200000 { |
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label = "jffs2"; |
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reg = <0x00200000 0x01d00000>; |
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}; |
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partition@1f00000 { |
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label = "uboot"; |
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reg = <0x01f00000 0x00040000>; |
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}; |
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partition@1f40000 { |
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label = "env"; |
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reg = <0x01f40000 0x00040000>; |
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}; |
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partition@1f80000 { |
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label = "oftree"; |
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reg = <0x01f80000 0x00040000>; |
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}; |
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partition@1fc0000 { |
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label = "space"; |
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reg = <0x01fc0000 0x00040000>; |
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}; |
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}; |
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sram@2,0 { |
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compatible = "mtd-ram"; |
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reg = <2 0 0x00200000>; |
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bank-width = <2>; |
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}; |
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/* |
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* example snippets for FPGA |
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* |
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* fpga@3,0 { |
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* compatible = "fpga_driver"; |
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* reg = <3 0 0x02000000>; |
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* bank-width = <4>; |
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* }; |
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* |
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* fpga@4,0 { |
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* compatible = "fpga_driver"; |
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* reg = <4 0 0x02000000>; |
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* bank-width = <4>; |
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* }; |
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*/ |
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/* |
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* example snippets for free chipselects |
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* |
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* device@5,0 { |
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* compatible = "custom_driver"; |
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* reg = <5 0 0x02000000>; |
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* }; |
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* |
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* device@6,0 { |
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* compatible = "custom_driver"; |
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* reg = <6 0 0x02000000>; |
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* }; |
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* |
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* device@7,0 { |
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* compatible = "custom_driver"; |
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* reg = <7 0 0x02000000>; |
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* }; |
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*/ |
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}; |
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};
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