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526 lines
12 KiB
526 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* base MPC5121 Device Tree Source |
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* |
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* Copyright 2007-2008 Freescale Semiconductor Inc. |
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*/ |
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#include <dt-bindings/clock/mpc512x-clock.h> |
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/dts-v1/; |
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/ { |
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model = "mpc5121"; |
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compatible = "fsl,mpc5121"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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interrupt-parent = <&ipic>; |
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aliases { |
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ethernet0 = ð0; |
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pci = &pci; |
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}; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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PowerPC,5121@0 { |
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device_type = "cpu"; |
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reg = <0>; |
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d-cache-line-size = <0x20>; /* 32 bytes */ |
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i-cache-line-size = <0x20>; /* 32 bytes */ |
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d-cache-size = <0x8000>; /* L1, 32K */ |
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i-cache-size = <0x8000>; /* L1, 32K */ |
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timebase-frequency = <49500000>;/* 49.5 MHz (csb/4) */ |
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bus-frequency = <198000000>; /* 198 MHz csb bus */ |
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clock-frequency = <396000000>; /* 396 MHz ppc core */ |
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}; |
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}; |
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memory { |
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device_type = "memory"; |
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reg = <0x00000000 0x10000000>; /* 256MB at 0 */ |
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}; |
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mbx@20000000 { |
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compatible = "fsl,mpc5121-mbx"; |
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reg = <0x20000000 0x4000>; |
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interrupts = <66 0x8>; |
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clocks = <&clks MPC512x_CLK_MBX_BUS>, |
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<&clks MPC512x_CLK_MBX_3D>, |
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<&clks MPC512x_CLK_MBX>; |
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clock-names = "mbx-bus", "mbx-3d", "mbx"; |
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}; |
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sram@30000000 { |
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compatible = "fsl,mpc5121-sram"; |
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reg = <0x30000000 0x20000>; /* 128K at 0x30000000 */ |
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}; |
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nfc@40000000 { |
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compatible = "fsl,mpc5121-nfc"; |
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reg = <0x40000000 0x100000>; /* 1M at 0x40000000 */ |
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interrupts = <6 8>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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clocks = <&clks MPC512x_CLK_NFC>; |
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clock-names = "ipg"; |
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}; |
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localbus@80000020 { |
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compatible = "fsl,mpc5121-localbus"; |
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#address-cells = <2>; |
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#size-cells = <1>; |
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reg = <0x80000020 0x40>; |
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ranges = <0x0 0x0 0xfc000000 0x04000000>; |
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}; |
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clocks { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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osc: osc { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <33000000>; |
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}; |
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}; |
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soc@80000000 { |
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compatible = "fsl,mpc5121-immr"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0x0 0x80000000 0x400000>; |
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reg = <0x80000000 0x400000>; |
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bus-frequency = <66000000>; /* 66 MHz ips bus */ |
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/* |
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* IPIC |
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* interrupts cell = <intr #, sense> |
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* sense values match linux IORESOURCE_IRQ_* defines: |
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* sense == 8: Level, low assertion |
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* sense == 2: Edge, high-to-low change |
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*/ |
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ipic: interrupt-controller@c00 { |
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compatible = "fsl,mpc5121-ipic", "fsl,ipic"; |
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interrupt-controller; |
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#address-cells = <0>; |
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#interrupt-cells = <2>; |
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reg = <0xc00 0x100>; |
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}; |
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/* Watchdog timer */ |
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wdt@900 { |
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compatible = "fsl,mpc5121-wdt"; |
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reg = <0x900 0x100>; |
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}; |
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/* Real time clock */ |
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rtc@a00 { |
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compatible = "fsl,mpc5121-rtc"; |
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reg = <0xa00 0x100>; |
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interrupts = <79 0x8 80 0x8>; |
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}; |
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/* Reset module */ |
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reset@e00 { |
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compatible = "fsl,mpc5121-reset"; |
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reg = <0xe00 0x100>; |
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}; |
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/* Clock control */ |
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clks: clock@f00 { |
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compatible = "fsl,mpc5121-clock"; |
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reg = <0xf00 0x100>; |
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#clock-cells = <1>; |
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clocks = <&osc>; |
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clock-names = "osc"; |
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}; |
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/* Power Management Controller */ |
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pmc@1000{ |
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compatible = "fsl,mpc5121-pmc"; |
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reg = <0x1000 0x100>; |
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interrupts = <83 0x8>; |
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}; |
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gpio@1100 { |
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compatible = "fsl,mpc5121-gpio"; |
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reg = <0x1100 0x100>; |
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interrupts = <78 0x8>; |
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}; |
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can@1300 { |
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compatible = "fsl,mpc5121-mscan"; |
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reg = <0x1300 0x80>; |
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interrupts = <12 0x8>; |
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clocks = <&clks MPC512x_CLK_BDLC>, |
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<&clks MPC512x_CLK_IPS>, |
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<&clks MPC512x_CLK_SYS>, |
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<&clks MPC512x_CLK_REF>, |
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<&clks MPC512x_CLK_MSCAN0_MCLK>; |
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clock-names = "ipg", "ips", "sys", "ref", "mclk"; |
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}; |
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can@1380 { |
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compatible = "fsl,mpc5121-mscan"; |
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reg = <0x1380 0x80>; |
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interrupts = <13 0x8>; |
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clocks = <&clks MPC512x_CLK_BDLC>, |
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<&clks MPC512x_CLK_IPS>, |
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<&clks MPC512x_CLK_SYS>, |
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<&clks MPC512x_CLK_REF>, |
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<&clks MPC512x_CLK_MSCAN1_MCLK>; |
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clock-names = "ipg", "ips", "sys", "ref", "mclk"; |
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}; |
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sdhc@1500 { |
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compatible = "fsl,mpc5121-sdhc"; |
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reg = <0x1500 0x100>; |
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interrupts = <8 0x8>; |
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dmas = <&dma0 30>; |
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dma-names = "rx-tx"; |
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clocks = <&clks MPC512x_CLK_IPS>, |
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<&clks MPC512x_CLK_SDHC>; |
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clock-names = "ipg", "per"; |
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}; |
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i2c@1700 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "fsl,mpc5121-i2c", "fsl-i2c"; |
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reg = <0x1700 0x20>; |
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interrupts = <9 0x8>; |
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clocks = <&clks MPC512x_CLK_I2C>; |
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clock-names = "ipg"; |
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}; |
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i2c@1720 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "fsl,mpc5121-i2c", "fsl-i2c"; |
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reg = <0x1720 0x20>; |
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interrupts = <10 0x8>; |
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clocks = <&clks MPC512x_CLK_I2C>; |
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clock-names = "ipg"; |
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}; |
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i2c@1740 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "fsl,mpc5121-i2c", "fsl-i2c"; |
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reg = <0x1740 0x20>; |
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interrupts = <11 0x8>; |
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clocks = <&clks MPC512x_CLK_I2C>; |
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clock-names = "ipg"; |
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}; |
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i2ccontrol@1760 { |
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compatible = "fsl,mpc5121-i2c-ctrl"; |
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reg = <0x1760 0x8>; |
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}; |
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axe@2000 { |
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compatible = "fsl,mpc5121-axe"; |
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reg = <0x2000 0x100>; |
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interrupts = <42 0x8>; |
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clocks = <&clks MPC512x_CLK_AXE>; |
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clock-names = "ipg"; |
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}; |
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display@2100 { |
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compatible = "fsl,mpc5121-diu"; |
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reg = <0x2100 0x100>; |
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interrupts = <64 0x8>; |
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clocks = <&clks MPC512x_CLK_DIU>; |
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clock-names = "ipg"; |
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}; |
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can@2300 { |
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compatible = "fsl,mpc5121-mscan"; |
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reg = <0x2300 0x80>; |
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interrupts = <90 0x8>; |
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clocks = <&clks MPC512x_CLK_BDLC>, |
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<&clks MPC512x_CLK_IPS>, |
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<&clks MPC512x_CLK_SYS>, |
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<&clks MPC512x_CLK_REF>, |
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<&clks MPC512x_CLK_MSCAN2_MCLK>; |
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clock-names = "ipg", "ips", "sys", "ref", "mclk"; |
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}; |
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can@2380 { |
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compatible = "fsl,mpc5121-mscan"; |
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reg = <0x2380 0x80>; |
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interrupts = <91 0x8>; |
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clocks = <&clks MPC512x_CLK_BDLC>, |
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<&clks MPC512x_CLK_IPS>, |
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<&clks MPC512x_CLK_SYS>, |
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<&clks MPC512x_CLK_REF>, |
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<&clks MPC512x_CLK_MSCAN3_MCLK>; |
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clock-names = "ipg", "ips", "sys", "ref", "mclk"; |
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}; |
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viu@2400 { |
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compatible = "fsl,mpc5121-viu"; |
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reg = <0x2400 0x400>; |
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interrupts = <67 0x8>; |
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clocks = <&clks MPC512x_CLK_VIU>; |
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clock-names = "ipg"; |
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}; |
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mdio@2800 { |
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compatible = "fsl,mpc5121-fec-mdio"; |
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reg = <0x2800 0x800>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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clocks = <&clks MPC512x_CLK_FEC>; |
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clock-names = "per"; |
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}; |
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eth0: ethernet@2800 { |
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device_type = "network"; |
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compatible = "fsl,mpc5121-fec"; |
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reg = <0x2800 0x800>; |
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local-mac-address = [ 00 00 00 00 00 00 ]; |
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interrupts = <4 0x8>; |
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clocks = <&clks MPC512x_CLK_FEC>; |
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clock-names = "per"; |
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}; |
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/* USB1 using external ULPI PHY */ |
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usb@3000 { |
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compatible = "fsl,mpc5121-usb2-dr"; |
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reg = <0x3000 0x600>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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interrupts = <43 0x8>; |
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dr_mode = "otg"; |
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phy_type = "ulpi"; |
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clocks = <&clks MPC512x_CLK_USB1>; |
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clock-names = "ipg"; |
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}; |
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/* USB0 using internal UTMI PHY */ |
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usb@4000 { |
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compatible = "fsl,mpc5121-usb2-dr"; |
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reg = <0x4000 0x600>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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interrupts = <44 0x8>; |
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dr_mode = "otg"; |
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phy_type = "utmi_wide"; |
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clocks = <&clks MPC512x_CLK_USB2>; |
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clock-names = "ipg"; |
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}; |
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/* IO control */ |
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ioctl@a000 { |
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compatible = "fsl,mpc5121-ioctl"; |
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reg = <0xA000 0x1000>; |
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}; |
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/* LocalPlus controller */ |
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lpc@10000 { |
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compatible = "fsl,mpc5121-lpc"; |
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reg = <0x10000 0x100>; |
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}; |
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sclpc@10100 { |
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compatible = "fsl,mpc512x-lpbfifo"; |
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reg = <0x10100 0x50>; |
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interrupts = <7 0x8>; |
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dmas = <&dma0 26>; |
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dma-names = "rx-tx"; |
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}; |
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pata@10200 { |
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compatible = "fsl,mpc5121-pata"; |
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reg = <0x10200 0x100>; |
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interrupts = <5 0x8>; |
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clocks = <&clks MPC512x_CLK_PATA>; |
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clock-names = "ipg"; |
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}; |
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/* 512x PSCs are not 52xx PSC compatible */ |
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/* PSC0 */ |
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psc@11000 { |
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compatible = "fsl,mpc5121-psc"; |
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reg = <0x11000 0x100>; |
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interrupts = <40 0x8>; |
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fsl,rx-fifo-size = <16>; |
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fsl,tx-fifo-size = <16>; |
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clocks = <&clks MPC512x_CLK_PSC0>, |
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<&clks MPC512x_CLK_PSC0_MCLK>; |
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clock-names = "ipg", "mclk"; |
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}; |
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/* PSC1 */ |
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psc@11100 { |
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compatible = "fsl,mpc5121-psc"; |
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reg = <0x11100 0x100>; |
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interrupts = <40 0x8>; |
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fsl,rx-fifo-size = <16>; |
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fsl,tx-fifo-size = <16>; |
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clocks = <&clks MPC512x_CLK_PSC1>, |
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<&clks MPC512x_CLK_PSC1_MCLK>; |
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clock-names = "ipg", "mclk"; |
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}; |
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/* PSC2 */ |
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psc@11200 { |
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compatible = "fsl,mpc5121-psc"; |
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reg = <0x11200 0x100>; |
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interrupts = <40 0x8>; |
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fsl,rx-fifo-size = <16>; |
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fsl,tx-fifo-size = <16>; |
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clocks = <&clks MPC512x_CLK_PSC2>, |
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<&clks MPC512x_CLK_PSC2_MCLK>; |
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clock-names = "ipg", "mclk"; |
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}; |
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/* PSC3 */ |
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psc@11300 { |
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compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; |
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reg = <0x11300 0x100>; |
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interrupts = <40 0x8>; |
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fsl,rx-fifo-size = <16>; |
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fsl,tx-fifo-size = <16>; |
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clocks = <&clks MPC512x_CLK_PSC3>, |
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<&clks MPC512x_CLK_PSC3_MCLK>; |
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clock-names = "ipg", "mclk"; |
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}; |
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/* PSC4 */ |
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psc@11400 { |
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compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc"; |
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reg = <0x11400 0x100>; |
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interrupts = <40 0x8>; |
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fsl,rx-fifo-size = <16>; |
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fsl,tx-fifo-size = <16>; |
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clocks = <&clks MPC512x_CLK_PSC4>, |
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<&clks MPC512x_CLK_PSC4_MCLK>; |
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clock-names = "ipg", "mclk"; |
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}; |
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/* PSC5 */ |
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psc@11500 { |
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compatible = "fsl,mpc5121-psc"; |
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reg = <0x11500 0x100>; |
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interrupts = <40 0x8>; |
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fsl,rx-fifo-size = <16>; |
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fsl,tx-fifo-size = <16>; |
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clocks = <&clks MPC512x_CLK_PSC5>, |
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<&clks MPC512x_CLK_PSC5_MCLK>; |
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clock-names = "ipg", "mclk"; |
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}; |
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/* PSC6 */ |
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psc@11600 { |
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compatible = "fsl,mpc5121-psc"; |
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reg = <0x11600 0x100>; |
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interrupts = <40 0x8>; |
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fsl,rx-fifo-size = <16>; |
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fsl,tx-fifo-size = <16>; |
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clocks = <&clks MPC512x_CLK_PSC6>, |
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<&clks MPC512x_CLK_PSC6_MCLK>; |
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clock-names = "ipg", "mclk"; |
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}; |
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/* PSC7 */ |
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psc@11700 { |
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compatible = "fsl,mpc5121-psc"; |
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reg = <0x11700 0x100>; |
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interrupts = <40 0x8>; |
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fsl,rx-fifo-size = <16>; |
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fsl,tx-fifo-size = <16>; |
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clocks = <&clks MPC512x_CLK_PSC7>, |
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<&clks MPC512x_CLK_PSC7_MCLK>; |
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clock-names = "ipg", "mclk"; |
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}; |
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/* PSC8 */ |
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psc@11800 { |
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compatible = "fsl,mpc5121-psc"; |
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reg = <0x11800 0x100>; |
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interrupts = <40 0x8>; |
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fsl,rx-fifo-size = <16>; |
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fsl,tx-fifo-size = <16>; |
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clocks = <&clks MPC512x_CLK_PSC8>, |
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<&clks MPC512x_CLK_PSC8_MCLK>; |
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clock-names = "ipg", "mclk"; |
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}; |
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/* PSC9 */ |
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psc@11900 { |
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compatible = "fsl,mpc5121-psc"; |
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reg = <0x11900 0x100>; |
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interrupts = <40 0x8>; |
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fsl,rx-fifo-size = <16>; |
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fsl,tx-fifo-size = <16>; |
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clocks = <&clks MPC512x_CLK_PSC9>, |
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<&clks MPC512x_CLK_PSC9_MCLK>; |
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clock-names = "ipg", "mclk"; |
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}; |
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/* PSC10 */ |
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psc@11a00 { |
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compatible = "fsl,mpc5121-psc"; |
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reg = <0x11a00 0x100>; |
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interrupts = <40 0x8>; |
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fsl,rx-fifo-size = <16>; |
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fsl,tx-fifo-size = <16>; |
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clocks = <&clks MPC512x_CLK_PSC10>, |
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<&clks MPC512x_CLK_PSC10_MCLK>; |
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clock-names = "ipg", "mclk"; |
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}; |
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/* PSC11 */ |
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psc@11b00 { |
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compatible = "fsl,mpc5121-psc"; |
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reg = <0x11b00 0x100>; |
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interrupts = <40 0x8>; |
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fsl,rx-fifo-size = <16>; |
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fsl,tx-fifo-size = <16>; |
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clocks = <&clks MPC512x_CLK_PSC11>, |
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<&clks MPC512x_CLK_PSC11_MCLK>; |
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clock-names = "ipg", "mclk"; |
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}; |
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pscfifo@11f00 { |
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compatible = "fsl,mpc5121-psc-fifo"; |
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reg = <0x11f00 0x100>; |
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interrupts = <40 0x8>; |
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clocks = <&clks MPC512x_CLK_PSC_FIFO>; |
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clock-names = "ipg"; |
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}; |
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dma0: dma@14000 { |
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compatible = "fsl,mpc5121-dma"; |
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reg = <0x14000 0x1800>; |
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interrupts = <65 0x8>; |
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#dma-cells = <1>; |
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}; |
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}; |
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pci: pci@80008500 { |
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compatible = "fsl,mpc5121-pci"; |
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device_type = "pci"; |
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interrupts = <1 0x8>; |
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clock-frequency = <0>; |
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#address-cells = <3>; |
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#size-cells = <2>; |
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#interrupt-cells = <1>; |
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clocks = <&clks MPC512x_CLK_PCI>; |
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clock-names = "ipg"; |
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reg = <0x80008500 0x100 /* internal registers */ |
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0x80008300 0x8>; /* config space access registers */ |
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bus-range = <0x0 0x0>; |
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ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000 |
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0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000 |
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0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>; |
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}; |
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};
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