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799 lines
20 KiB
799 lines
20 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright 2007 David Gibson, IBM Corporation. |
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* |
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* Based on earlier code: |
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* Matt Porter <[email protected]> |
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* Copyright 2002-2005 MontaVista Software Inc. |
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* |
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* Eugene Surovegin <[email protected]> or <[email protected]> |
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* Copyright (c) 2003, 2004 Zultys Technologies |
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* |
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* Copyright (C) 2009 Wind River Systems, Inc. |
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* Updated for supporting PPC405EX on Kilauea. |
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* Tiejun Chen <[email protected]> |
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*/ |
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#include <stddef.h> |
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#include "types.h" |
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#include "string.h" |
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#include "stdio.h" |
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#include "ops.h" |
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#include "reg.h" |
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#include "dcr.h" |
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|
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static unsigned long chip_11_errata(unsigned long memsize) |
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{ |
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unsigned long pvr; |
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|
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pvr = mfpvr(); |
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|
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switch (pvr & 0xf0000ff0) { |
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case 0x40000850: |
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case 0x400008d0: |
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case 0x200008d0: |
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memsize -= 4096; |
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break; |
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default: |
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break; |
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} |
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|
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return memsize; |
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} |
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|
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/* Read the 4xx SDRAM controller to get size of system memory. */ |
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void ibm4xx_sdram_fixup_memsize(void) |
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{ |
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int i; |
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unsigned long memsize, bank_config; |
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|
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memsize = 0; |
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for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) { |
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bank_config = SDRAM0_READ(sdram_bxcr[i]); |
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if (bank_config & SDRAM_CONFIG_BANK_ENABLE) |
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memsize += SDRAM_CONFIG_BANK_SIZE(bank_config); |
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} |
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|
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memsize = chip_11_errata(memsize); |
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dt_fixup_memory(0, memsize); |
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} |
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|
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/* Read the 440SPe MQ controller to get size of system memory. */ |
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#define DCRN_MQ0_B0BAS 0x40 |
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#define DCRN_MQ0_B1BAS 0x41 |
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#define DCRN_MQ0_B2BAS 0x42 |
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#define DCRN_MQ0_B3BAS 0x43 |
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|
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static u64 ibm440spe_decode_bas(u32 bas) |
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{ |
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u64 base = ((u64)(bas & 0xFFE00000u)) << 2; |
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|
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/* open coded because I'm paranoid about invalid values */ |
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switch ((bas >> 4) & 0xFFF) { |
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case 0: |
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return 0; |
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case 0xffc: |
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return base + 0x000800000ull; |
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case 0xff8: |
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return base + 0x001000000ull; |
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case 0xff0: |
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return base + 0x002000000ull; |
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case 0xfe0: |
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return base + 0x004000000ull; |
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case 0xfc0: |
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return base + 0x008000000ull; |
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case 0xf80: |
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return base + 0x010000000ull; |
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case 0xf00: |
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return base + 0x020000000ull; |
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case 0xe00: |
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return base + 0x040000000ull; |
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case 0xc00: |
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return base + 0x080000000ull; |
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case 0x800: |
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return base + 0x100000000ull; |
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} |
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printf("Memory BAS value 0x%08x unsupported !\n", bas); |
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return 0; |
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} |
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|
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void ibm440spe_fixup_memsize(void) |
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{ |
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u64 banktop, memsize = 0; |
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|
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/* Ultimately, we should directly construct the memory node |
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* so we are able to handle holes in the memory address space |
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*/ |
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banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B0BAS)); |
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if (banktop > memsize) |
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memsize = banktop; |
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banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B1BAS)); |
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if (banktop > memsize) |
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memsize = banktop; |
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banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B2BAS)); |
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if (banktop > memsize) |
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memsize = banktop; |
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banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B3BAS)); |
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if (banktop > memsize) |
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memsize = banktop; |
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|
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dt_fixup_memory(0, memsize); |
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} |
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|
|
|
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/* 4xx DDR1/2 Denali memory controller support */ |
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/* DDR0 registers */ |
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#define DDR0_02 2 |
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#define DDR0_08 8 |
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#define DDR0_10 10 |
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#define DDR0_14 14 |
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#define DDR0_42 42 |
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#define DDR0_43 43 |
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|
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/* DDR0_02 */ |
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#define DDR_START 0x1 |
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#define DDR_START_SHIFT 0 |
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#define DDR_MAX_CS_REG 0x3 |
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#define DDR_MAX_CS_REG_SHIFT 24 |
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#define DDR_MAX_COL_REG 0xf |
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#define DDR_MAX_COL_REG_SHIFT 16 |
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#define DDR_MAX_ROW_REG 0xf |
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#define DDR_MAX_ROW_REG_SHIFT 8 |
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/* DDR0_08 */ |
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#define DDR_DDR2_MODE 0x1 |
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#define DDR_DDR2_MODE_SHIFT 0 |
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/* DDR0_10 */ |
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#define DDR_CS_MAP 0x3 |
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#define DDR_CS_MAP_SHIFT 8 |
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/* DDR0_14 */ |
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#define DDR_REDUC 0x1 |
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#define DDR_REDUC_SHIFT 16 |
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/* DDR0_42 */ |
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#define DDR_APIN 0x7 |
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#define DDR_APIN_SHIFT 24 |
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/* DDR0_43 */ |
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#define DDR_COL_SZ 0x7 |
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#define DDR_COL_SZ_SHIFT 8 |
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#define DDR_BANK8 0x1 |
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#define DDR_BANK8_SHIFT 0 |
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|
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#define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask)) |
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|
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/* |
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* Some U-Boot versions set the number of chipselects to two |
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* for Sequoia/Rainier boards while they only have one chipselect |
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* hardwired. Hardcode the number of chipselects to one |
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* for sequioa/rainer board models or read the actual value |
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* from the memory controller register DDR0_10 otherwise. |
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*/ |
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static inline u32 ibm4xx_denali_get_cs(void) |
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{ |
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void *devp; |
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char model[64]; |
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u32 val, cs; |
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|
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devp = finddevice("/"); |
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if (!devp) |
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goto read_cs; |
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|
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if (getprop(devp, "model", model, sizeof(model)) <= 0) |
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goto read_cs; |
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|
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model[sizeof(model)-1] = 0; |
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|
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if (!strcmp(model, "amcc,sequoia") || |
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!strcmp(model, "amcc,rainier")) |
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return 1; |
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|
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read_cs: |
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/* get CS value */ |
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val = SDRAM0_READ(DDR0_10); |
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|
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val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT); |
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cs = 0; |
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while (val) { |
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if (val & 0x1) |
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cs++; |
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val = val >> 1; |
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} |
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return cs; |
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} |
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|
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void ibm4xx_denali_fixup_memsize(void) |
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{ |
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u32 val, max_cs, max_col, max_row; |
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u32 cs, col, row, bank, dpath; |
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unsigned long memsize; |
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val = SDRAM0_READ(DDR0_02); |
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if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT)) |
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fatal("DDR controller is not initialized\n"); |
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|
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/* get maximum cs col and row values */ |
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max_cs = DDR_GET_VAL(val, DDR_MAX_CS_REG, DDR_MAX_CS_REG_SHIFT); |
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max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT); |
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max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT); |
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cs = ibm4xx_denali_get_cs(); |
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if (!cs) |
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fatal("No memory installed\n"); |
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if (cs > max_cs) |
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fatal("DDR wrong CS configuration\n"); |
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|
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/* get data path bytes */ |
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val = SDRAM0_READ(DDR0_14); |
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|
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if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT)) |
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dpath = 4; /* 32 bits */ |
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else |
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dpath = 8; /* 64 bits */ |
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|
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/* get address pins (rows) */ |
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val = SDRAM0_READ(DDR0_42); |
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|
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row = DDR_GET_VAL(val, DDR_APIN, DDR_APIN_SHIFT); |
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if (row > max_row) |
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fatal("DDR wrong APIN configuration\n"); |
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row = max_row - row; |
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|
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/* get collomn size and banks */ |
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val = SDRAM0_READ(DDR0_43); |
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col = DDR_GET_VAL(val, DDR_COL_SZ, DDR_COL_SZ_SHIFT); |
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if (col > max_col) |
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fatal("DDR wrong COL configuration\n"); |
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col = max_col - col; |
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|
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if (DDR_GET_VAL(val, DDR_BANK8, DDR_BANK8_SHIFT)) |
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bank = 8; /* 8 banks */ |
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else |
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bank = 4; /* 4 banks */ |
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|
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memsize = cs * (1 << (col+row)) * bank * dpath; |
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memsize = chip_11_errata(memsize); |
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dt_fixup_memory(0, memsize); |
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} |
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|
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#define SPRN_DBCR0_40X 0x3F2 |
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#define SPRN_DBCR0_44X 0x134 |
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#define DBCR0_RST_SYSTEM 0x30000000 |
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|
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void ibm44x_dbcr_reset(void) |
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{ |
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unsigned long tmp; |
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asm volatile ( |
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"mfspr %0,%1\n" |
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"oris %0,%0,%2@h\n" |
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"mtspr %1,%0" |
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: "=&r"(tmp) : "i"(SPRN_DBCR0_44X), "i"(DBCR0_RST_SYSTEM) |
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); |
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|
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} |
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|
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void ibm40x_dbcr_reset(void) |
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{ |
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unsigned long tmp; |
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|
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asm volatile ( |
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"mfspr %0,%1\n" |
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"oris %0,%0,%2@h\n" |
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"mtspr %1,%0" |
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: "=&r"(tmp) : "i"(SPRN_DBCR0_40X), "i"(DBCR0_RST_SYSTEM) |
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); |
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} |
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|
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#define EMAC_RESET 0x20000000 |
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void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1) |
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{ |
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/* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't |
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* do this for us |
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*/ |
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if (emac0) |
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*emac0 = EMAC_RESET; |
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if (emac1) |
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*emac1 = EMAC_RESET; |
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|
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mtdcr(DCRN_MAL0_CFG, MAL_RESET); |
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while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET) |
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; /* loop until reset takes effect */ |
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} |
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|
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/* Read 4xx EBC bus bridge registers to get mappings of the peripheral |
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* banks into the OPB address space */ |
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void ibm4xx_fixup_ebc_ranges(const char *ebc) |
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{ |
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void *devp; |
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u32 bxcr; |
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u32 ranges[EBC_NUM_BANKS*4]; |
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u32 *p = ranges; |
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int i; |
|
|
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for (i = 0; i < EBC_NUM_BANKS; i++) { |
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mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i)); |
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bxcr = mfdcr(DCRN_EBC0_CFGDATA); |
|
|
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if ((bxcr & EBC_BXCR_BU) != EBC_BXCR_BU_OFF) { |
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*p++ = i; |
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*p++ = 0; |
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*p++ = bxcr & EBC_BXCR_BAS; |
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*p++ = EBC_BXCR_BANK_SIZE(bxcr); |
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} |
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} |
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|
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devp = finddevice(ebc); |
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if (! devp) |
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fatal("Couldn't locate EBC node %s\n\r", ebc); |
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|
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setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32)); |
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} |
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|
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/* Calculate 440GP clocks */ |
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void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk) |
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{ |
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u32 sys0 = mfdcr(DCRN_CPC0_SYS0); |
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u32 cr0 = mfdcr(DCRN_CPC0_CR0); |
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u32 cpu, plb, opb, ebc, tb, uart0, uart1, m; |
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u32 opdv = CPC0_SYS0_OPDV(sys0); |
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u32 epdv = CPC0_SYS0_EPDV(sys0); |
|
|
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if (sys0 & CPC0_SYS0_BYPASS) { |
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/* Bypass system PLL */ |
|
cpu = plb = sys_clk; |
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} else { |
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if (sys0 & CPC0_SYS0_EXTSL) |
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/* PerClk */ |
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m = CPC0_SYS0_FWDVB(sys0) * opdv * epdv; |
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else |
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/* CPU clock */ |
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m = CPC0_SYS0_FBDV(sys0) * CPC0_SYS0_FWDVA(sys0); |
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cpu = sys_clk * m / CPC0_SYS0_FWDVA(sys0); |
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plb = sys_clk * m / CPC0_SYS0_FWDVB(sys0); |
|
} |
|
|
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opb = plb / opdv; |
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ebc = opb / epdv; |
|
|
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/* FIXME: Check if this is for all 440GP, or just Ebony */ |
|
if ((mfpvr() & 0xf0000fff) == 0x40000440) |
|
/* Rev. B 440GP, use external system clock */ |
|
tb = sys_clk; |
|
else |
|
/* Rev. C 440GP, errata force us to use internal clock */ |
|
tb = cpu; |
|
|
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if (cr0 & CPC0_CR0_U0EC) |
|
/* External UART clock */ |
|
uart0 = ser_clk; |
|
else |
|
/* Internal UART clock */ |
|
uart0 = plb / CPC0_CR0_UDIV(cr0); |
|
|
|
if (cr0 & CPC0_CR0_U1EC) |
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/* External UART clock */ |
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uart1 = ser_clk; |
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else |
|
/* Internal UART clock */ |
|
uart1 = plb / CPC0_CR0_UDIV(cr0); |
|
|
|
printf("PPC440GP: SysClk = %dMHz (%x)\n\r", |
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(sys_clk + 500000) / 1000000, sys_clk); |
|
|
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dt_fixup_cpu_clocks(cpu, tb, 0); |
|
|
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dt_fixup_clock("/plb", plb); |
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dt_fixup_clock("/plb/opb", opb); |
|
dt_fixup_clock("/plb/opb/ebc", ebc); |
|
dt_fixup_clock("/plb/opb/serial@40000200", uart0); |
|
dt_fixup_clock("/plb/opb/serial@40000300", uart1); |
|
} |
|
|
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#define SPRN_CCR1 0x378 |
|
|
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static inline u32 __fix_zero(u32 v, u32 def) |
|
{ |
|
return v ? v : def; |
|
} |
|
|
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static unsigned int __ibm440eplike_fixup_clocks(unsigned int sys_clk, |
|
unsigned int tmr_clk, |
|
int per_clk_from_opb) |
|
{ |
|
/* PLL config */ |
|
u32 pllc = CPR0_READ(DCRN_CPR0_PLLC); |
|
u32 plld = CPR0_READ(DCRN_CPR0_PLLD); |
|
|
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/* Dividers */ |
|
u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32); |
|
u32 fwdva = __fix_zero((plld >> 16) & 0xf, 16); |
|
u32 fwdvb = __fix_zero((plld >> 8) & 7, 8); |
|
u32 lfbdv = __fix_zero(plld & 0x3f, 64); |
|
u32 pradv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PRIMAD) >> 24) & 7, 8); |
|
u32 prbdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PRIMBD) >> 24) & 7, 8); |
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u32 opbdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_OPBD) >> 24) & 3, 4); |
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u32 perdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PERD) >> 24) & 3, 4); |
|
|
|
/* Input clocks for primary dividers */ |
|
u32 clk_a, clk_b; |
|
|
|
/* Resulting clocks */ |
|
u32 cpu, plb, opb, ebc, vco; |
|
|
|
/* Timebase */ |
|
u32 ccr1, tb = tmr_clk; |
|
|
|
if (pllc & 0x40000000) { |
|
u32 m; |
|
|
|
/* Feedback path */ |
|
switch ((pllc >> 24) & 7) { |
|
case 0: |
|
/* PLLOUTx */ |
|
m = ((pllc & 0x20000000) ? fwdvb : fwdva) * lfbdv; |
|
break; |
|
case 1: |
|
/* CPU */ |
|
m = fwdva * pradv0; |
|
break; |
|
case 5: |
|
/* PERClk */ |
|
m = fwdvb * prbdv0 * opbdv0 * perdv0; |
|
break; |
|
default: |
|
printf("WARNING ! Invalid PLL feedback source !\n"); |
|
goto bypass; |
|
} |
|
m *= fbdv; |
|
vco = sys_clk * m; |
|
clk_a = vco / fwdva; |
|
clk_b = vco / fwdvb; |
|
} else { |
|
bypass: |
|
/* Bypass system PLL */ |
|
vco = 0; |
|
clk_a = clk_b = sys_clk; |
|
} |
|
|
|
cpu = clk_a / pradv0; |
|
plb = clk_b / prbdv0; |
|
opb = plb / opbdv0; |
|
ebc = (per_clk_from_opb ? opb : plb) / perdv0; |
|
|
|
/* Figure out timebase. Either CPU or default TmrClk */ |
|
ccr1 = mfspr(SPRN_CCR1); |
|
|
|
/* If passed a 0 tmr_clk, force CPU clock */ |
|
if (tb == 0) { |
|
ccr1 &= ~0x80u; |
|
mtspr(SPRN_CCR1, ccr1); |
|
} |
|
if ((ccr1 & 0x0080) == 0) |
|
tb = cpu; |
|
|
|
dt_fixup_cpu_clocks(cpu, tb, 0); |
|
dt_fixup_clock("/plb", plb); |
|
dt_fixup_clock("/plb/opb", opb); |
|
dt_fixup_clock("/plb/opb/ebc", ebc); |
|
|
|
return plb; |
|
} |
|
|
|
static void eplike_fixup_uart_clk(int index, const char *path, |
|
unsigned int ser_clk, |
|
unsigned int plb_clk) |
|
{ |
|
unsigned int sdr; |
|
unsigned int clock; |
|
|
|
switch (index) { |
|
case 0: |
|
sdr = SDR0_READ(DCRN_SDR0_UART0); |
|
break; |
|
case 1: |
|
sdr = SDR0_READ(DCRN_SDR0_UART1); |
|
break; |
|
case 2: |
|
sdr = SDR0_READ(DCRN_SDR0_UART2); |
|
break; |
|
case 3: |
|
sdr = SDR0_READ(DCRN_SDR0_UART3); |
|
break; |
|
default: |
|
return; |
|
} |
|
|
|
if (sdr & 0x00800000u) |
|
clock = ser_clk; |
|
else |
|
clock = plb_clk / __fix_zero(sdr & 0xff, 256); |
|
|
|
dt_fixup_clock(path, clock); |
|
} |
|
|
|
void ibm440ep_fixup_clocks(unsigned int sys_clk, |
|
unsigned int ser_clk, |
|
unsigned int tmr_clk) |
|
{ |
|
unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 0); |
|
|
|
/* serial clocks need fixup based on int/ext */ |
|
eplike_fixup_uart_clk(0, "/plb/opb/serial@ef600300", ser_clk, plb_clk); |
|
eplike_fixup_uart_clk(1, "/plb/opb/serial@ef600400", ser_clk, plb_clk); |
|
eplike_fixup_uart_clk(2, "/plb/opb/serial@ef600500", ser_clk, plb_clk); |
|
eplike_fixup_uart_clk(3, "/plb/opb/serial@ef600600", ser_clk, plb_clk); |
|
} |
|
|
|
void ibm440gx_fixup_clocks(unsigned int sys_clk, |
|
unsigned int ser_clk, |
|
unsigned int tmr_clk) |
|
{ |
|
unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1); |
|
|
|
/* serial clocks need fixup based on int/ext */ |
|
eplike_fixup_uart_clk(0, "/plb/opb/serial@40000200", ser_clk, plb_clk); |
|
eplike_fixup_uart_clk(1, "/plb/opb/serial@40000300", ser_clk, plb_clk); |
|
} |
|
|
|
void ibm440spe_fixup_clocks(unsigned int sys_clk, |
|
unsigned int ser_clk, |
|
unsigned int tmr_clk) |
|
{ |
|
unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1); |
|
|
|
/* serial clocks need fixup based on int/ext */ |
|
eplike_fixup_uart_clk(0, "/plb/opb/serial@f0000200", ser_clk, plb_clk); |
|
eplike_fixup_uart_clk(1, "/plb/opb/serial@f0000300", ser_clk, plb_clk); |
|
eplike_fixup_uart_clk(2, "/plb/opb/serial@f0000600", ser_clk, plb_clk); |
|
} |
|
|
|
void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk) |
|
{ |
|
u32 pllmr = mfdcr(DCRN_CPC0_PLLMR); |
|
u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0); |
|
u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1); |
|
u32 psr = mfdcr(DCRN_405_CPC0_PSR); |
|
u32 cpu, plb, opb, ebc, tb, uart0, uart1, m; |
|
u32 fwdv, fwdvb, fbdv, cbdv, opdv, epdv, ppdv, udiv; |
|
|
|
fwdv = (8 - ((pllmr & 0xe0000000) >> 29)); |
|
fbdv = (pllmr & 0x1e000000) >> 25; |
|
if (fbdv == 0) |
|
fbdv = 16; |
|
cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */ |
|
opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */ |
|
ppdv = ((pllmr & 0x00006000) >> 13) + 1; /* PLB:PCI */ |
|
epdv = ((pllmr & 0x00001800) >> 11) + 2; /* PLB:EBC */ |
|
udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1; |
|
|
|
/* check for 405GPr */ |
|
if ((mfpvr() & 0xfffffff0) == (0x50910951 & 0xfffffff0)) { |
|
fwdvb = 8 - (pllmr & 0x00000007); |
|
if (!(psr & 0x00001000)) /* PCI async mode enable == 0 */ |
|
if (psr & 0x00000020) /* New mode enable */ |
|
m = fwdvb * 2 * ppdv; |
|
else |
|
m = fwdvb * cbdv * ppdv; |
|
else if (psr & 0x00000020) /* New mode enable */ |
|
if (psr & 0x00000800) /* PerClk synch mode */ |
|
m = fwdvb * 2 * epdv; |
|
else |
|
m = fbdv * fwdv; |
|
else if (epdv == fbdv) |
|
m = fbdv * cbdv * epdv; |
|
else |
|
m = fbdv * fwdvb * cbdv; |
|
|
|
cpu = sys_clk * m / fwdv; |
|
plb = sys_clk * m / (fwdvb * cbdv); |
|
} else { |
|
m = fwdv * fbdv * cbdv; |
|
cpu = sys_clk * m / fwdv; |
|
plb = cpu / cbdv; |
|
} |
|
opb = plb / opdv; |
|
ebc = plb / epdv; |
|
|
|
if (cpc0_cr0 & 0x80) |
|
/* uart0 uses the external clock */ |
|
uart0 = ser_clk; |
|
else |
|
uart0 = cpu / udiv; |
|
|
|
if (cpc0_cr0 & 0x40) |
|
/* uart1 uses the external clock */ |
|
uart1 = ser_clk; |
|
else |
|
uart1 = cpu / udiv; |
|
|
|
/* setup the timebase clock to tick at the cpu frequency */ |
|
cpc0_cr1 = cpc0_cr1 & ~0x00800000; |
|
mtdcr(DCRN_405_CPC0_CR1, cpc0_cr1); |
|
tb = cpu; |
|
|
|
dt_fixup_cpu_clocks(cpu, tb, 0); |
|
dt_fixup_clock("/plb", plb); |
|
dt_fixup_clock("/plb/opb", opb); |
|
dt_fixup_clock("/plb/ebc", ebc); |
|
dt_fixup_clock("/plb/opb/serial@ef600300", uart0); |
|
dt_fixup_clock("/plb/opb/serial@ef600400", uart1); |
|
} |
|
|
|
|
|
void ibm405ep_fixup_clocks(unsigned int sys_clk) |
|
{ |
|
u32 pllmr0 = mfdcr(DCRN_CPC0_PLLMR0); |
|
u32 pllmr1 = mfdcr(DCRN_CPC0_PLLMR1); |
|
u32 cpc0_ucr = mfdcr(DCRN_CPC0_UCR); |
|
u32 cpu, plb, opb, ebc, uart0, uart1; |
|
u32 fwdva, fwdvb, fbdv, cbdv, opdv, epdv; |
|
u32 pllmr0_ccdv, tb, m; |
|
|
|
fwdva = 8 - ((pllmr1 & 0x00070000) >> 16); |
|
fwdvb = 8 - ((pllmr1 & 0x00007000) >> 12); |
|
fbdv = (pllmr1 & 0x00f00000) >> 20; |
|
if (fbdv == 0) |
|
fbdv = 16; |
|
|
|
cbdv = ((pllmr0 & 0x00030000) >> 16) + 1; /* CPU:PLB */ |
|
epdv = ((pllmr0 & 0x00000300) >> 8) + 2; /* PLB:EBC */ |
|
opdv = ((pllmr0 & 0x00003000) >> 12) + 1; /* PLB:OPB */ |
|
|
|
m = fbdv * fwdvb; |
|
|
|
pllmr0_ccdv = ((pllmr0 & 0x00300000) >> 20) + 1; |
|
if (pllmr1 & 0x80000000) |
|
cpu = sys_clk * m / (fwdva * pllmr0_ccdv); |
|
else |
|
cpu = sys_clk / pllmr0_ccdv; |
|
|
|
plb = cpu / cbdv; |
|
opb = plb / opdv; |
|
ebc = plb / epdv; |
|
tb = cpu; |
|
uart0 = cpu / (cpc0_ucr & 0x0000007f); |
|
uart1 = cpu / ((cpc0_ucr & 0x00007f00) >> 8); |
|
|
|
dt_fixup_cpu_clocks(cpu, tb, 0); |
|
dt_fixup_clock("/plb", plb); |
|
dt_fixup_clock("/plb/opb", opb); |
|
dt_fixup_clock("/plb/ebc", ebc); |
|
dt_fixup_clock("/plb/opb/serial@ef600300", uart0); |
|
dt_fixup_clock("/plb/opb/serial@ef600400", uart1); |
|
} |
|
|
|
static u8 ibm405ex_fwdv_multi_bits[] = { |
|
/* values for: 1 - 16 */ |
|
0x01, 0x02, 0x0e, 0x09, 0x04, 0x0b, 0x10, 0x0d, 0x0c, 0x05, |
|
0x06, 0x0f, 0x0a, 0x07, 0x08, 0x03 |
|
}; |
|
|
|
u32 ibm405ex_get_fwdva(unsigned long cpr_fwdv) |
|
{ |
|
u32 index; |
|
|
|
for (index = 0; index < ARRAY_SIZE(ibm405ex_fwdv_multi_bits); index++) |
|
if (cpr_fwdv == (u32)ibm405ex_fwdv_multi_bits[index]) |
|
return index + 1; |
|
|
|
return 0; |
|
} |
|
|
|
static u8 ibm405ex_fbdv_multi_bits[] = { |
|
/* values for: 1 - 100 */ |
|
0x00, 0xff, 0x7e, 0xfd, 0x7a, 0xf5, 0x6a, 0xd5, 0x2a, 0xd4, |
|
0x29, 0xd3, 0x26, 0xcc, 0x19, 0xb3, 0x67, 0xce, 0x1d, 0xbb, |
|
0x77, 0xee, 0x5d, 0xba, 0x74, 0xe9, 0x52, 0xa5, 0x4b, 0x96, |
|
0x2c, 0xd8, 0x31, 0xe3, 0x46, 0x8d, 0x1b, 0xb7, 0x6f, 0xde, |
|
0x3d, 0xfb, 0x76, 0xed, 0x5a, 0xb5, 0x6b, 0xd6, 0x2d, 0xdb, |
|
0x36, 0xec, 0x59, 0xb2, 0x64, 0xc9, 0x12, 0xa4, 0x48, 0x91, |
|
0x23, 0xc7, 0x0e, 0x9c, 0x38, 0xf0, 0x61, 0xc2, 0x05, 0x8b, |
|
0x17, 0xaf, 0x5f, 0xbe, 0x7c, 0xf9, 0x72, 0xe5, 0x4a, 0x95, |
|
0x2b, 0xd7, 0x2e, 0xdc, 0x39, 0xf3, 0x66, 0xcd, 0x1a, 0xb4, |
|
0x68, 0xd1, 0x22, 0xc4, 0x09, 0x93, 0x27, 0xcf, 0x1e, 0xbc, |
|
/* values for: 101 - 200 */ |
|
0x78, 0xf1, 0x62, 0xc5, 0x0a, 0x94, 0x28, 0xd0, 0x21, 0xc3, |
|
0x06, 0x8c, 0x18, 0xb0, 0x60, 0xc1, 0x02, 0x84, 0x08, 0x90, |
|
0x20, 0xc0, 0x01, 0x83, 0x07, 0x8f, 0x1f, 0xbf, 0x7f, 0xfe, |
|
0x7d, 0xfa, 0x75, 0xea, 0x55, 0xaa, 0x54, 0xa9, 0x53, 0xa6, |
|
0x4c, 0x99, 0x33, 0xe7, 0x4e, 0x9d, 0x3b, 0xf7, 0x6e, 0xdd, |
|
0x3a, 0xf4, 0x69, 0xd2, 0x25, 0xcb, 0x16, 0xac, 0x58, 0xb1, |
|
0x63, 0xc6, 0x0d, 0x9b, 0x37, 0xef, 0x5e, 0xbd, 0x7b, 0xf6, |
|
0x6d, 0xda, 0x35, 0xeb, 0x56, 0xad, 0x5b, 0xb6, 0x6c, 0xd9, |
|
0x32, 0xe4, 0x49, 0x92, 0x24, 0xc8, 0x11, 0xa3, 0x47, 0x8e, |
|
0x1c, 0xb8, 0x70, 0xe1, 0x42, 0x85, 0x0b, 0x97, 0x2f, 0xdf, |
|
/* values for: 201 - 255 */ |
|
0x3e, 0xfc, 0x79, 0xf2, 0x65, 0xca, 0x15, 0xab, 0x57, 0xae, |
|
0x5c, 0xb9, 0x73, 0xe6, 0x4d, 0x9a, 0x34, 0xe8, 0x51, 0xa2, |
|
0x44, 0x89, 0x13, 0xa7, 0x4f, 0x9e, 0x3c, 0xf8, 0x71, 0xe2, |
|
0x45, 0x8a, 0x14, 0xa8, 0x50, 0xa1, 0x43, 0x86, 0x0c, 0x98, |
|
0x30, 0xe0, 0x41, 0x82, 0x04, 0x88, 0x10, 0xa0, 0x40, 0x81, |
|
0x03, 0x87, 0x0f, 0x9f, 0x3f /* END */ |
|
}; |
|
|
|
u32 ibm405ex_get_fbdv(unsigned long cpr_fbdv) |
|
{ |
|
u32 index; |
|
|
|
for (index = 0; index < ARRAY_SIZE(ibm405ex_fbdv_multi_bits); index++) |
|
if (cpr_fbdv == (u32)ibm405ex_fbdv_multi_bits[index]) |
|
return index + 1; |
|
|
|
return 0; |
|
} |
|
|
|
void ibm405ex_fixup_clocks(unsigned int sys_clk, unsigned int uart_clk) |
|
{ |
|
/* PLL config */ |
|
u32 pllc = CPR0_READ(DCRN_CPR0_PLLC); |
|
u32 plld = CPR0_READ(DCRN_CPR0_PLLD); |
|
u32 cpud = CPR0_READ(DCRN_CPR0_PRIMAD); |
|
u32 plbd = CPR0_READ(DCRN_CPR0_PRIMBD); |
|
u32 opbd = CPR0_READ(DCRN_CPR0_OPBD); |
|
u32 perd = CPR0_READ(DCRN_CPR0_PERD); |
|
|
|
/* Dividers */ |
|
u32 fbdv = ibm405ex_get_fbdv(__fix_zero((plld >> 24) & 0xff, 1)); |
|
|
|
u32 fwdva = ibm405ex_get_fwdva(__fix_zero((plld >> 16) & 0x0f, 1)); |
|
|
|
u32 cpudv0 = __fix_zero((cpud >> 24) & 7, 8); |
|
|
|
/* PLBDV0 is hardwared to 010. */ |
|
u32 plbdv0 = 2; |
|
u32 plb2xdv0 = __fix_zero((plbd >> 16) & 7, 8); |
|
|
|
u32 opbdv0 = __fix_zero((opbd >> 24) & 3, 4); |
|
|
|
u32 perdv0 = __fix_zero((perd >> 24) & 3, 4); |
|
|
|
/* Resulting clocks */ |
|
u32 cpu, plb, opb, ebc, vco, tb, uart0, uart1; |
|
|
|
/* PLL's VCO is the source for primary forward ? */ |
|
if (pllc & 0x40000000) { |
|
u32 m; |
|
|
|
/* Feedback path */ |
|
switch ((pllc >> 24) & 7) { |
|
case 0: |
|
/* PLLOUTx */ |
|
m = fbdv; |
|
break; |
|
case 1: |
|
/* CPU */ |
|
m = fbdv * fwdva * cpudv0; |
|
break; |
|
case 5: |
|
/* PERClk */ |
|
m = fbdv * fwdva * plb2xdv0 * plbdv0 * opbdv0 * perdv0; |
|
break; |
|
default: |
|
printf("WARNING ! Invalid PLL feedback source !\n"); |
|
goto bypass; |
|
} |
|
|
|
vco = (unsigned int)(sys_clk * m); |
|
} else { |
|
bypass: |
|
/* Bypass system PLL */ |
|
vco = 0; |
|
} |
|
|
|
/* CPU = VCO / ( FWDVA x CPUDV0) */ |
|
cpu = vco / (fwdva * cpudv0); |
|
/* PLB = VCO / ( FWDVA x PLB2XDV0 x PLBDV0) */ |
|
plb = vco / (fwdva * plb2xdv0 * plbdv0); |
|
/* OPB = PLB / OPBDV0 */ |
|
opb = plb / opbdv0; |
|
/* EBC = OPB / PERDV0 */ |
|
ebc = opb / perdv0; |
|
|
|
tb = cpu; |
|
uart0 = uart1 = uart_clk; |
|
|
|
dt_fixup_cpu_clocks(cpu, tb, 0); |
|
dt_fixup_clock("/plb", plb); |
|
dt_fixup_clock("/plb/opb", opb); |
|
dt_fixup_clock("/plb/opb/ebc", ebc); |
|
dt_fixup_clock("/plb/opb/serial@ef600200", uart0); |
|
dt_fixup_clock("/plb/opb/serial@ef600300", uart1); |
|
}
|
|
|