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1430 lines
38 KiB
1430 lines
38 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Linux/PA-RISC Project (http://www.parisc-linux.org/) |
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* |
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* Floating-point emulation code |
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* Copyright (C) 2001 Hewlett-Packard (Paul Bame) <[email protected]> |
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*/ |
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/* |
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* BEGIN_DESC |
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* |
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* File: |
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* @(#) pa/fp/fpudispatch.c $Revision: 1.1 $ |
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* |
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* Purpose: |
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* <<please update with a synopsis of the functionality provided by this file>> |
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* |
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* External Interfaces: |
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* <<the following list was autogenerated, please review>> |
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* emfpudispatch(ir, dummy1, dummy2, fpregs) |
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* fpudispatch(ir, excp_code, holder, fpregs) |
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* |
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* Internal Interfaces: |
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* <<the following list was autogenerated, please review>> |
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* static u_int decode_06(u_int, u_int *) |
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* static u_int decode_0c(u_int, u_int, u_int, u_int *) |
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* static u_int decode_0e(u_int, u_int, u_int, u_int *) |
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* static u_int decode_26(u_int, u_int *) |
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* static u_int decode_2e(u_int, u_int *) |
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* static void update_status_cbit(u_int *, u_int, u_int, u_int) |
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* |
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* Theory: |
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* <<please update with a overview of the operation of this file>> |
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* |
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* END_DESC |
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*/ |
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#define FPUDEBUG 0 |
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#include "float.h" |
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#include <linux/bug.h> |
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#include <linux/kernel.h> |
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#include <asm/processor.h> |
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/* #include <sys/debug.h> */ |
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/* #include <machine/sys/mdep_private.h> */ |
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#define COPR_INST 0x30000000 |
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/* |
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* definition of extru macro. If pos and len are constants, the compiler |
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* will generate an extru instruction when optimized |
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*/ |
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#define extru(r,pos,len) (((r) >> (31-(pos))) & (( 1 << (len)) - 1)) |
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/* definitions of bit field locations in the instruction */ |
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#define fpmajorpos 5 |
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#define fpr1pos 10 |
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#define fpr2pos 15 |
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#define fptpos 31 |
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#define fpsubpos 18 |
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#define fpclass1subpos 16 |
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#define fpclasspos 22 |
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#define fpfmtpos 20 |
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#define fpdfpos 18 |
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#define fpnulpos 26 |
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/* |
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* the following are the extra bits for the 0E major op |
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*/ |
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#define fpxr1pos 24 |
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#define fpxr2pos 19 |
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#define fpxtpos 25 |
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#define fpxpos 23 |
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#define fp0efmtpos 20 |
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/* |
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* the following are for the multi-ops |
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*/ |
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#define fprm1pos 10 |
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#define fprm2pos 15 |
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#define fptmpos 31 |
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#define fprapos 25 |
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#define fptapos 20 |
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#define fpmultifmt 26 |
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/* |
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* the following are for the fused FP instructions |
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*/ |
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/* fprm1pos 10 */ |
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/* fprm2pos 15 */ |
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#define fpraupos 18 |
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#define fpxrm2pos 19 |
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/* fpfmtpos 20 */ |
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#define fpralpos 23 |
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#define fpxrm1pos 24 |
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/* fpxtpos 25 */ |
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#define fpfusedsubop 26 |
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/* fptpos 31 */ |
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/* |
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* offset to constant zero in the FP emulation registers |
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*/ |
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#define fpzeroreg (32*sizeof(double)/sizeof(u_int)) |
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/* |
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* extract the major opcode from the instruction |
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*/ |
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#define get_major(op) extru(op,fpmajorpos,6) |
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/* |
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* extract the two bit class field from the FP instruction. The class is at bit |
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* positions 21-22 |
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*/ |
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#define get_class(op) extru(op,fpclasspos,2) |
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/* |
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* extract the 3 bit subop field. For all but class 1 instructions, it is |
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* located at bit positions 16-18 |
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*/ |
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#define get_subop(op) extru(op,fpsubpos,3) |
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/* |
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* extract the 2 or 3 bit subop field from class 1 instructions. It is located |
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* at bit positions 15-16 (PA1.1) or 14-16 (PA2.0) |
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*/ |
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#define get_subop1_PA1_1(op) extru(op,fpclass1subpos,2) /* PA89 (1.1) fmt */ |
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#define get_subop1_PA2_0(op) extru(op,fpclass1subpos,3) /* PA 2.0 fmt */ |
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/* definitions of unimplemented exceptions */ |
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#define MAJOR_0C_EXCP 0x09 |
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#define MAJOR_0E_EXCP 0x0b |
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#define MAJOR_06_EXCP 0x03 |
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#define MAJOR_26_EXCP 0x23 |
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#define MAJOR_2E_EXCP 0x2b |
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#define PA83_UNIMP_EXCP 0x01 |
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/* |
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* Special Defines for TIMEX specific code |
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*/ |
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#define FPU_TYPE_FLAG_POS (EM_FPU_TYPE_OFFSET>>2) |
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#define TIMEX_ROLEX_FPU_MASK (TIMEX_EXTEN_FLAG|ROLEX_EXTEN_FLAG) |
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/* |
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* Static function definitions |
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*/ |
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#define _PROTOTYPES |
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#if defined(_PROTOTYPES) || defined(_lint) |
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static u_int decode_0c(u_int, u_int, u_int, u_int *); |
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static u_int decode_0e(u_int, u_int, u_int, u_int *); |
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static u_int decode_06(u_int, u_int *); |
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static u_int decode_26(u_int, u_int *); |
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static u_int decode_2e(u_int, u_int *); |
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static void update_status_cbit(u_int *, u_int, u_int, u_int); |
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#else /* !_PROTOTYPES&&!_lint */ |
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static u_int decode_0c(); |
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static u_int decode_0e(); |
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static u_int decode_06(); |
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static u_int decode_26(); |
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static u_int decode_2e(); |
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static void update_status_cbit(); |
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#endif /* _PROTOTYPES&&!_lint */ |
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#define VASSERT(x) |
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static void parisc_linux_get_fpu_type(u_int fpregs[]) |
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{ |
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/* on pa-linux the fpu type is not filled in by the |
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* caller; it is constructed here |
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*/ |
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if (boot_cpu_data.cpu_type == pcxs) |
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fpregs[FPU_TYPE_FLAG_POS] = TIMEX_EXTEN_FLAG; |
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else if (boot_cpu_data.cpu_type == pcxt || |
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boot_cpu_data.cpu_type == pcxt_) |
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fpregs[FPU_TYPE_FLAG_POS] = ROLEX_EXTEN_FLAG; |
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else if (boot_cpu_data.cpu_type >= pcxu) |
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fpregs[FPU_TYPE_FLAG_POS] = PA2_0_FPU_FLAG; |
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} |
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/* |
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* this routine will decode the excepting floating point instruction and |
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* call the appropriate emulation routine. |
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* It is called by decode_fpu with the following parameters: |
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* fpudispatch(current_ir, unimplemented_code, 0, &Fpu_register) |
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* where current_ir is the instruction to be emulated, |
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* unimplemented_code is the exception_code that the hardware generated |
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* and &Fpu_register is the address of emulated FP reg 0. |
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*/ |
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u_int |
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fpudispatch(u_int ir, u_int excp_code, u_int holder, u_int fpregs[]) |
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{ |
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u_int class, subop; |
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u_int fpu_type_flags; |
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/* All FP emulation code assumes that ints are 4-bytes in length */ |
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VASSERT(sizeof(int) == 4); |
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parisc_linux_get_fpu_type(fpregs); |
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fpu_type_flags=fpregs[FPU_TYPE_FLAG_POS]; /* get fpu type flags */ |
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class = get_class(ir); |
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if (class == 1) { |
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if (fpu_type_flags & PA2_0_FPU_FLAG) |
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subop = get_subop1_PA2_0(ir); |
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else |
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subop = get_subop1_PA1_1(ir); |
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} |
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else |
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subop = get_subop(ir); |
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if (FPUDEBUG) printk("class %d subop %d\n", class, subop); |
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switch (excp_code) { |
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case MAJOR_0C_EXCP: |
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case PA83_UNIMP_EXCP: |
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return(decode_0c(ir,class,subop,fpregs)); |
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case MAJOR_0E_EXCP: |
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return(decode_0e(ir,class,subop,fpregs)); |
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case MAJOR_06_EXCP: |
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return(decode_06(ir,fpregs)); |
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case MAJOR_26_EXCP: |
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return(decode_26(ir,fpregs)); |
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case MAJOR_2E_EXCP: |
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return(decode_2e(ir,fpregs)); |
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default: |
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/* "crashme Night Gallery painting nr 2. (asm_crash.s). |
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* This was fixed for multi-user kernels, but |
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* workstation kernels had a panic here. This allowed |
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* any arbitrary user to panic the kernel by executing |
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* setting the FP exception registers to strange values |
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* and generating an emulation trap. The emulation and |
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* exception code must never be able to panic the |
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* kernel. |
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*/ |
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return(UNIMPLEMENTEDEXCEPTION); |
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} |
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} |
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/* |
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* this routine is called by $emulation_trap to emulate a coprocessor |
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* instruction if one doesn't exist |
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*/ |
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u_int |
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emfpudispatch(u_int ir, u_int dummy1, u_int dummy2, u_int fpregs[]) |
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{ |
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u_int class, subop, major; |
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u_int fpu_type_flags; |
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/* All FP emulation code assumes that ints are 4-bytes in length */ |
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VASSERT(sizeof(int) == 4); |
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fpu_type_flags=fpregs[FPU_TYPE_FLAG_POS]; /* get fpu type flags */ |
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major = get_major(ir); |
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class = get_class(ir); |
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if (class == 1) { |
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if (fpu_type_flags & PA2_0_FPU_FLAG) |
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subop = get_subop1_PA2_0(ir); |
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else |
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subop = get_subop1_PA1_1(ir); |
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} |
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else |
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subop = get_subop(ir); |
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switch (major) { |
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case 0x0C: |
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return(decode_0c(ir,class,subop,fpregs)); |
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case 0x0E: |
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return(decode_0e(ir,class,subop,fpregs)); |
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case 0x06: |
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return(decode_06(ir,fpregs)); |
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case 0x26: |
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return(decode_26(ir,fpregs)); |
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case 0x2E: |
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return(decode_2e(ir,fpregs)); |
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default: |
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return(PA83_UNIMP_EXCP); |
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} |
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} |
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static u_int |
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decode_0c(u_int ir, u_int class, u_int subop, u_int fpregs[]) |
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{ |
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u_int r1,r2,t; /* operand register offsets */ |
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u_int fmt; /* also sf for class 1 conversions */ |
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u_int df; /* for class 1 conversions */ |
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u_int *status; |
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u_int retval, local_status; |
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u_int fpu_type_flags; |
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if (ir == COPR_INST) { |
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fpregs[0] = EMULATION_VERSION << 11; |
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return(NOEXCEPTION); |
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} |
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status = &fpregs[0]; /* fp status register */ |
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local_status = fpregs[0]; /* and local copy */ |
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r1 = extru(ir,fpr1pos,5) * sizeof(double)/sizeof(u_int); |
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if (r1 == 0) /* map fr0 source to constant zero */ |
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r1 = fpzeroreg; |
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t = extru(ir,fptpos,5) * sizeof(double)/sizeof(u_int); |
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if (t == 0 && class != 2) /* don't allow fr0 as a dest */ |
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return(MAJOR_0C_EXCP); |
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fmt = extru(ir,fpfmtpos,2); /* get fmt completer */ |
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switch (class) { |
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case 0: |
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switch (subop) { |
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case 0: /* COPR 0,0 emulated above*/ |
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case 1: |
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return(MAJOR_0C_EXCP); |
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case 2: /* FCPY */ |
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switch (fmt) { |
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case 2: /* illegal */ |
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return(MAJOR_0C_EXCP); |
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case 3: /* quad */ |
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t &= ~3; /* force to even reg #s */ |
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r1 &= ~3; |
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fpregs[t+3] = fpregs[r1+3]; |
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fpregs[t+2] = fpregs[r1+2]; |
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case 1: /* double */ |
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fpregs[t+1] = fpregs[r1+1]; |
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case 0: /* single */ |
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fpregs[t] = fpregs[r1]; |
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return(NOEXCEPTION); |
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} |
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case 3: /* FABS */ |
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switch (fmt) { |
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case 2: /* illegal */ |
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return(MAJOR_0C_EXCP); |
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case 3: /* quad */ |
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t &= ~3; /* force to even reg #s */ |
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r1 &= ~3; |
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fpregs[t+3] = fpregs[r1+3]; |
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fpregs[t+2] = fpregs[r1+2]; |
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case 1: /* double */ |
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fpregs[t+1] = fpregs[r1+1]; |
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case 0: /* single */ |
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/* copy and clear sign bit */ |
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fpregs[t] = fpregs[r1] & 0x7fffffff; |
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return(NOEXCEPTION); |
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} |
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case 6: /* FNEG */ |
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switch (fmt) { |
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case 2: /* illegal */ |
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return(MAJOR_0C_EXCP); |
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case 3: /* quad */ |
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t &= ~3; /* force to even reg #s */ |
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r1 &= ~3; |
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fpregs[t+3] = fpregs[r1+3]; |
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fpregs[t+2] = fpregs[r1+2]; |
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case 1: /* double */ |
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fpregs[t+1] = fpregs[r1+1]; |
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case 0: /* single */ |
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/* copy and invert sign bit */ |
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fpregs[t] = fpregs[r1] ^ 0x80000000; |
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return(NOEXCEPTION); |
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} |
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case 7: /* FNEGABS */ |
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switch (fmt) { |
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case 2: /* illegal */ |
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return(MAJOR_0C_EXCP); |
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case 3: /* quad */ |
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t &= ~3; /* force to even reg #s */ |
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r1 &= ~3; |
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fpregs[t+3] = fpregs[r1+3]; |
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fpregs[t+2] = fpregs[r1+2]; |
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case 1: /* double */ |
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fpregs[t+1] = fpregs[r1+1]; |
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case 0: /* single */ |
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/* copy and set sign bit */ |
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fpregs[t] = fpregs[r1] | 0x80000000; |
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return(NOEXCEPTION); |
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} |
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case 4: /* FSQRT */ |
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switch (fmt) { |
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case 0: |
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return(sgl_fsqrt(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 1: |
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return(dbl_fsqrt(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 2: |
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case 3: /* quad not implemented */ |
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return(MAJOR_0C_EXCP); |
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} |
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case 5: /* FRND */ |
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switch (fmt) { |
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case 0: |
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return(sgl_frnd(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 1: |
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return(dbl_frnd(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 2: |
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case 3: /* quad not implemented */ |
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return(MAJOR_0C_EXCP); |
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} |
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} /* end of switch (subop) */ |
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case 1: /* class 1 */ |
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df = extru(ir,fpdfpos,2); /* get dest format */ |
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if ((df & 2) || (fmt & 2)) { |
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/* |
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* fmt's 2 and 3 are illegal of not implemented |
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* quad conversions |
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*/ |
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return(MAJOR_0C_EXCP); |
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} |
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/* |
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* encode source and dest formats into 2 bits. |
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* high bit is source, low bit is dest. |
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* bit = 1 --> double precision |
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*/ |
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fmt = (fmt << 1) | df; |
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switch (subop) { |
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case 0: /* FCNVFF */ |
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switch(fmt) { |
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case 0: /* sgl/sgl */ |
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return(MAJOR_0C_EXCP); |
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case 1: /* sgl/dbl */ |
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return(sgl_to_dbl_fcnvff(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 2: /* dbl/sgl */ |
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return(dbl_to_sgl_fcnvff(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 3: /* dbl/dbl */ |
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return(MAJOR_0C_EXCP); |
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} |
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case 1: /* FCNVXF */ |
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switch(fmt) { |
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case 0: /* sgl/sgl */ |
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return(sgl_to_sgl_fcnvxf(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 1: /* sgl/dbl */ |
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return(sgl_to_dbl_fcnvxf(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 2: /* dbl/sgl */ |
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return(dbl_to_sgl_fcnvxf(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 3: /* dbl/dbl */ |
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return(dbl_to_dbl_fcnvxf(&fpregs[r1],0, |
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&fpregs[t],status)); |
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} |
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case 2: /* FCNVFX */ |
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switch(fmt) { |
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case 0: /* sgl/sgl */ |
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return(sgl_to_sgl_fcnvfx(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 1: /* sgl/dbl */ |
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return(sgl_to_dbl_fcnvfx(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 2: /* dbl/sgl */ |
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return(dbl_to_sgl_fcnvfx(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 3: /* dbl/dbl */ |
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return(dbl_to_dbl_fcnvfx(&fpregs[r1],0, |
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&fpregs[t],status)); |
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} |
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case 3: /* FCNVFXT */ |
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switch(fmt) { |
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case 0: /* sgl/sgl */ |
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return(sgl_to_sgl_fcnvfxt(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 1: /* sgl/dbl */ |
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return(sgl_to_dbl_fcnvfxt(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 2: /* dbl/sgl */ |
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return(dbl_to_sgl_fcnvfxt(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 3: /* dbl/dbl */ |
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return(dbl_to_dbl_fcnvfxt(&fpregs[r1],0, |
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&fpregs[t],status)); |
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} |
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case 5: /* FCNVUF (PA2.0 only) */ |
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switch(fmt) { |
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case 0: /* sgl/sgl */ |
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return(sgl_to_sgl_fcnvuf(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 1: /* sgl/dbl */ |
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return(sgl_to_dbl_fcnvuf(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 2: /* dbl/sgl */ |
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return(dbl_to_sgl_fcnvuf(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 3: /* dbl/dbl */ |
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return(dbl_to_dbl_fcnvuf(&fpregs[r1],0, |
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&fpregs[t],status)); |
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} |
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case 6: /* FCNVFU (PA2.0 only) */ |
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switch(fmt) { |
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case 0: /* sgl/sgl */ |
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return(sgl_to_sgl_fcnvfu(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 1: /* sgl/dbl */ |
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return(sgl_to_dbl_fcnvfu(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 2: /* dbl/sgl */ |
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return(dbl_to_sgl_fcnvfu(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 3: /* dbl/dbl */ |
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return(dbl_to_dbl_fcnvfu(&fpregs[r1],0, |
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&fpregs[t],status)); |
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} |
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case 7: /* FCNVFUT (PA2.0 only) */ |
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switch(fmt) { |
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case 0: /* sgl/sgl */ |
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return(sgl_to_sgl_fcnvfut(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 1: /* sgl/dbl */ |
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return(sgl_to_dbl_fcnvfut(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 2: /* dbl/sgl */ |
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return(dbl_to_sgl_fcnvfut(&fpregs[r1],0, |
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&fpregs[t],status)); |
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case 3: /* dbl/dbl */ |
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return(dbl_to_dbl_fcnvfut(&fpregs[r1],0, |
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&fpregs[t],status)); |
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} |
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case 4: /* undefined */ |
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return(MAJOR_0C_EXCP); |
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} /* end of switch subop */ |
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|
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case 2: /* class 2 */ |
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fpu_type_flags=fpregs[FPU_TYPE_FLAG_POS]; |
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r2 = extru(ir, fpr2pos, 5) * sizeof(double)/sizeof(u_int); |
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if (r2 == 0) |
|
r2 = fpzeroreg; |
|
if (fpu_type_flags & PA2_0_FPU_FLAG) { |
|
/* FTEST if nullify bit set, otherwise FCMP */ |
|
if (extru(ir, fpnulpos, 1)) { /* FTEST */ |
|
switch (fmt) { |
|
case 0: |
|
/* |
|
* arg0 is not used |
|
* second param is the t field used for |
|
* ftest,acc and ftest,rej |
|
* third param is the subop (y-field) |
|
*/ |
|
BUG(); |
|
/* Unsupported |
|
* return(ftest(0L,extru(ir,fptpos,5), |
|
* &fpregs[0],subop)); |
|
*/ |
|
case 1: |
|
case 2: |
|
case 3: |
|
return(MAJOR_0C_EXCP); |
|
} |
|
} else { /* FCMP */ |
|
switch (fmt) { |
|
case 0: |
|
retval = sgl_fcmp(&fpregs[r1], |
|
&fpregs[r2],extru(ir,fptpos,5), |
|
&local_status); |
|
update_status_cbit(status,local_status, |
|
fpu_type_flags, subop); |
|
return(retval); |
|
case 1: |
|
retval = dbl_fcmp(&fpregs[r1], |
|
&fpregs[r2],extru(ir,fptpos,5), |
|
&local_status); |
|
update_status_cbit(status,local_status, |
|
fpu_type_flags, subop); |
|
return(retval); |
|
case 2: /* illegal */ |
|
case 3: /* quad not implemented */ |
|
return(MAJOR_0C_EXCP); |
|
} |
|
} |
|
} /* end of if for PA2.0 */ |
|
else { /* PA1.0 & PA1.1 */ |
|
switch (subop) { |
|
case 2: |
|
case 3: |
|
case 4: |
|
case 5: |
|
case 6: |
|
case 7: |
|
return(MAJOR_0C_EXCP); |
|
case 0: /* FCMP */ |
|
switch (fmt) { |
|
case 0: |
|
retval = sgl_fcmp(&fpregs[r1], |
|
&fpregs[r2],extru(ir,fptpos,5), |
|
&local_status); |
|
update_status_cbit(status,local_status, |
|
fpu_type_flags, subop); |
|
return(retval); |
|
case 1: |
|
retval = dbl_fcmp(&fpregs[r1], |
|
&fpregs[r2],extru(ir,fptpos,5), |
|
&local_status); |
|
update_status_cbit(status,local_status, |
|
fpu_type_flags, subop); |
|
return(retval); |
|
case 2: /* illegal */ |
|
case 3: /* quad not implemented */ |
|
return(MAJOR_0C_EXCP); |
|
} |
|
case 1: /* FTEST */ |
|
switch (fmt) { |
|
case 0: |
|
/* |
|
* arg0 is not used |
|
* second param is the t field used for |
|
* ftest,acc and ftest,rej |
|
* third param is the subop (y-field) |
|
*/ |
|
BUG(); |
|
/* unsupported |
|
* return(ftest(0L,extru(ir,fptpos,5), |
|
* &fpregs[0],subop)); |
|
*/ |
|
case 1: |
|
case 2: |
|
case 3: |
|
return(MAJOR_0C_EXCP); |
|
} |
|
} /* end of switch subop */ |
|
} /* end of else for PA1.0 & PA1.1 */ |
|
case 3: /* class 3 */ |
|
r2 = extru(ir,fpr2pos,5) * sizeof(double)/sizeof(u_int); |
|
if (r2 == 0) |
|
r2 = fpzeroreg; |
|
switch (subop) { |
|
case 5: |
|
case 6: |
|
case 7: |
|
return(MAJOR_0C_EXCP); |
|
|
|
case 0: /* FADD */ |
|
switch (fmt) { |
|
case 0: |
|
return(sgl_fadd(&fpregs[r1],&fpregs[r2], |
|
&fpregs[t],status)); |
|
case 1: |
|
return(dbl_fadd(&fpregs[r1],&fpregs[r2], |
|
&fpregs[t],status)); |
|
case 2: /* illegal */ |
|
case 3: /* quad not implemented */ |
|
return(MAJOR_0C_EXCP); |
|
} |
|
case 1: /* FSUB */ |
|
switch (fmt) { |
|
case 0: |
|
return(sgl_fsub(&fpregs[r1],&fpregs[r2], |
|
&fpregs[t],status)); |
|
case 1: |
|
return(dbl_fsub(&fpregs[r1],&fpregs[r2], |
|
&fpregs[t],status)); |
|
case 2: /* illegal */ |
|
case 3: /* quad not implemented */ |
|
return(MAJOR_0C_EXCP); |
|
} |
|
case 2: /* FMPY */ |
|
switch (fmt) { |
|
case 0: |
|
return(sgl_fmpy(&fpregs[r1],&fpregs[r2], |
|
&fpregs[t],status)); |
|
case 1: |
|
return(dbl_fmpy(&fpregs[r1],&fpregs[r2], |
|
&fpregs[t],status)); |
|
case 2: /* illegal */ |
|
case 3: /* quad not implemented */ |
|
return(MAJOR_0C_EXCP); |
|
} |
|
case 3: /* FDIV */ |
|
switch (fmt) { |
|
case 0: |
|
return(sgl_fdiv(&fpregs[r1],&fpregs[r2], |
|
&fpregs[t],status)); |
|
case 1: |
|
return(dbl_fdiv(&fpregs[r1],&fpregs[r2], |
|
&fpregs[t],status)); |
|
case 2: /* illegal */ |
|
case 3: /* quad not implemented */ |
|
return(MAJOR_0C_EXCP); |
|
} |
|
case 4: /* FREM */ |
|
switch (fmt) { |
|
case 0: |
|
return(sgl_frem(&fpregs[r1],&fpregs[r2], |
|
&fpregs[t],status)); |
|
case 1: |
|
return(dbl_frem(&fpregs[r1],&fpregs[r2], |
|
&fpregs[t],status)); |
|
case 2: /* illegal */ |
|
case 3: /* quad not implemented */ |
|
return(MAJOR_0C_EXCP); |
|
} |
|
} /* end of class 3 switch */ |
|
} /* end of switch(class) */ |
|
|
|
/* If we get here, something is really wrong! */ |
|
return(MAJOR_0C_EXCP); |
|
} |
|
|
|
static u_int |
|
decode_0e(ir,class,subop,fpregs) |
|
u_int ir,class,subop; |
|
u_int fpregs[]; |
|
{ |
|
u_int r1,r2,t; /* operand register offsets */ |
|
u_int fmt; /* also sf for class 1 conversions */ |
|
u_int df; /* dest format for class 1 conversions */ |
|
u_int *status; |
|
u_int retval, local_status; |
|
u_int fpu_type_flags; |
|
|
|
status = &fpregs[0]; |
|
local_status = fpregs[0]; |
|
r1 = ((extru(ir,fpr1pos,5)<<1)|(extru(ir,fpxr1pos,1))); |
|
if (r1 == 0) |
|
r1 = fpzeroreg; |
|
t = ((extru(ir,fptpos,5)<<1)|(extru(ir,fpxtpos,1))); |
|
if (t == 0 && class != 2) |
|
return(MAJOR_0E_EXCP); |
|
if (class < 2) /* class 0 or 1 has 2 bit fmt */ |
|
fmt = extru(ir,fpfmtpos,2); |
|
else /* class 2 and 3 have 1 bit fmt */ |
|
fmt = extru(ir,fp0efmtpos,1); |
|
/* |
|
* An undefined combination, double precision accessing the |
|
* right half of a FPR, can get us into trouble. |
|
* Let's just force proper alignment on it. |
|
*/ |
|
if (fmt == DBL) { |
|
r1 &= ~1; |
|
if (class != 1) |
|
t &= ~1; |
|
} |
|
|
|
switch (class) { |
|
case 0: |
|
switch (subop) { |
|
case 0: /* unimplemented */ |
|
case 1: |
|
return(MAJOR_0E_EXCP); |
|
case 2: /* FCPY */ |
|
switch (fmt) { |
|
case 2: |
|
case 3: |
|
return(MAJOR_0E_EXCP); |
|
case 1: /* double */ |
|
fpregs[t+1] = fpregs[r1+1]; |
|
case 0: /* single */ |
|
fpregs[t] = fpregs[r1]; |
|
return(NOEXCEPTION); |
|
} |
|
case 3: /* FABS */ |
|
switch (fmt) { |
|
case 2: |
|
case 3: |
|
return(MAJOR_0E_EXCP); |
|
case 1: /* double */ |
|
fpregs[t+1] = fpregs[r1+1]; |
|
case 0: /* single */ |
|
fpregs[t] = fpregs[r1] & 0x7fffffff; |
|
return(NOEXCEPTION); |
|
} |
|
case 6: /* FNEG */ |
|
switch (fmt) { |
|
case 2: |
|
case 3: |
|
return(MAJOR_0E_EXCP); |
|
case 1: /* double */ |
|
fpregs[t+1] = fpregs[r1+1]; |
|
case 0: /* single */ |
|
fpregs[t] = fpregs[r1] ^ 0x80000000; |
|
return(NOEXCEPTION); |
|
} |
|
case 7: /* FNEGABS */ |
|
switch (fmt) { |
|
case 2: |
|
case 3: |
|
return(MAJOR_0E_EXCP); |
|
case 1: /* double */ |
|
fpregs[t+1] = fpregs[r1+1]; |
|
case 0: /* single */ |
|
fpregs[t] = fpregs[r1] | 0x80000000; |
|
return(NOEXCEPTION); |
|
} |
|
case 4: /* FSQRT */ |
|
switch (fmt) { |
|
case 0: |
|
return(sgl_fsqrt(&fpregs[r1],0, |
|
&fpregs[t], status)); |
|
case 1: |
|
return(dbl_fsqrt(&fpregs[r1],0, |
|
&fpregs[t], status)); |
|
case 2: |
|
case 3: |
|
return(MAJOR_0E_EXCP); |
|
} |
|
case 5: /* FRMD */ |
|
switch (fmt) { |
|
case 0: |
|
return(sgl_frnd(&fpregs[r1],0, |
|
&fpregs[t], status)); |
|
case 1: |
|
return(dbl_frnd(&fpregs[r1],0, |
|
&fpregs[t], status)); |
|
case 2: |
|
case 3: |
|
return(MAJOR_0E_EXCP); |
|
} |
|
} /* end of switch (subop */ |
|
|
|
case 1: /* class 1 */ |
|
df = extru(ir,fpdfpos,2); /* get dest format */ |
|
/* |
|
* Fix Crashme problem (writing to 31R in double precision) |
|
* here too. |
|
*/ |
|
if (df == DBL) { |
|
t &= ~1; |
|
} |
|
if ((df & 2) || (fmt & 2)) |
|
return(MAJOR_0E_EXCP); |
|
|
|
fmt = (fmt << 1) | df; |
|
switch (subop) { |
|
case 0: /* FCNVFF */ |
|
switch(fmt) { |
|
case 0: /* sgl/sgl */ |
|
return(MAJOR_0E_EXCP); |
|
case 1: /* sgl/dbl */ |
|
return(sgl_to_dbl_fcnvff(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
case 2: /* dbl/sgl */ |
|
return(dbl_to_sgl_fcnvff(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
case 3: /* dbl/dbl */ |
|
return(MAJOR_0E_EXCP); |
|
} |
|
case 1: /* FCNVXF */ |
|
switch(fmt) { |
|
case 0: /* sgl/sgl */ |
|
return(sgl_to_sgl_fcnvxf(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
case 1: /* sgl/dbl */ |
|
return(sgl_to_dbl_fcnvxf(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
case 2: /* dbl/sgl */ |
|
return(dbl_to_sgl_fcnvxf(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
case 3: /* dbl/dbl */ |
|
return(dbl_to_dbl_fcnvxf(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
} |
|
case 2: /* FCNVFX */ |
|
switch(fmt) { |
|
case 0: /* sgl/sgl */ |
|
return(sgl_to_sgl_fcnvfx(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
case 1: /* sgl/dbl */ |
|
return(sgl_to_dbl_fcnvfx(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
case 2: /* dbl/sgl */ |
|
return(dbl_to_sgl_fcnvfx(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
case 3: /* dbl/dbl */ |
|
return(dbl_to_dbl_fcnvfx(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
} |
|
case 3: /* FCNVFXT */ |
|
switch(fmt) { |
|
case 0: /* sgl/sgl */ |
|
return(sgl_to_sgl_fcnvfxt(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
case 1: /* sgl/dbl */ |
|
return(sgl_to_dbl_fcnvfxt(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
case 2: /* dbl/sgl */ |
|
return(dbl_to_sgl_fcnvfxt(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
case 3: /* dbl/dbl */ |
|
return(dbl_to_dbl_fcnvfxt(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
} |
|
case 5: /* FCNVUF (PA2.0 only) */ |
|
switch(fmt) { |
|
case 0: /* sgl/sgl */ |
|
return(sgl_to_sgl_fcnvuf(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
case 1: /* sgl/dbl */ |
|
return(sgl_to_dbl_fcnvuf(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
case 2: /* dbl/sgl */ |
|
return(dbl_to_sgl_fcnvuf(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
case 3: /* dbl/dbl */ |
|
return(dbl_to_dbl_fcnvuf(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
} |
|
case 6: /* FCNVFU (PA2.0 only) */ |
|
switch(fmt) { |
|
case 0: /* sgl/sgl */ |
|
return(sgl_to_sgl_fcnvfu(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
case 1: /* sgl/dbl */ |
|
return(sgl_to_dbl_fcnvfu(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
case 2: /* dbl/sgl */ |
|
return(dbl_to_sgl_fcnvfu(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
case 3: /* dbl/dbl */ |
|
return(dbl_to_dbl_fcnvfu(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
} |
|
case 7: /* FCNVFUT (PA2.0 only) */ |
|
switch(fmt) { |
|
case 0: /* sgl/sgl */ |
|
return(sgl_to_sgl_fcnvfut(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
case 1: /* sgl/dbl */ |
|
return(sgl_to_dbl_fcnvfut(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
case 2: /* dbl/sgl */ |
|
return(dbl_to_sgl_fcnvfut(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
case 3: /* dbl/dbl */ |
|
return(dbl_to_dbl_fcnvfut(&fpregs[r1],0, |
|
&fpregs[t],status)); |
|
} |
|
case 4: /* undefined */ |
|
return(MAJOR_0C_EXCP); |
|
} /* end of switch subop */ |
|
case 2: /* class 2 */ |
|
/* |
|
* Be careful out there. |
|
* Crashme can generate cases where FR31R is specified |
|
* as the source or target of a double precision operation. |
|
* Since we just pass the address of the floating-point |
|
* register to the emulation routines, this can cause |
|
* corruption of fpzeroreg. |
|
*/ |
|
if (fmt == DBL) |
|
r2 = (extru(ir,fpr2pos,5)<<1); |
|
else |
|
r2 = ((extru(ir,fpr2pos,5)<<1)|(extru(ir,fpxr2pos,1))); |
|
fpu_type_flags=fpregs[FPU_TYPE_FLAG_POS]; |
|
if (r2 == 0) |
|
r2 = fpzeroreg; |
|
if (fpu_type_flags & PA2_0_FPU_FLAG) { |
|
/* FTEST if nullify bit set, otherwise FCMP */ |
|
if (extru(ir, fpnulpos, 1)) { /* FTEST */ |
|
/* not legal */ |
|
return(MAJOR_0E_EXCP); |
|
} else { /* FCMP */ |
|
switch (fmt) { |
|
/* |
|
* fmt is only 1 bit long |
|
*/ |
|
case 0: |
|
retval = sgl_fcmp(&fpregs[r1], |
|
&fpregs[r2],extru(ir,fptpos,5), |
|
&local_status); |
|
update_status_cbit(status,local_status, |
|
fpu_type_flags, subop); |
|
return(retval); |
|
case 1: |
|
retval = dbl_fcmp(&fpregs[r1], |
|
&fpregs[r2],extru(ir,fptpos,5), |
|
&local_status); |
|
update_status_cbit(status,local_status, |
|
fpu_type_flags, subop); |
|
return(retval); |
|
} |
|
} |
|
} /* end of if for PA2.0 */ |
|
else { /* PA1.0 & PA1.1 */ |
|
switch (subop) { |
|
case 1: |
|
case 2: |
|
case 3: |
|
case 4: |
|
case 5: |
|
case 6: |
|
case 7: |
|
return(MAJOR_0E_EXCP); |
|
case 0: /* FCMP */ |
|
switch (fmt) { |
|
/* |
|
* fmt is only 1 bit long |
|
*/ |
|
case 0: |
|
retval = sgl_fcmp(&fpregs[r1], |
|
&fpregs[r2],extru(ir,fptpos,5), |
|
&local_status); |
|
update_status_cbit(status,local_status, |
|
fpu_type_flags, subop); |
|
return(retval); |
|
case 1: |
|
retval = dbl_fcmp(&fpregs[r1], |
|
&fpregs[r2],extru(ir,fptpos,5), |
|
&local_status); |
|
update_status_cbit(status,local_status, |
|
fpu_type_flags, subop); |
|
return(retval); |
|
} |
|
} /* end of switch subop */ |
|
} /* end of else for PA1.0 & PA1.1 */ |
|
case 3: /* class 3 */ |
|
/* |
|
* Be careful out there. |
|
* Crashme can generate cases where FR31R is specified |
|
* as the source or target of a double precision operation. |
|
* Since we just pass the address of the floating-point |
|
* register to the emulation routines, this can cause |
|
* corruption of fpzeroreg. |
|
*/ |
|
if (fmt == DBL) |
|
r2 = (extru(ir,fpr2pos,5)<<1); |
|
else |
|
r2 = ((extru(ir,fpr2pos,5)<<1)|(extru(ir,fpxr2pos,1))); |
|
if (r2 == 0) |
|
r2 = fpzeroreg; |
|
switch (subop) { |
|
case 5: |
|
case 6: |
|
case 7: |
|
return(MAJOR_0E_EXCP); |
|
|
|
/* |
|
* Note that fmt is only 1 bit for class 3 */ |
|
case 0: /* FADD */ |
|
switch (fmt) { |
|
case 0: |
|
return(sgl_fadd(&fpregs[r1],&fpregs[r2], |
|
&fpregs[t],status)); |
|
case 1: |
|
return(dbl_fadd(&fpregs[r1],&fpregs[r2], |
|
&fpregs[t],status)); |
|
} |
|
case 1: /* FSUB */ |
|
switch (fmt) { |
|
case 0: |
|
return(sgl_fsub(&fpregs[r1],&fpregs[r2], |
|
&fpregs[t],status)); |
|
case 1: |
|
return(dbl_fsub(&fpregs[r1],&fpregs[r2], |
|
&fpregs[t],status)); |
|
} |
|
case 2: /* FMPY or XMPYU */ |
|
/* |
|
* check for integer multiply (x bit set) |
|
*/ |
|
if (extru(ir,fpxpos,1)) { |
|
/* |
|
* emulate XMPYU |
|
*/ |
|
switch (fmt) { |
|
case 0: |
|
/* |
|
* bad instruction if t specifies |
|
* the right half of a register |
|
*/ |
|
if (t & 1) |
|
return(MAJOR_0E_EXCP); |
|
BUG(); |
|
/* unsupported |
|
* impyu(&fpregs[r1],&fpregs[r2], |
|
* &fpregs[t]); |
|
*/ |
|
return(NOEXCEPTION); |
|
case 1: |
|
return(MAJOR_0E_EXCP); |
|
} |
|
} |
|
else { /* FMPY */ |
|
switch (fmt) { |
|
case 0: |
|
return(sgl_fmpy(&fpregs[r1], |
|
&fpregs[r2],&fpregs[t],status)); |
|
case 1: |
|
return(dbl_fmpy(&fpregs[r1], |
|
&fpregs[r2],&fpregs[t],status)); |
|
} |
|
} |
|
case 3: /* FDIV */ |
|
switch (fmt) { |
|
case 0: |
|
return(sgl_fdiv(&fpregs[r1],&fpregs[r2], |
|
&fpregs[t],status)); |
|
case 1: |
|
return(dbl_fdiv(&fpregs[r1],&fpregs[r2], |
|
&fpregs[t],status)); |
|
} |
|
case 4: /* FREM */ |
|
switch (fmt) { |
|
case 0: |
|
return(sgl_frem(&fpregs[r1],&fpregs[r2], |
|
&fpregs[t],status)); |
|
case 1: |
|
return(dbl_frem(&fpregs[r1],&fpregs[r2], |
|
&fpregs[t],status)); |
|
} |
|
} /* end of class 3 switch */ |
|
} /* end of switch(class) */ |
|
|
|
/* If we get here, something is really wrong! */ |
|
return(MAJOR_0E_EXCP); |
|
} |
|
|
|
|
|
/* |
|
* routine to decode the 06 (FMPYADD and FMPYCFXT) instruction |
|
*/ |
|
static u_int |
|
decode_06(ir,fpregs) |
|
u_int ir; |
|
u_int fpregs[]; |
|
{ |
|
u_int rm1, rm2, tm, ra, ta; /* operands */ |
|
u_int fmt; |
|
u_int error = 0; |
|
u_int status; |
|
u_int fpu_type_flags; |
|
union { |
|
double dbl; |
|
float flt; |
|
struct { u_int i1; u_int i2; } ints; |
|
} mtmp, atmp; |
|
|
|
|
|
status = fpregs[0]; /* use a local copy of status reg */ |
|
fpu_type_flags=fpregs[FPU_TYPE_FLAG_POS]; /* get fpu type flags */ |
|
fmt = extru(ir, fpmultifmt, 1); /* get sgl/dbl flag */ |
|
if (fmt == 0) { /* DBL */ |
|
rm1 = extru(ir, fprm1pos, 5) * sizeof(double)/sizeof(u_int); |
|
if (rm1 == 0) |
|
rm1 = fpzeroreg; |
|
rm2 = extru(ir, fprm2pos, 5) * sizeof(double)/sizeof(u_int); |
|
if (rm2 == 0) |
|
rm2 = fpzeroreg; |
|
tm = extru(ir, fptmpos, 5) * sizeof(double)/sizeof(u_int); |
|
if (tm == 0) |
|
return(MAJOR_06_EXCP); |
|
ra = extru(ir, fprapos, 5) * sizeof(double)/sizeof(u_int); |
|
ta = extru(ir, fptapos, 5) * sizeof(double)/sizeof(u_int); |
|
if (ta == 0) |
|
return(MAJOR_06_EXCP); |
|
|
|
if (fpu_type_flags & TIMEX_ROLEX_FPU_MASK) { |
|
|
|
if (ra == 0) { |
|
/* special case FMPYCFXT, see sgl case below */ |
|
if (dbl_fmpy(&fpregs[rm1],&fpregs[rm2], |
|
&mtmp.ints.i1,&status)) |
|
error = 1; |
|
if (dbl_to_sgl_fcnvfxt(&fpregs[ta], |
|
&atmp.ints.i1,&atmp.ints.i1,&status)) |
|
error = 1; |
|
} |
|
else { |
|
|
|
if (dbl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1, |
|
&status)) |
|
error = 1; |
|
if (dbl_fadd(&fpregs[ta], &fpregs[ra], &atmp.ints.i1, |
|
&status)) |
|
error = 1; |
|
} |
|
} |
|
|
|
else |
|
|
|
{ |
|
if (ra == 0) |
|
ra = fpzeroreg; |
|
|
|
if (dbl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1, |
|
&status)) |
|
error = 1; |
|
if (dbl_fadd(&fpregs[ta], &fpregs[ra], &atmp.ints.i1, |
|
&status)) |
|
error = 1; |
|
|
|
} |
|
|
|
if (error) |
|
return(MAJOR_06_EXCP); |
|
else { |
|
/* copy results */ |
|
fpregs[tm] = mtmp.ints.i1; |
|
fpregs[tm+1] = mtmp.ints.i2; |
|
fpregs[ta] = atmp.ints.i1; |
|
fpregs[ta+1] = atmp.ints.i2; |
|
fpregs[0] = status; |
|
return(NOEXCEPTION); |
|
} |
|
} |
|
else { /* SGL */ |
|
/* |
|
* calculate offsets for single precision numbers |
|
* See table 6-14 in PA-89 architecture for mapping |
|
*/ |
|
rm1 = (extru(ir,fprm1pos,4) | 0x10 ) << 1; /* get offset */ |
|
rm1 |= extru(ir,fprm1pos-4,1); /* add right word offset */ |
|
|
|
rm2 = (extru(ir,fprm2pos,4) | 0x10 ) << 1; /* get offset */ |
|
rm2 |= extru(ir,fprm2pos-4,1); /* add right word offset */ |
|
|
|
tm = (extru(ir,fptmpos,4) | 0x10 ) << 1; /* get offset */ |
|
tm |= extru(ir,fptmpos-4,1); /* add right word offset */ |
|
|
|
ra = (extru(ir,fprapos,4) | 0x10 ) << 1; /* get offset */ |
|
ra |= extru(ir,fprapos-4,1); /* add right word offset */ |
|
|
|
ta = (extru(ir,fptapos,4) | 0x10 ) << 1; /* get offset */ |
|
ta |= extru(ir,fptapos-4,1); /* add right word offset */ |
|
|
|
if (ra == 0x20 &&(fpu_type_flags & TIMEX_ROLEX_FPU_MASK)) { |
|
/* special case FMPYCFXT (really 0) |
|
* This instruction is only present on the Timex and |
|
* Rolex fpu's in so if it is the special case and |
|
* one of these fpu's we run the FMPYCFXT instruction |
|
*/ |
|
if (sgl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1, |
|
&status)) |
|
error = 1; |
|
if (sgl_to_sgl_fcnvfxt(&fpregs[ta],&atmp.ints.i1, |
|
&atmp.ints.i1,&status)) |
|
error = 1; |
|
} |
|
else { |
|
if (sgl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1, |
|
&status)) |
|
error = 1; |
|
if (sgl_fadd(&fpregs[ta], &fpregs[ra], &atmp.ints.i1, |
|
&status)) |
|
error = 1; |
|
} |
|
if (error) |
|
return(MAJOR_06_EXCP); |
|
else { |
|
/* copy results */ |
|
fpregs[tm] = mtmp.ints.i1; |
|
fpregs[ta] = atmp.ints.i1; |
|
fpregs[0] = status; |
|
return(NOEXCEPTION); |
|
} |
|
} |
|
} |
|
|
|
/* |
|
* routine to decode the 26 (FMPYSUB) instruction |
|
*/ |
|
static u_int |
|
decode_26(ir,fpregs) |
|
u_int ir; |
|
u_int fpregs[]; |
|
{ |
|
u_int rm1, rm2, tm, ra, ta; /* operands */ |
|
u_int fmt; |
|
u_int error = 0; |
|
u_int status; |
|
union { |
|
double dbl; |
|
float flt; |
|
struct { u_int i1; u_int i2; } ints; |
|
} mtmp, atmp; |
|
|
|
|
|
status = fpregs[0]; |
|
fmt = extru(ir, fpmultifmt, 1); /* get sgl/dbl flag */ |
|
if (fmt == 0) { /* DBL */ |
|
rm1 = extru(ir, fprm1pos, 5) * sizeof(double)/sizeof(u_int); |
|
if (rm1 == 0) |
|
rm1 = fpzeroreg; |
|
rm2 = extru(ir, fprm2pos, 5) * sizeof(double)/sizeof(u_int); |
|
if (rm2 == 0) |
|
rm2 = fpzeroreg; |
|
tm = extru(ir, fptmpos, 5) * sizeof(double)/sizeof(u_int); |
|
if (tm == 0) |
|
return(MAJOR_26_EXCP); |
|
ra = extru(ir, fprapos, 5) * sizeof(double)/sizeof(u_int); |
|
if (ra == 0) |
|
return(MAJOR_26_EXCP); |
|
ta = extru(ir, fptapos, 5) * sizeof(double)/sizeof(u_int); |
|
if (ta == 0) |
|
return(MAJOR_26_EXCP); |
|
|
|
if (dbl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1,&status)) |
|
error = 1; |
|
if (dbl_fsub(&fpregs[ta], &fpregs[ra], &atmp.ints.i1,&status)) |
|
error = 1; |
|
if (error) |
|
return(MAJOR_26_EXCP); |
|
else { |
|
/* copy results */ |
|
fpregs[tm] = mtmp.ints.i1; |
|
fpregs[tm+1] = mtmp.ints.i2; |
|
fpregs[ta] = atmp.ints.i1; |
|
fpregs[ta+1] = atmp.ints.i2; |
|
fpregs[0] = status; |
|
return(NOEXCEPTION); |
|
} |
|
} |
|
else { /* SGL */ |
|
/* |
|
* calculate offsets for single precision numbers |
|
* See table 6-14 in PA-89 architecture for mapping |
|
*/ |
|
rm1 = (extru(ir,fprm1pos,4) | 0x10 ) << 1; /* get offset */ |
|
rm1 |= extru(ir,fprm1pos-4,1); /* add right word offset */ |
|
|
|
rm2 = (extru(ir,fprm2pos,4) | 0x10 ) << 1; /* get offset */ |
|
rm2 |= extru(ir,fprm2pos-4,1); /* add right word offset */ |
|
|
|
tm = (extru(ir,fptmpos,4) | 0x10 ) << 1; /* get offset */ |
|
tm |= extru(ir,fptmpos-4,1); /* add right word offset */ |
|
|
|
ra = (extru(ir,fprapos,4) | 0x10 ) << 1; /* get offset */ |
|
ra |= extru(ir,fprapos-4,1); /* add right word offset */ |
|
|
|
ta = (extru(ir,fptapos,4) | 0x10 ) << 1; /* get offset */ |
|
ta |= extru(ir,fptapos-4,1); /* add right word offset */ |
|
|
|
if (sgl_fmpy(&fpregs[rm1],&fpregs[rm2],&mtmp.ints.i1,&status)) |
|
error = 1; |
|
if (sgl_fsub(&fpregs[ta], &fpregs[ra], &atmp.ints.i1,&status)) |
|
error = 1; |
|
if (error) |
|
return(MAJOR_26_EXCP); |
|
else { |
|
/* copy results */ |
|
fpregs[tm] = mtmp.ints.i1; |
|
fpregs[ta] = atmp.ints.i1; |
|
fpregs[0] = status; |
|
return(NOEXCEPTION); |
|
} |
|
} |
|
|
|
} |
|
|
|
/* |
|
* routine to decode the 2E (FMPYFADD,FMPYNFADD) instructions |
|
*/ |
|
static u_int |
|
decode_2e(ir,fpregs) |
|
u_int ir; |
|
u_int fpregs[]; |
|
{ |
|
u_int rm1, rm2, ra, t; /* operands */ |
|
u_int fmt; |
|
|
|
fmt = extru(ir,fpfmtpos,1); /* get fmt completer */ |
|
if (fmt == DBL) { /* DBL */ |
|
rm1 = extru(ir,fprm1pos,5) * sizeof(double)/sizeof(u_int); |
|
if (rm1 == 0) |
|
rm1 = fpzeroreg; |
|
rm2 = extru(ir,fprm2pos,5) * sizeof(double)/sizeof(u_int); |
|
if (rm2 == 0) |
|
rm2 = fpzeroreg; |
|
ra = ((extru(ir,fpraupos,3)<<2)|(extru(ir,fpralpos,3)>>1)) * |
|
sizeof(double)/sizeof(u_int); |
|
if (ra == 0) |
|
ra = fpzeroreg; |
|
t = extru(ir,fptpos,5) * sizeof(double)/sizeof(u_int); |
|
if (t == 0) |
|
return(MAJOR_2E_EXCP); |
|
|
|
if (extru(ir,fpfusedsubop,1)) { /* fmpyfadd or fmpynfadd? */ |
|
return(dbl_fmpynfadd(&fpregs[rm1], &fpregs[rm2], |
|
&fpregs[ra], &fpregs[0], &fpregs[t])); |
|
} else { |
|
return(dbl_fmpyfadd(&fpregs[rm1], &fpregs[rm2], |
|
&fpregs[ra], &fpregs[0], &fpregs[t])); |
|
} |
|
} /* end DBL */ |
|
else { /* SGL */ |
|
rm1 = (extru(ir,fprm1pos,5)<<1)|(extru(ir,fpxrm1pos,1)); |
|
if (rm1 == 0) |
|
rm1 = fpzeroreg; |
|
rm2 = (extru(ir,fprm2pos,5)<<1)|(extru(ir,fpxrm2pos,1)); |
|
if (rm2 == 0) |
|
rm2 = fpzeroreg; |
|
ra = (extru(ir,fpraupos,3)<<3)|extru(ir,fpralpos,3); |
|
if (ra == 0) |
|
ra = fpzeroreg; |
|
t = ((extru(ir,fptpos,5)<<1)|(extru(ir,fpxtpos,1))); |
|
if (t == 0) |
|
return(MAJOR_2E_EXCP); |
|
|
|
if (extru(ir,fpfusedsubop,1)) { /* fmpyfadd or fmpynfadd? */ |
|
return(sgl_fmpynfadd(&fpregs[rm1], &fpregs[rm2], |
|
&fpregs[ra], &fpregs[0], &fpregs[t])); |
|
} else { |
|
return(sgl_fmpyfadd(&fpregs[rm1], &fpregs[rm2], |
|
&fpregs[ra], &fpregs[0], &fpregs[t])); |
|
} |
|
} /* end SGL */ |
|
} |
|
|
|
/* |
|
* update_status_cbit |
|
* |
|
* This routine returns the correct FP status register value in |
|
* *status, based on the C-bit & V-bit returned by the FCMP |
|
* emulation routine in new_status. The architecture type |
|
* (PA83, PA89 or PA2.0) is available in fpu_type. The y_field |
|
* and the architecture type are used to determine what flavor |
|
* of FCMP is being emulated. |
|
*/ |
|
static void |
|
update_status_cbit(status, new_status, fpu_type, y_field) |
|
u_int *status, new_status; |
|
u_int fpu_type; |
|
u_int y_field; |
|
{ |
|
/* |
|
* For PA89 FPU's which implement the Compare Queue and |
|
* for PA2.0 FPU's, update the Compare Queue if the y-field = 0, |
|
* otherwise update the specified bit in the Compare Array. |
|
* Note that the y-field will always be 0 for non-PA2.0 FPU's. |
|
*/ |
|
if ((fpu_type & TIMEX_EXTEN_FLAG) || |
|
(fpu_type & ROLEX_EXTEN_FLAG) || |
|
(fpu_type & PA2_0_FPU_FLAG)) { |
|
if (y_field == 0) { |
|
*status = ((*status & 0x04000000) >> 5) | /* old Cbit */ |
|
((*status & 0x003ff000) >> 1) | /* old CQ */ |
|
(new_status & 0xffc007ff); /* all other bits*/ |
|
} else { |
|
*status = (*status & 0x04000000) | /* old Cbit */ |
|
((new_status & 0x04000000) >> (y_field+4)) | |
|
(new_status & ~0x04000000 & /* other bits */ |
|
~(0x04000000 >> (y_field+4))); |
|
} |
|
} |
|
/* if PA83, just update the C-bit */ |
|
else { |
|
*status = new_status; |
|
} |
|
}
|
|
|