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286 lines
7.5 KiB
286 lines
7.5 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* linux/arch/parisc/kernel/time.c |
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* |
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* Copyright (C) 1991, 1992, 1995 Linus Torvalds |
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* Modifications for ARM (C) 1994, 1995, 1996,1997 Russell King |
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* Copyright (C) 1999 SuSE GmbH, (Philipp Rumpf, [email protected]) |
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* |
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* 1994-07-02 Alan Modra |
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* fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime |
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* 1998-12-20 Updated NTP code according to technical memorandum Jan '96 |
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* "A Kernel Model for Precision Timekeeping" by Dave Mills |
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*/ |
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#include <linux/errno.h> |
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#include <linux/module.h> |
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#include <linux/rtc.h> |
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#include <linux/sched.h> |
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#include <linux/sched/clock.h> |
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#include <linux/sched_clock.h> |
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#include <linux/kernel.h> |
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#include <linux/param.h> |
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#include <linux/string.h> |
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#include <linux/mm.h> |
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#include <linux/interrupt.h> |
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#include <linux/time.h> |
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#include <linux/init.h> |
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#include <linux/smp.h> |
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#include <linux/profile.h> |
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#include <linux/clocksource.h> |
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#include <linux/platform_device.h> |
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#include <linux/ftrace.h> |
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#include <linux/uaccess.h> |
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#include <asm/io.h> |
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#include <asm/irq.h> |
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#include <asm/page.h> |
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#include <asm/param.h> |
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#include <asm/pdc.h> |
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#include <asm/led.h> |
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#include <linux/timex.h> |
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static unsigned long clocktick __ro_after_init; /* timer cycles per tick */ |
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/* |
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* We keep time on PA-RISC Linux by using the Interval Timer which is |
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* a pair of registers; one is read-only and one is write-only; both |
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* accessed through CR16. The read-only register is 32 or 64 bits wide, |
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* and increments by 1 every CPU clock tick. The architecture only |
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* guarantees us a rate between 0.5 and 2, but all implementations use a |
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* rate of 1. The write-only register is 32-bits wide. When the lowest |
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* 32 bits of the read-only register compare equal to the write-only |
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* register, it raises a maskable external interrupt. Each processor has |
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* an Interval Timer of its own and they are not synchronised. |
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* |
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* We want to generate an interrupt every 1/HZ seconds. So we program |
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* CR16 to interrupt every @clocktick cycles. The it_value in cpu_data |
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* is programmed with the intended time of the next tick. We can be |
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* held off for an arbitrarily long period of time by interrupts being |
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* disabled, so we may miss one or more ticks. |
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*/ |
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irqreturn_t __irq_entry timer_interrupt(int irq, void *dev_id) |
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{ |
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unsigned long now; |
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unsigned long next_tick; |
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unsigned long ticks_elapsed = 0; |
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unsigned int cpu = smp_processor_id(); |
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struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu); |
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/* gcc can optimize for "read-only" case with a local clocktick */ |
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unsigned long cpt = clocktick; |
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/* Initialize next_tick to the old expected tick time. */ |
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next_tick = cpuinfo->it_value; |
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/* Calculate how many ticks have elapsed. */ |
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now = mfctl(16); |
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do { |
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++ticks_elapsed; |
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next_tick += cpt; |
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} while (next_tick - now > cpt); |
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/* Store (in CR16 cycles) up to when we are accounting right now. */ |
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cpuinfo->it_value = next_tick; |
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/* Go do system house keeping. */ |
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if (cpu != 0) |
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ticks_elapsed = 0; |
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legacy_timer_tick(ticks_elapsed); |
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/* Skip clockticks on purpose if we know we would miss those. |
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* The new CR16 must be "later" than current CR16 otherwise |
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* itimer would not fire until CR16 wrapped - e.g 4 seconds |
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* later on a 1Ghz processor. We'll account for the missed |
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* ticks on the next timer interrupt. |
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* We want IT to fire modulo clocktick even if we miss/skip some. |
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* But those interrupts don't in fact get delivered that regularly. |
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* |
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* "next_tick - now" will always give the difference regardless |
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* if one or the other wrapped. If "now" is "bigger" we'll end up |
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* with a very large unsigned number. |
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*/ |
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now = mfctl(16); |
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while (next_tick - now > cpt) |
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next_tick += cpt; |
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/* Program the IT when to deliver the next interrupt. |
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* Only bottom 32-bits of next_tick are writable in CR16! |
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* Timer interrupt will be delivered at least a few hundred cycles |
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* after the IT fires, so if we are too close (<= 8000 cycles) to the |
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* next cycle, simply skip it. |
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*/ |
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if (next_tick - now <= 8000) |
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next_tick += cpt; |
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mtctl(next_tick, 16); |
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return IRQ_HANDLED; |
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} |
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unsigned long profile_pc(struct pt_regs *regs) |
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{ |
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unsigned long pc = instruction_pointer(regs); |
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if (regs->gr[0] & PSW_N) |
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pc -= 4; |
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#ifdef CONFIG_SMP |
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if (in_lock_functions(pc)) |
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pc = regs->gr[2]; |
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#endif |
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return pc; |
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} |
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EXPORT_SYMBOL(profile_pc); |
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/* clock source code */ |
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static u64 notrace read_cr16(struct clocksource *cs) |
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{ |
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return get_cycles(); |
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} |
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static struct clocksource clocksource_cr16 = { |
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.name = "cr16", |
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.rating = 300, |
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.read = read_cr16, |
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.mask = CLOCKSOURCE_MASK(BITS_PER_LONG), |
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.flags = CLOCK_SOURCE_IS_CONTINUOUS, |
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}; |
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void __init start_cpu_itimer(void) |
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{ |
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unsigned int cpu = smp_processor_id(); |
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unsigned long next_tick = mfctl(16) + clocktick; |
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mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */ |
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per_cpu(cpu_data, cpu).it_value = next_tick; |
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} |
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#if IS_ENABLED(CONFIG_RTC_DRV_GENERIC) |
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static int rtc_generic_get_time(struct device *dev, struct rtc_time *tm) |
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{ |
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struct pdc_tod tod_data; |
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memset(tm, 0, sizeof(*tm)); |
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if (pdc_tod_read(&tod_data) < 0) |
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return -EOPNOTSUPP; |
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/* we treat tod_sec as unsigned, so this can work until year 2106 */ |
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rtc_time64_to_tm(tod_data.tod_sec, tm); |
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return 0; |
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} |
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static int rtc_generic_set_time(struct device *dev, struct rtc_time *tm) |
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{ |
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time64_t secs = rtc_tm_to_time64(tm); |
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int ret; |
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/* hppa has Y2K38 problem: pdc_tod_set() takes an u32 value! */ |
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ret = pdc_tod_set(secs, 0); |
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if (ret != 0) { |
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pr_warn("pdc_tod_set(%lld) returned error %d\n", secs, ret); |
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if (ret == PDC_INVALID_ARG) |
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return -EINVAL; |
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return -EOPNOTSUPP; |
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} |
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return 0; |
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} |
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static const struct rtc_class_ops rtc_generic_ops = { |
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.read_time = rtc_generic_get_time, |
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.set_time = rtc_generic_set_time, |
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}; |
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static int __init rtc_init(void) |
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{ |
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struct platform_device *pdev; |
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pdev = platform_device_register_data(NULL, "rtc-generic", -1, |
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&rtc_generic_ops, |
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sizeof(rtc_generic_ops)); |
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return PTR_ERR_OR_ZERO(pdev); |
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} |
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device_initcall(rtc_init); |
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#endif |
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void read_persistent_clock64(struct timespec64 *ts) |
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{ |
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static struct pdc_tod tod_data; |
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if (pdc_tod_read(&tod_data) == 0) { |
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ts->tv_sec = tod_data.tod_sec; |
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ts->tv_nsec = tod_data.tod_usec * 1000; |
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} else { |
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printk(KERN_ERR "Error reading tod clock\n"); |
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ts->tv_sec = 0; |
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ts->tv_nsec = 0; |
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} |
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} |
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static u64 notrace read_cr16_sched_clock(void) |
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{ |
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return get_cycles(); |
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} |
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/* |
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* timer interrupt and sched_clock() initialization |
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*/ |
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void __init time_init(void) |
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{ |
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unsigned long cr16_hz; |
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clocktick = (100 * PAGE0->mem_10msec) / HZ; |
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start_cpu_itimer(); /* get CPU 0 started */ |
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cr16_hz = 100 * PAGE0->mem_10msec; /* Hz */ |
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/* register as sched_clock source */ |
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sched_clock_register(read_cr16_sched_clock, BITS_PER_LONG, cr16_hz); |
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} |
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static int __init init_cr16_clocksource(void) |
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{ |
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/* |
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* The cr16 interval timers are not syncronized across CPUs on |
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* different sockets, so mark them unstable and lower rating on |
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* multi-socket SMP systems. |
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*/ |
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if (num_online_cpus() > 1 && !running_on_qemu) { |
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int cpu; |
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unsigned long cpu0_loc; |
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cpu0_loc = per_cpu(cpu_data, 0).cpu_loc; |
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for_each_online_cpu(cpu) { |
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if (cpu == 0) |
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continue; |
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if ((cpu0_loc != 0) && |
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(cpu0_loc == per_cpu(cpu_data, cpu).cpu_loc)) |
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continue; |
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clocksource_cr16.name = "cr16_unstable"; |
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clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE; |
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clocksource_cr16.rating = 0; |
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break; |
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} |
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} |
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/* XXX: We may want to mark sched_clock stable here if cr16 clocks are |
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* in sync: |
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* (clocksource_cr16.flags == CLOCK_SOURCE_IS_CONTINUOUS) */ |
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/* register at clocksource framework */ |
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clocksource_register_hz(&clocksource_cr16, |
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100 * PAGE0->mem_10msec); |
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return 0; |
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} |
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device_initcall(init_cr16_clocksource);
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