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193 lines
4.9 KiB
193 lines
4.9 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* OpenRISC tlb.c |
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* |
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* Linux architectural port borrowing liberally from similar works of |
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* others. All original copyrights apply as per the original source |
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* declaration. |
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* |
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* Modifications for the OpenRISC architecture: |
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* Copyright (C) 2003 Matjaz Breskvar <[email protected]> |
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* Copyright (C) 2010-2011 Julius Baxter <[email protected]> |
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* Copyright (C) 2010-2011 Jonas Bonn <[email protected]> |
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*/ |
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#include <linux/sched.h> |
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#include <linux/kernel.h> |
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#include <linux/errno.h> |
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#include <linux/string.h> |
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#include <linux/types.h> |
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#include <linux/ptrace.h> |
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#include <linux/mman.h> |
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#include <linux/mm.h> |
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#include <linux/init.h> |
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#include <asm/tlbflush.h> |
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#include <asm/mmu_context.h> |
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#include <asm/spr_defs.h> |
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#define NO_CONTEXT -1 |
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#define NUM_DTLB_SETS (1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> \ |
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SPR_DMMUCFGR_NTS_OFF)) |
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#define NUM_ITLB_SETS (1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> \ |
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SPR_IMMUCFGR_NTS_OFF)) |
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#define DTLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_DTLB_SETS-1)) |
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#define ITLB_OFFSET(addr) (((addr) >> PAGE_SHIFT) & (NUM_ITLB_SETS-1)) |
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/* |
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* Invalidate all TLB entries. |
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* |
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* This comes down to setting the 'valid' bit for all xTLBMR registers to 0. |
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* Easiest way to accomplish this is to just zero out the xTLBMR register |
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* completely. |
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* |
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*/ |
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void local_flush_tlb_all(void) |
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{ |
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int i; |
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unsigned long num_tlb_sets; |
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/* Determine number of sets for IMMU. */ |
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/* FIXME: Assumption is I & D nsets equal. */ |
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num_tlb_sets = NUM_ITLB_SETS; |
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for (i = 0; i < num_tlb_sets; i++) { |
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mtspr_off(SPR_DTLBMR_BASE(0), i, 0); |
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mtspr_off(SPR_ITLBMR_BASE(0), i, 0); |
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} |
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} |
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#define have_dtlbeir (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_TEIRI) |
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#define have_itlbeir (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_TEIRI) |
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/* |
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* Invalidate a single page. This is what the xTLBEIR register is for. |
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* |
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* There's no point in checking the vma for PAGE_EXEC to determine whether it's |
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* the data or instruction TLB that should be flushed... that would take more |
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* than the few instructions that the following compiles down to! |
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* |
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* The case where we don't have the xTLBEIR register really only works for |
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* MMU's with a single way and is hard-coded that way. |
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*/ |
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#define flush_dtlb_page_eir(addr) mtspr(SPR_DTLBEIR, addr) |
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#define flush_dtlb_page_no_eir(addr) \ |
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mtspr_off(SPR_DTLBMR_BASE(0), DTLB_OFFSET(addr), 0); |
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#define flush_itlb_page_eir(addr) mtspr(SPR_ITLBEIR, addr) |
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#define flush_itlb_page_no_eir(addr) \ |
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mtspr_off(SPR_ITLBMR_BASE(0), ITLB_OFFSET(addr), 0); |
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void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) |
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{ |
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if (have_dtlbeir) |
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flush_dtlb_page_eir(addr); |
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else |
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flush_dtlb_page_no_eir(addr); |
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if (have_itlbeir) |
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flush_itlb_page_eir(addr); |
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else |
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flush_itlb_page_no_eir(addr); |
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} |
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void local_flush_tlb_range(struct vm_area_struct *vma, |
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unsigned long start, unsigned long end) |
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{ |
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int addr; |
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bool dtlbeir; |
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bool itlbeir; |
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dtlbeir = have_dtlbeir; |
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itlbeir = have_itlbeir; |
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for (addr = start; addr < end; addr += PAGE_SIZE) { |
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if (dtlbeir) |
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flush_dtlb_page_eir(addr); |
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else |
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flush_dtlb_page_no_eir(addr); |
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if (itlbeir) |
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flush_itlb_page_eir(addr); |
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else |
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flush_itlb_page_no_eir(addr); |
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} |
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} |
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/* |
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* Invalidate the selected mm context only. |
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* |
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* FIXME: Due to some bug here, we're flushing everything for now. |
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* This should be changed to loop over over mm and call flush_tlb_range. |
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*/ |
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void local_flush_tlb_mm(struct mm_struct *mm) |
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{ |
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/* Was seeing bugs with the mm struct passed to us. Scrapped most of |
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this function. */ |
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/* Several architctures do this */ |
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local_flush_tlb_all(); |
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} |
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/* called in schedule() just before actually doing the switch_to */ |
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void switch_mm(struct mm_struct *prev, struct mm_struct *next, |
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struct task_struct *next_tsk) |
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{ |
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unsigned int cpu; |
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if (unlikely(prev == next)) |
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return; |
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cpu = smp_processor_id(); |
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cpumask_clear_cpu(cpu, mm_cpumask(prev)); |
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cpumask_set_cpu(cpu, mm_cpumask(next)); |
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/* remember the pgd for the fault handlers |
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* this is similar to the pgd register in some other CPU's. |
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* we need our own copy of it because current and active_mm |
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* might be invalid at points where we still need to derefer |
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* the pgd. |
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*/ |
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current_pgd[cpu] = next->pgd; |
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/* We don't have context support implemented, so flush all |
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* entries belonging to previous map |
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*/ |
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local_flush_tlb_mm(prev); |
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} |
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/* |
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* Initialize the context related info for a new mm_struct |
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* instance. |
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*/ |
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int init_new_context(struct task_struct *tsk, struct mm_struct *mm) |
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{ |
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mm->context = NO_CONTEXT; |
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return 0; |
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} |
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/* called by __exit_mm to destroy the used MMU context if any before |
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* destroying the mm itself. this is only called when the last user of the mm |
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* drops it. |
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*/ |
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void destroy_context(struct mm_struct *mm) |
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{ |
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flush_tlb_mm(mm); |
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} |
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/* called once during VM initialization, from init.c */ |
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void __init tlb_init(void) |
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{ |
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/* Do nothing... */ |
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/* invalidate the entire TLB */ |
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/* flush_tlb_all(); */ |
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}
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