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125 lines
3.0 KiB
125 lines
3.0 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* OpenRISC Linux |
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* |
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* Linux architectural port borrowing liberally from similar works of |
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* others. All original copyrights apply as per the original source |
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* declaration. |
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* |
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* Modifications for the OpenRISC architecture: |
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* Copyright (C) 2003 Matjaz Breskvar <[email protected]> |
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* Copyright (C) 2010-2011 Jonas Bonn <[email protected]> |
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* |
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* DMA mapping callbacks... |
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*/ |
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#include <linux/dma-map-ops.h> |
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#include <linux/pagewalk.h> |
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#include <asm/cpuinfo.h> |
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#include <asm/spr_defs.h> |
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#include <asm/tlbflush.h> |
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static int |
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page_set_nocache(pte_t *pte, unsigned long addr, |
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unsigned long next, struct mm_walk *walk) |
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{ |
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unsigned long cl; |
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struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()]; |
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pte_val(*pte) |= _PAGE_CI; |
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/* |
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* Flush the page out of the TLB so that the new page flags get |
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* picked up next time there's an access |
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*/ |
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flush_tlb_page(NULL, addr); |
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/* Flush page out of dcache */ |
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for (cl = __pa(addr); cl < __pa(next); cl += cpuinfo->dcache_block_size) |
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mtspr(SPR_DCBFR, cl); |
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return 0; |
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} |
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static const struct mm_walk_ops set_nocache_walk_ops = { |
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.pte_entry = page_set_nocache, |
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}; |
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static int |
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page_clear_nocache(pte_t *pte, unsigned long addr, |
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unsigned long next, struct mm_walk *walk) |
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{ |
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pte_val(*pte) &= ~_PAGE_CI; |
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/* |
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* Flush the page out of the TLB so that the new page flags get |
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* picked up next time there's an access |
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*/ |
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flush_tlb_page(NULL, addr); |
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return 0; |
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} |
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static const struct mm_walk_ops clear_nocache_walk_ops = { |
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.pte_entry = page_clear_nocache, |
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}; |
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void *arch_dma_set_uncached(void *cpu_addr, size_t size) |
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{ |
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unsigned long va = (unsigned long)cpu_addr; |
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int error; |
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/* |
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* We need to iterate through the pages, clearing the dcache for |
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* them and setting the cache-inhibit bit. |
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*/ |
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mmap_read_lock(&init_mm); |
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error = walk_page_range(&init_mm, va, va + size, &set_nocache_walk_ops, |
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NULL); |
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mmap_read_unlock(&init_mm); |
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if (error) |
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return ERR_PTR(error); |
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return cpu_addr; |
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} |
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void arch_dma_clear_uncached(void *cpu_addr, size_t size) |
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{ |
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unsigned long va = (unsigned long)cpu_addr; |
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mmap_read_lock(&init_mm); |
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/* walk_page_range shouldn't be able to fail here */ |
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WARN_ON(walk_page_range(&init_mm, va, va + size, |
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&clear_nocache_walk_ops, NULL)); |
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mmap_read_unlock(&init_mm); |
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} |
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void arch_sync_dma_for_device(phys_addr_t addr, size_t size, |
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enum dma_data_direction dir) |
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{ |
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unsigned long cl; |
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struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()]; |
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switch (dir) { |
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case DMA_TO_DEVICE: |
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/* Flush the dcache for the requested range */ |
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for (cl = addr; cl < addr + size; |
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cl += cpuinfo->dcache_block_size) |
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mtspr(SPR_DCBFR, cl); |
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break; |
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case DMA_FROM_DEVICE: |
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/* Invalidate the dcache for the requested range */ |
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for (cl = addr; cl < addr + size; |
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cl += cpuinfo->dcache_block_size) |
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mtspr(SPR_DCBIR, cl); |
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break; |
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default: |
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/* |
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* NOTE: If dir == DMA_BIDIRECTIONAL then there's no need to |
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* flush nor invalidate the cache here as the area will need |
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* to be manually synced anyway. |
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*/ |
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break; |
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} |
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}
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