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149 lines
3.5 KiB
149 lines
3.5 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* ip30-smp.c: SMP on IP30 architecture. |
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* Based off of the original IP30 SMP code, with inspiration from ip27-smp.c |
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* and smp-bmips.c. |
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* |
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* Copyright (C) 2005-2007 Stanislaw Skowronek <[email protected]> |
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* 2006-2007, 2014-2015 Joshua Kinard <[email protected]> |
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* 2009 Johannes Dickgreber <[email protected]> |
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*/ |
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#include <linux/init.h> |
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#include <linux/sched.h> |
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#include <linux/sched/task_stack.h> |
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#include <asm/time.h> |
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#include <asm/sgi/heart.h> |
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#include "ip30-common.h" |
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#define MPCONF_MAGIC 0xbaddeed2 |
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#define MPCONF_ADDR 0xa800000000000600L |
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#define MPCONF_SIZE 0x80 |
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#define MPCONF(x) (MPCONF_ADDR + (x) * MPCONF_SIZE) |
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/* HEART can theoretically do 4 CPUs, but only 2 are physically possible */ |
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#define MP_NCPU 2 |
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struct mpconf { |
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u32 magic; |
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u32 prid; |
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u32 physid; |
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u32 virtid; |
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u32 scachesz; |
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u16 fanloads; |
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u16 res; |
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void *launch; |
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void *rendezvous; |
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u64 res2[3]; |
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void *stackaddr; |
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void *lnch_parm; |
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void *rndv_parm; |
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u32 idleflag; |
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}; |
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static void ip30_smp_send_ipi_single(int cpu, u32 action) |
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{ |
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int irq; |
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switch (action) { |
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case SMP_RESCHEDULE_YOURSELF: |
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irq = HEART_L2_INT_RESCHED_CPU_0; |
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break; |
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case SMP_CALL_FUNCTION: |
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irq = HEART_L2_INT_CALL_CPU_0; |
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break; |
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default: |
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panic("IP30: Unknown action value in %s!\n", __func__); |
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} |
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irq += cpu; |
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/* Poke the other CPU -- it's got mail! */ |
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heart_write(BIT_ULL(irq), &heart_regs->set_isr); |
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} |
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static void ip30_smp_send_ipi_mask(const struct cpumask *mask, u32 action) |
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{ |
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u32 i; |
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for_each_cpu(i, mask) |
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ip30_smp_send_ipi_single(i, action); |
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} |
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static void __init ip30_smp_setup(void) |
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{ |
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int i; |
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int ncpu = 0; |
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struct mpconf *mpc; |
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init_cpu_possible(cpumask_of(0)); |
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/* Scan the MPCONF structure and enumerate available CPUs. */ |
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for (i = 0; i < MP_NCPU; i++) { |
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mpc = (struct mpconf *)MPCONF(i); |
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if (mpc->magic == MPCONF_MAGIC) { |
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set_cpu_possible(i, true); |
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__cpu_number_map[i] = ++ncpu; |
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__cpu_logical_map[ncpu] = i; |
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pr_info("IP30: Slot: %d, PrID: %.8x, PhyID: %d, VirtID: %d\n", |
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i, mpc->prid, mpc->physid, mpc->virtid); |
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} |
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} |
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pr_info("IP30: Detected %d CPU(s) present.\n", ncpu); |
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/* |
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* Set the coherency algorithm to '5' (cacheable coherent |
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* exclusive on write). This is needed on IP30 SMP, especially |
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* for R14000 CPUs, otherwise, instruction bus errors will |
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* occur upon reaching userland. |
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*/ |
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change_c0_config(CONF_CM_CMASK, CONF_CM_CACHABLE_COW); |
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} |
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static void __init ip30_smp_prepare_cpus(unsigned int max_cpus) |
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{ |
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/* nothing to do here */ |
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} |
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static int __init ip30_smp_boot_secondary(int cpu, struct task_struct *idle) |
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{ |
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struct mpconf *mpc = (struct mpconf *)MPCONF(cpu); |
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/* Stack pointer (sp). */ |
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mpc->stackaddr = (void *)__KSTK_TOS(idle); |
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/* Global pointer (gp). */ |
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mpc->lnch_parm = task_thread_info(idle); |
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mb(); /* make sure stack and lparm are written */ |
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/* Boot CPUx. */ |
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mpc->launch = smp_bootstrap; |
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/* CPUx now executes smp_bootstrap, then ip30_smp_finish */ |
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return 0; |
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} |
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static void __init ip30_smp_init_cpu(void) |
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{ |
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ip30_per_cpu_init(); |
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} |
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static void __init ip30_smp_finish(void) |
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{ |
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enable_percpu_irq(get_c0_compare_int(), IRQ_TYPE_NONE); |
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local_irq_enable(); |
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} |
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struct plat_smp_ops __read_mostly ip30_smp_ops = { |
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.send_ipi_single = ip30_smp_send_ipi_single, |
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.send_ipi_mask = ip30_smp_send_ipi_mask, |
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.smp_setup = ip30_smp_setup, |
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.prepare_cpus = ip30_smp_prepare_cpus, |
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.boot_secondary = ip30_smp_boot_secondary, |
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.init_secondary = ip30_smp_init_cpu, |
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.smp_finish = ip30_smp_finish, |
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.prepare_boot_cpu = ip30_smp_init_cpu, |
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};
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