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759 lines
20 KiB
759 lines
20 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2003 Christoph Hellwig ([email protected]) |
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* Copyright (C) 1999, 2000, 04 Ralf Baechle ([email protected]) |
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/export.h> |
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#include <linux/pci.h> |
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#include <linux/smp.h> |
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#include <linux/dma-direct.h> |
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#include <linux/platform_device.h> |
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#include <linux/platform_data/xtalk-bridge.h> |
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#include <linux/nvmem-consumer.h> |
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#include <linux/crc16.h> |
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|
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#include <asm/pci/bridge.h> |
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#include <asm/paccess.h> |
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#include <asm/sn/irq_alloc.h> |
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#include <asm/sn/ioc3.h> |
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|
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#define CRC16_INIT 0 |
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#define CRC16_VALID 0xb001 |
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|
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/* |
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* Common phys<->dma mapping for platforms using pci xtalk bridge |
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*/ |
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dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) |
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{ |
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struct pci_dev *pdev = to_pci_dev(dev); |
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struct bridge_controller *bc = BRIDGE_CONTROLLER(pdev->bus); |
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return bc->baddr + paddr; |
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} |
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phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dma_addr) |
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{ |
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return dma_addr & ~(0xffUL << 56); |
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} |
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/* |
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* Most of the IOC3 PCI config register aren't present |
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* we emulate what is needed for a normal PCI enumeration |
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*/ |
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static int ioc3_cfg_rd(void *addr, int where, int size, u32 *value, u32 sid) |
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{ |
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u32 cf, shift, mask; |
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switch (where & ~3) { |
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case 0x00 ... 0x10: |
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case 0x40 ... 0x44: |
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if (get_dbe(cf, (u32 *)addr)) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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break; |
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case 0x2c: |
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cf = sid; |
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break; |
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case 0x3c: |
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/* emulate sane interrupt pin value */ |
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cf = 0x00000100; |
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break; |
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default: |
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cf = 0; |
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break; |
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} |
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shift = (where & 3) << 3; |
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mask = 0xffffffffU >> ((4 - size) << 3); |
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*value = (cf >> shift) & mask; |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int ioc3_cfg_wr(void *addr, int where, int size, u32 value) |
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{ |
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u32 cf, shift, mask, smask; |
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if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) |
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return PCIBIOS_SUCCESSFUL; |
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if (get_dbe(cf, (u32 *)addr)) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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shift = ((where & 3) << 3); |
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mask = (0xffffffffU >> ((4 - size) << 3)); |
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smask = mask << shift; |
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cf = (cf & ~smask) | ((value & mask) << shift); |
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if (put_dbe(cf, (u32 *)addr)) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static void bridge_disable_swapping(struct pci_dev *dev) |
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{ |
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struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus); |
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int slot = PCI_SLOT(dev->devfn); |
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/* Turn off byte swapping */ |
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bridge_clr(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR); |
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bridge_read(bc, b_widget.w_tflush); /* Flush */ |
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} |
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, |
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bridge_disable_swapping); |
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/* |
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* The Bridge ASIC supports both type 0 and type 1 access. Type 1 is |
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* not really documented, so right now I can't write code which uses it. |
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* Therefore we use type 0 accesses for now even though they won't work |
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* correctly for PCI-to-PCI bridges. |
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* |
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* The function is complicated by the ultimate brokenness of the IOC3 chip |
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* which is used in SGI systems. The IOC3 can only handle 32-bit PCI |
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* accesses and does only decode parts of it's address space. |
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*/ |
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static int pci_conf0_read_config(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 *value) |
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{ |
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struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); |
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struct bridge_regs *bridge = bc->base; |
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int slot = PCI_SLOT(devfn); |
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int fn = PCI_FUNC(devfn); |
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void *addr; |
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u32 cf; |
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int res; |
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID]; |
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if (get_dbe(cf, (u32 *)addr)) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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/* |
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* IOC3 is broken beyond belief ... Don't even give the |
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* generic PCI code a chance to look at it for real ... |
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*/ |
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if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) { |
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; |
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return ioc3_cfg_rd(addr, where, size, value, |
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bc->ioc3_sid[slot]); |
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} |
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)]; |
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if (size == 1) |
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res = get_dbe(*value, (u8 *)addr); |
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else if (size == 2) |
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res = get_dbe(*value, (u16 *)addr); |
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else |
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res = get_dbe(*value, (u32 *)addr); |
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return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; |
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} |
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static int pci_conf1_read_config(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 *value) |
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{ |
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struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); |
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struct bridge_regs *bridge = bc->base; |
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int busno = bus->number; |
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int slot = PCI_SLOT(devfn); |
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int fn = PCI_FUNC(devfn); |
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void *addr; |
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u32 cf; |
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int res; |
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bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11)); |
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addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID]; |
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if (get_dbe(cf, (u32 *)addr)) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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/* |
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* IOC3 is broken beyond belief ... Don't even give the |
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* generic PCI code a chance to look at it for real ... |
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*/ |
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if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) { |
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addr = &bridge->b_type1_cfg.c[(fn << 8) | (where & ~3)]; |
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return ioc3_cfg_rd(addr, where, size, value, |
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bc->ioc3_sid[slot]); |
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} |
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addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))]; |
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if (size == 1) |
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res = get_dbe(*value, (u8 *)addr); |
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else if (size == 2) |
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res = get_dbe(*value, (u16 *)addr); |
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else |
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res = get_dbe(*value, (u32 *)addr); |
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return res ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; |
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} |
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static int pci_read_config(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 *value) |
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{ |
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if (!pci_is_root_bus(bus)) |
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return pci_conf1_read_config(bus, devfn, where, size, value); |
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return pci_conf0_read_config(bus, devfn, where, size, value); |
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} |
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static int pci_conf0_write_config(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 value) |
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{ |
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struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); |
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struct bridge_regs *bridge = bc->base; |
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int slot = PCI_SLOT(devfn); |
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int fn = PCI_FUNC(devfn); |
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void *addr; |
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u32 cf; |
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int res; |
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[PCI_VENDOR_ID]; |
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if (get_dbe(cf, (u32 *)addr)) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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/* |
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* IOC3 is broken beyond belief ... Don't even give the |
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* generic PCI code a chance to look at it for real ... |
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*/ |
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if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) { |
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; |
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return ioc3_cfg_wr(addr, where, size, value); |
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} |
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].c[where ^ (4 - size)]; |
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if (size == 1) |
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res = put_dbe(value, (u8 *)addr); |
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else if (size == 2) |
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res = put_dbe(value, (u16 *)addr); |
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else |
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res = put_dbe(value, (u32 *)addr); |
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if (res) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int pci_conf1_write_config(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 value) |
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{ |
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struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); |
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struct bridge_regs *bridge = bc->base; |
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int slot = PCI_SLOT(devfn); |
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int fn = PCI_FUNC(devfn); |
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int busno = bus->number; |
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void *addr; |
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u32 cf; |
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int res; |
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bridge_write(bc, b_pci_cfg, (busno << 16) | (slot << 11)); |
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addr = &bridge->b_type1_cfg.c[(fn << 8) | PCI_VENDOR_ID]; |
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if (get_dbe(cf, (u32 *)addr)) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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/* |
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* IOC3 is broken beyond belief ... Don't even give the |
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* generic PCI code a chance to look at it for real ... |
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*/ |
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if (cf == (PCI_VENDOR_ID_SGI | (PCI_DEVICE_ID_SGI_IOC3 << 16))) { |
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addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; |
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return ioc3_cfg_wr(addr, where, size, value); |
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} |
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addr = &bridge->b_type1_cfg.c[(fn << 8) | (where ^ (4 - size))]; |
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if (size == 1) |
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res = put_dbe(value, (u8 *)addr); |
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else if (size == 2) |
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res = put_dbe(value, (u16 *)addr); |
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else |
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res = put_dbe(value, (u32 *)addr); |
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if (res) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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return PCIBIOS_SUCCESSFUL; |
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} |
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static int pci_write_config(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 value) |
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{ |
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if (!pci_is_root_bus(bus)) |
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return pci_conf1_write_config(bus, devfn, where, size, value); |
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return pci_conf0_write_config(bus, devfn, where, size, value); |
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} |
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static struct pci_ops bridge_pci_ops = { |
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.read = pci_read_config, |
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.write = pci_write_config, |
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}; |
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struct bridge_irq_chip_data { |
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struct bridge_controller *bc; |
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nasid_t nasid; |
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}; |
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static int bridge_set_affinity(struct irq_data *d, const struct cpumask *mask, |
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bool force) |
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{ |
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#ifdef CONFIG_NUMA |
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struct bridge_irq_chip_data *data = d->chip_data; |
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int bit = d->parent_data->hwirq; |
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int pin = d->hwirq; |
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int ret, cpu; |
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ret = irq_chip_set_affinity_parent(d, mask, force); |
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if (ret >= 0) { |
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cpu = cpumask_first_and(mask, cpu_online_mask); |
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data->nasid = cpu_to_node(cpu); |
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bridge_write(data->bc, b_int_addr[pin].addr, |
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(((data->bc->intr_addr >> 30) & 0x30000) | |
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bit | (data->nasid << 8))); |
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bridge_read(data->bc, b_wid_tflush); |
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} |
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return ret; |
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#else |
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return irq_chip_set_affinity_parent(d, mask, force); |
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#endif |
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} |
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struct irq_chip bridge_irq_chip = { |
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.name = "BRIDGE", |
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.irq_mask = irq_chip_mask_parent, |
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.irq_unmask = irq_chip_unmask_parent, |
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.irq_set_affinity = bridge_set_affinity |
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}; |
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static int bridge_domain_alloc(struct irq_domain *domain, unsigned int virq, |
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unsigned int nr_irqs, void *arg) |
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{ |
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struct bridge_irq_chip_data *data; |
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struct irq_alloc_info *info = arg; |
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int ret; |
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if (nr_irqs > 1 || !info) |
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return -EINVAL; |
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data = kzalloc(sizeof(*data), GFP_KERNEL); |
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if (!data) |
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return -ENOMEM; |
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ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg); |
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if (ret >= 0) { |
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data->bc = info->ctrl; |
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data->nasid = info->nasid; |
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irq_domain_set_info(domain, virq, info->pin, &bridge_irq_chip, |
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data, handle_level_irq, NULL, NULL); |
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} else { |
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kfree(data); |
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} |
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return ret; |
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} |
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static void bridge_domain_free(struct irq_domain *domain, unsigned int virq, |
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unsigned int nr_irqs) |
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{ |
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struct irq_data *irqd = irq_domain_get_irq_data(domain, virq); |
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if (nr_irqs) |
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return; |
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kfree(irqd->chip_data); |
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irq_domain_free_irqs_top(domain, virq, nr_irqs); |
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} |
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static int bridge_domain_activate(struct irq_domain *domain, |
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struct irq_data *irqd, bool reserve) |
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{ |
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struct bridge_irq_chip_data *data = irqd->chip_data; |
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struct bridge_controller *bc = data->bc; |
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int bit = irqd->parent_data->hwirq; |
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int pin = irqd->hwirq; |
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u32 device; |
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bridge_write(bc, b_int_addr[pin].addr, |
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(((bc->intr_addr >> 30) & 0x30000) | |
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bit | (data->nasid << 8))); |
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bridge_set(bc, b_int_enable, (1 << pin)); |
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bridge_set(bc, b_int_enable, 0x7ffffe00); /* more stuff in int_enable */ |
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/* |
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* Enable sending of an interrupt clear packt to the hub on a high to |
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* low transition of the interrupt pin. |
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* |
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* IRIX sets additional bits in the address which are documented as |
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* reserved in the bridge docs. |
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*/ |
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bridge_set(bc, b_int_mode, (1UL << pin)); |
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/* |
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* We assume the bridge to have a 1:1 mapping between devices |
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* (slots) and intr pins. |
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*/ |
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device = bridge_read(bc, b_int_device); |
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device &= ~(7 << (pin*3)); |
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device |= (pin << (pin*3)); |
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bridge_write(bc, b_int_device, device); |
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bridge_read(bc, b_wid_tflush); |
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return 0; |
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} |
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static void bridge_domain_deactivate(struct irq_domain *domain, |
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struct irq_data *irqd) |
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{ |
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struct bridge_irq_chip_data *data = irqd->chip_data; |
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bridge_clr(data->bc, b_int_enable, (1 << irqd->hwirq)); |
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bridge_read(data->bc, b_wid_tflush); |
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} |
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static const struct irq_domain_ops bridge_domain_ops = { |
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.alloc = bridge_domain_alloc, |
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.free = bridge_domain_free, |
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.activate = bridge_domain_activate, |
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.deactivate = bridge_domain_deactivate |
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}; |
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|
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/* |
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* All observed requests have pin == 1. We could have a global here, that |
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* gets incremented and returned every time - unfortunately, pci_map_irq |
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* may be called on the same device over and over, and need to return the |
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* same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7]. |
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* |
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* A given PCI device, in general, should be able to intr any of the cpus |
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* on any one of the hubs connected to its xbow. |
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*/ |
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static int bridge_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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{ |
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struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus); |
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struct irq_alloc_info info; |
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int irq; |
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switch (pin) { |
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case PCI_INTERRUPT_UNKNOWN: |
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case PCI_INTERRUPT_INTA: |
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case PCI_INTERRUPT_INTC: |
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pin = 0; |
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break; |
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case PCI_INTERRUPT_INTB: |
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case PCI_INTERRUPT_INTD: |
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pin = 1; |
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} |
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irq = bc->pci_int[slot][pin]; |
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if (irq == -1) { |
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info.ctrl = bc; |
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info.nasid = bc->nasid; |
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info.pin = bc->int_mapping[slot][pin]; |
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irq = irq_domain_alloc_irqs(bc->domain, 1, bc->nasid, &info); |
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if (irq < 0) |
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return irq; |
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bc->pci_int[slot][pin] = irq; |
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} |
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return irq; |
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} |
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#define IOC3_SID(sid) (PCI_VENDOR_ID_SGI | ((sid) << 16)) |
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static void bridge_setup_ip27_baseio6g(struct bridge_controller *bc) |
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{ |
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bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP27_BASEIO6G); |
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bc->ioc3_sid[6] = IOC3_SID(IOC3_SUBSYS_IP27_MIO); |
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bc->int_mapping[2][1] = 4; |
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bc->int_mapping[6][1] = 6; |
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} |
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static void bridge_setup_ip27_baseio(struct bridge_controller *bc) |
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{ |
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bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP27_BASEIO); |
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bc->int_mapping[2][1] = 4; |
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} |
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|
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static void bridge_setup_ip29_baseio(struct bridge_controller *bc) |
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{ |
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bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP29_SYSBOARD); |
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bc->int_mapping[2][1] = 3; |
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} |
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|
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static void bridge_setup_ip30_sysboard(struct bridge_controller *bc) |
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{ |
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bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_IP30_SYSBOARD); |
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bc->int_mapping[2][1] = 4; |
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} |
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static void bridge_setup_menet(struct bridge_controller *bc) |
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{ |
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bc->ioc3_sid[0] = IOC3_SID(IOC3_SUBSYS_MENET); |
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bc->ioc3_sid[1] = IOC3_SID(IOC3_SUBSYS_MENET); |
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bc->ioc3_sid[2] = IOC3_SID(IOC3_SUBSYS_MENET); |
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bc->ioc3_sid[3] = IOC3_SID(IOC3_SUBSYS_MENET4); |
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} |
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|
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static void bridge_setup_io7(struct bridge_controller *bc) |
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{ |
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bc->ioc3_sid[4] = IOC3_SID(IOC3_SUBSYS_IO7); |
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} |
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|
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static void bridge_setup_io8(struct bridge_controller *bc) |
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{ |
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bc->ioc3_sid[4] = IOC3_SID(IOC3_SUBSYS_IO8); |
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} |
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|
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static void bridge_setup_io9(struct bridge_controller *bc) |
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{ |
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bc->ioc3_sid[1] = IOC3_SID(IOC3_SUBSYS_IO9); |
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} |
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|
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static void bridge_setup_ip34_fuel_sysboard(struct bridge_controller *bc) |
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{ |
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bc->ioc3_sid[4] = IOC3_SID(IOC3_SUBSYS_IP34_SYSBOARD); |
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} |
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|
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#define BRIDGE_BOARD_SETUP(_partno, _setup) \ |
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{ .match = _partno, .setup = _setup } |
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|
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static const struct { |
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char *match; |
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void (*setup)(struct bridge_controller *bc); |
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} bridge_ioc3_devid[] = { |
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BRIDGE_BOARD_SETUP("030-0734-", bridge_setup_ip27_baseio6g), |
|
BRIDGE_BOARD_SETUP("030-0880-", bridge_setup_ip27_baseio6g), |
|
BRIDGE_BOARD_SETUP("030-1023-", bridge_setup_ip27_baseio), |
|
BRIDGE_BOARD_SETUP("030-1124-", bridge_setup_ip27_baseio), |
|
BRIDGE_BOARD_SETUP("030-1025-", bridge_setup_ip29_baseio), |
|
BRIDGE_BOARD_SETUP("030-1244-", bridge_setup_ip29_baseio), |
|
BRIDGE_BOARD_SETUP("030-1389-", bridge_setup_ip29_baseio), |
|
BRIDGE_BOARD_SETUP("030-0887-", bridge_setup_ip30_sysboard), |
|
BRIDGE_BOARD_SETUP("030-1467-", bridge_setup_ip30_sysboard), |
|
BRIDGE_BOARD_SETUP("030-0873-", bridge_setup_menet), |
|
BRIDGE_BOARD_SETUP("030-1557-", bridge_setup_io7), |
|
BRIDGE_BOARD_SETUP("030-1673-", bridge_setup_io8), |
|
BRIDGE_BOARD_SETUP("030-1771-", bridge_setup_io9), |
|
BRIDGE_BOARD_SETUP("030-1707-", bridge_setup_ip34_fuel_sysboard), |
|
}; |
|
|
|
static void bridge_setup_board(struct bridge_controller *bc, char *partnum) |
|
{ |
|
int i; |
|
|
|
for (i = 0; i < ARRAY_SIZE(bridge_ioc3_devid); i++) |
|
if (!strncmp(partnum, bridge_ioc3_devid[i].match, |
|
strlen(bridge_ioc3_devid[i].match))) { |
|
bridge_ioc3_devid[i].setup(bc); |
|
} |
|
} |
|
|
|
static int bridge_nvmem_match(struct device *dev, const void *data) |
|
{ |
|
const char *name = dev_name(dev); |
|
const char *prefix = data; |
|
|
|
if (strlen(name) < strlen(prefix)) |
|
return 0; |
|
|
|
return memcmp(prefix, dev_name(dev), strlen(prefix)) == 0; |
|
} |
|
|
|
static int bridge_get_partnum(u64 baddr, char *partnum) |
|
{ |
|
struct nvmem_device *nvmem; |
|
char prefix[24]; |
|
u8 prom[64]; |
|
int i, j; |
|
int ret; |
|
|
|
snprintf(prefix, sizeof(prefix), "bridge-%012llx-0b-", baddr); |
|
|
|
nvmem = nvmem_device_find(prefix, bridge_nvmem_match); |
|
if (IS_ERR(nvmem)) |
|
return PTR_ERR(nvmem); |
|
|
|
ret = nvmem_device_read(nvmem, 0, 64, prom); |
|
nvmem_device_put(nvmem); |
|
|
|
if (ret != 64) |
|
return ret; |
|
|
|
if (crc16(CRC16_INIT, prom, 32) != CRC16_VALID || |
|
crc16(CRC16_INIT, prom + 32, 32) != CRC16_VALID) |
|
return -EINVAL; |
|
|
|
/* Assemble part number */ |
|
j = 0; |
|
for (i = 0; i < 19; i++) |
|
if (prom[i + 11] != ' ') |
|
partnum[j++] = prom[i + 11]; |
|
|
|
for (i = 0; i < 6; i++) |
|
if (prom[i + 32] != ' ') |
|
partnum[j++] = prom[i + 32]; |
|
|
|
partnum[j] = 0; |
|
|
|
return 0; |
|
} |
|
|
|
static int bridge_probe(struct platform_device *pdev) |
|
{ |
|
struct xtalk_bridge_platform_data *bd = dev_get_platdata(&pdev->dev); |
|
struct device *dev = &pdev->dev; |
|
struct bridge_controller *bc; |
|
struct pci_host_bridge *host; |
|
struct irq_domain *domain, *parent; |
|
struct fwnode_handle *fn; |
|
char partnum[26]; |
|
int slot; |
|
int err; |
|
|
|
/* get part number from one wire prom */ |
|
if (bridge_get_partnum(virt_to_phys((void *)bd->bridge_addr), partnum)) |
|
return -EPROBE_DEFER; /* not available yet */ |
|
|
|
parent = irq_get_default_host(); |
|
if (!parent) |
|
return -ENODEV; |
|
fn = irq_domain_alloc_named_fwnode("BRIDGE"); |
|
if (!fn) |
|
return -ENOMEM; |
|
domain = irq_domain_create_hierarchy(parent, 0, 8, fn, |
|
&bridge_domain_ops, NULL); |
|
if (!domain) { |
|
irq_domain_free_fwnode(fn); |
|
return -ENOMEM; |
|
} |
|
|
|
pci_set_flags(PCI_PROBE_ONLY); |
|
|
|
host = devm_pci_alloc_host_bridge(dev, sizeof(*bc)); |
|
if (!host) { |
|
err = -ENOMEM; |
|
goto err_remove_domain; |
|
} |
|
|
|
bc = pci_host_bridge_priv(host); |
|
|
|
bc->busn.name = "Bridge PCI busn"; |
|
bc->busn.start = 0; |
|
bc->busn.end = 0xff; |
|
bc->busn.flags = IORESOURCE_BUS; |
|
|
|
bc->domain = domain; |
|
|
|
pci_add_resource_offset(&host->windows, &bd->mem, bd->mem_offset); |
|
pci_add_resource_offset(&host->windows, &bd->io, bd->io_offset); |
|
pci_add_resource(&host->windows, &bc->busn); |
|
|
|
err = devm_request_pci_bus_resources(dev, &host->windows); |
|
if (err < 0) |
|
goto err_free_resource; |
|
|
|
bc->nasid = bd->nasid; |
|
|
|
bc->baddr = (u64)bd->masterwid << 60 | PCI64_ATTR_BAR; |
|
bc->base = (struct bridge_regs *)bd->bridge_addr; |
|
bc->intr_addr = bd->intr_addr; |
|
|
|
/* |
|
* Clear all pending interrupts. |
|
*/ |
|
bridge_write(bc, b_int_rst_stat, BRIDGE_IRR_ALL_CLR); |
|
|
|
/* |
|
* Until otherwise set up, assume all interrupts are from slot 0 |
|
*/ |
|
bridge_write(bc, b_int_device, 0x0); |
|
|
|
/* |
|
* disable swapping for big windows |
|
*/ |
|
bridge_clr(bc, b_wid_control, |
|
BRIDGE_CTRL_IO_SWAP | BRIDGE_CTRL_MEM_SWAP); |
|
#ifdef CONFIG_PAGE_SIZE_4KB |
|
bridge_clr(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE); |
|
#else /* 16kB or larger */ |
|
bridge_set(bc, b_wid_control, BRIDGE_CTRL_PAGE_SIZE); |
|
#endif |
|
|
|
/* |
|
* Hmm... IRIX sets additional bits in the address which |
|
* are documented as reserved in the bridge docs. |
|
*/ |
|
bridge_write(bc, b_wid_int_upper, |
|
((bc->intr_addr >> 32) & 0xffff) | (bd->masterwid << 16)); |
|
bridge_write(bc, b_wid_int_lower, bc->intr_addr & 0xffffffff); |
|
bridge_write(bc, b_dir_map, (bd->masterwid << 20)); /* DMA */ |
|
bridge_write(bc, b_int_enable, 0); |
|
|
|
for (slot = 0; slot < 8; slot++) { |
|
bridge_set(bc, b_device[slot].reg, BRIDGE_DEV_SWAP_DIR); |
|
bc->pci_int[slot][0] = -1; |
|
bc->pci_int[slot][1] = -1; |
|
/* default interrupt pin mapping */ |
|
bc->int_mapping[slot][0] = slot; |
|
bc->int_mapping[slot][1] = slot ^ 4; |
|
} |
|
bridge_read(bc, b_wid_tflush); /* wait until Bridge PIO complete */ |
|
|
|
bridge_setup_board(bc, partnum); |
|
|
|
host->dev.parent = dev; |
|
host->sysdata = bc; |
|
host->busnr = 0; |
|
host->ops = &bridge_pci_ops; |
|
host->map_irq = bridge_map_irq; |
|
host->swizzle_irq = pci_common_swizzle; |
|
|
|
err = pci_scan_root_bus_bridge(host); |
|
if (err < 0) |
|
goto err_free_resource; |
|
|
|
pci_bus_claim_resources(host->bus); |
|
pci_bus_add_devices(host->bus); |
|
|
|
platform_set_drvdata(pdev, host->bus); |
|
|
|
return 0; |
|
|
|
err_free_resource: |
|
pci_free_resource_list(&host->windows); |
|
err_remove_domain: |
|
irq_domain_remove(domain); |
|
irq_domain_free_fwnode(fn); |
|
return err; |
|
} |
|
|
|
static int bridge_remove(struct platform_device *pdev) |
|
{ |
|
struct pci_bus *bus = platform_get_drvdata(pdev); |
|
struct bridge_controller *bc = BRIDGE_CONTROLLER(bus); |
|
struct fwnode_handle *fn = bc->domain->fwnode; |
|
|
|
irq_domain_remove(bc->domain); |
|
irq_domain_free_fwnode(fn); |
|
pci_lock_rescan_remove(); |
|
pci_stop_root_bus(bus); |
|
pci_remove_root_bus(bus); |
|
pci_unlock_rescan_remove(); |
|
|
|
return 0; |
|
} |
|
|
|
static struct platform_driver bridge_driver = { |
|
.probe = bridge_probe, |
|
.remove = bridge_remove, |
|
.driver = { |
|
.name = "xtalk-bridge", |
|
} |
|
}; |
|
|
|
builtin_platform_driver(bridge_driver);
|
|
|