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231 lines
7.3 KiB
231 lines
7.3 KiB
/* |
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* BRIEF MODULE DESCRIPTION |
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* PCI initialization for IDT EB434 board |
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* |
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* Copyright 2004 IDT Inc. ([email protected]) |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License as published by the |
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* Free Software Foundation; either version 2 of the License, or (at your |
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* option) any later version. |
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* |
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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* You should have received a copy of the GNU General Public License along |
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* with this program; if not, write to the Free Software Foundation, Inc., |
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* 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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#include <linux/types.h> |
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#include <linux/pci.h> |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <asm/mach-rc32434/rc32434.h> |
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#include <asm/mach-rc32434/pci.h> |
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#define PCI_ACCESS_READ 0 |
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#define PCI_ACCESS_WRITE 1 |
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/* define an unsigned array for the PCI registers */ |
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static unsigned int korina_cnfg_regs[25] = { |
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KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4, |
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KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8, |
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KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12, |
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KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16, |
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KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20, |
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KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24 |
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}; |
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static struct resource rc32434_res_pci_mem1; |
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static struct resource rc32434_res_pci_mem2; |
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static struct resource rc32434_res_pci_mem1 = { |
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.name = "PCI MEM1", |
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.start = 0x50000000, |
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.end = 0x5FFFFFFF, |
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.flags = IORESOURCE_MEM, |
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.sibling = NULL, |
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.child = &rc32434_res_pci_mem2 |
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}; |
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static struct resource rc32434_res_pci_mem2 = { |
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.name = "PCI Mem2", |
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.start = 0x60000000, |
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.end = 0x6FFFFFFF, |
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.flags = IORESOURCE_MEM, |
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.parent = &rc32434_res_pci_mem1, |
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.sibling = NULL, |
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.child = NULL |
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}; |
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static struct resource rc32434_res_pci_io1 = { |
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.name = "PCI I/O1", |
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.start = 0x18800000, |
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.end = 0x188FFFFF, |
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.flags = IORESOURCE_IO, |
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}; |
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extern struct pci_ops rc32434_pci_ops; |
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#define PCI_MEM1_START PCI_ADDR_START |
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#define PCI_MEM1_END (PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1) |
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#define PCI_MEM2_START (PCI_ADDR_START + CPUTOPCI_MEM_WIN) |
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#define PCI_MEM2_END (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) - 1) |
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#define PCI_IO1_START (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN)) |
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#define PCI_IO1_END \ |
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(PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN - 1) |
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#define PCI_IO2_START \ |
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(PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN) |
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#define PCI_IO2_END \ |
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(PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) - 1) |
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struct pci_controller rc32434_controller2; |
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struct pci_controller rc32434_controller = { |
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.pci_ops = &rc32434_pci_ops, |
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.mem_resource = &rc32434_res_pci_mem1, |
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.io_resource = &rc32434_res_pci_io1, |
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.mem_offset = 0, |
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.io_offset = 0, |
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}; |
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#ifdef __MIPSEB__ |
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#define PCI_ENDIAN_FLAG PCILBAC_sb_m |
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#else |
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#define PCI_ENDIAN_FLAG 0 |
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#endif |
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static int __init rc32434_pcibridge_init(void) |
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{ |
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unsigned int pcicvalue, pcicdata = 0; |
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unsigned int dummyread, pcicntlval; |
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int loopCount; |
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unsigned int pci_config_addr; |
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pcicvalue = rc32434_pci->pcic; |
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pcicvalue = (pcicvalue >> PCIM_SHFT) & PCIM_BIT_LEN; |
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if (!((pcicvalue == PCIM_H_EA) || |
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(pcicvalue == PCIM_H_IA_FIX) || |
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(pcicvalue == PCIM_H_IA_RR))) { |
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pr_err("PCI init error!!!\n"); |
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/* Not in Host Mode, return ERROR */ |
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return -1; |
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} |
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/* Enables the Idle Grant mode, Arbiter Parking */ |
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pcicdata |= (PCI_CTL_IGM | PCI_CTL_EAP | PCI_CTL_EN); |
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rc32434_pci->pcic = pcicdata; /* Enable the PCI bus Interface */ |
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/* Zero out the PCI status & PCI Status Mask */ |
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for (;;) { |
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pcicdata = rc32434_pci->pcis; |
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if (!(pcicdata & PCI_STAT_RIP)) |
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break; |
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} |
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rc32434_pci->pcis = 0; |
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rc32434_pci->pcism = 0xFFFFFFFF; |
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/* Zero out the PCI decoupled registers */ |
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rc32434_pci->pcidac = 0; /* |
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* disable PCI decoupled accesses at |
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* initialization |
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*/ |
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rc32434_pci->pcidas = 0; /* clear the status */ |
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rc32434_pci->pcidasm = 0x0000007F; /* Mask all the interrupts */ |
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/* Mask PCI Messaging Interrupts */ |
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rc32434_pci_msg->pciiic = 0; |
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rc32434_pci_msg->pciiim = 0xFFFFFFFF; |
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rc32434_pci_msg->pciioic = 0; |
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rc32434_pci_msg->pciioim = 0; |
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/* Setup PCILB0 as Memory Window */ |
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rc32434_pci->pcilba[0].address = (unsigned int) (PCI_ADDR_START); |
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/* setup the PCI map address as same as the local address */ |
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rc32434_pci->pcilba[0].mapping = (unsigned int) (PCI_ADDR_START); |
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/* Setup PCILBA1 as MEM */ |
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rc32434_pci->pcilba[0].control = |
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(((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG); |
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dummyread = rc32434_pci->pcilba[0].control; /* flush the CPU write Buffers */ |
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rc32434_pci->pcilba[1].address = 0x60000000; |
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rc32434_pci->pcilba[1].mapping = 0x60000000; |
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/* setup PCILBA2 as IO Window */ |
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rc32434_pci->pcilba[1].control = |
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(((SIZE_256MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG); |
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dummyread = rc32434_pci->pcilba[1].control; /* flush the CPU write Buffers */ |
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rc32434_pci->pcilba[2].address = 0x18C00000; |
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rc32434_pci->pcilba[2].mapping = 0x18FFFFFF; |
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/* setup PCILBA2 as IO Window */ |
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rc32434_pci->pcilba[2].control = |
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(((SIZE_4MB & 0x1f) << PCI_LBAC_SIZE_BIT) | PCI_ENDIAN_FLAG); |
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dummyread = rc32434_pci->pcilba[2].control; /* flush the CPU write Buffers */ |
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/* Setup PCILBA3 as IO Window */ |
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rc32434_pci->pcilba[3].address = 0x18800000; |
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rc32434_pci->pcilba[3].mapping = 0x18800000; |
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rc32434_pci->pcilba[3].control = |
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((((SIZE_1MB & 0x1ff) << PCI_LBAC_SIZE_BIT) | PCI_LBAC_MSI) | |
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PCI_ENDIAN_FLAG); |
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dummyread = rc32434_pci->pcilba[3].control; /* flush the CPU write Buffers */ |
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pci_config_addr = (unsigned int) (0x80000004); |
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for (loopCount = 0; loopCount < 24; loopCount++) { |
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rc32434_pci->pcicfga = pci_config_addr; |
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dummyread = rc32434_pci->pcicfga; |
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rc32434_pci->pcicfgd = korina_cnfg_regs[loopCount]; |
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dummyread = rc32434_pci->pcicfgd; |
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pci_config_addr += 4; |
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} |
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rc32434_pci->pcitc = |
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(unsigned int) ((PCITC_RTIMER_VAL & 0xff) << PCI_TC_RTIMER_BIT) | |
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((PCITC_DTIMER_VAL & 0xff) << PCI_TC_DTIMER_BIT); |
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pcicntlval = rc32434_pci->pcic; |
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pcicntlval &= ~PCI_CTL_TNR; |
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rc32434_pci->pcic = pcicntlval; |
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pcicntlval = rc32434_pci->pcic; |
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return 0; |
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} |
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static int __init rc32434_pci_init(void) |
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{ |
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void __iomem *io_map_base; |
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pr_info("PCI: Initializing PCI\n"); |
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ioport_resource.start = rc32434_res_pci_io1.start; |
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ioport_resource.end = rc32434_res_pci_io1.end; |
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rc32434_pcibridge_init(); |
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io_map_base = ioremap(rc32434_res_pci_io1.start, |
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resource_size(&rc32434_res_pci_io1)); |
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if (!io_map_base) |
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return -ENOMEM; |
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rc32434_controller.io_map_base = |
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(unsigned long)io_map_base - rc32434_res_pci_io1.start; |
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register_pci_controller(&rc32434_controller); |
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rc32434_sync(); |
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return 0; |
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} |
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arch_initcall(rc32434_pci_init);
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