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711 lines
22 KiB
711 lines
22 KiB
/* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 2005-2009 Cavium Networks |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/pci.h> |
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#include <linux/interrupt.h> |
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#include <linux/time.h> |
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#include <linux/delay.h> |
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#include <linux/platform_device.h> |
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#include <linux/swiotlb.h> |
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#include <asm/time.h> |
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#include <asm/octeon/octeon.h> |
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#include <asm/octeon/cvmx-npi-defs.h> |
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#include <asm/octeon/cvmx-pci-defs.h> |
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#include <asm/octeon/pci-octeon.h> |
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#define USE_OCTEON_INTERNAL_ARBITER |
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/* |
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* Octeon's PCI controller uses did=3, subdid=2 for PCI IO |
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* addresses. Use PCI endian swapping 1 so no address swapping is |
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* necessary. The Linux io routines will endian swap the data. |
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*/ |
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#define OCTEON_PCI_IOSPACE_BASE 0x80011a0400000000ull |
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#define OCTEON_PCI_IOSPACE_SIZE (1ull<<32) |
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/* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */ |
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#define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull) |
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u64 octeon_bar1_pci_phys; |
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/** |
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* This is the bit decoding used for the Octeon PCI controller addresses |
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*/ |
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union octeon_pci_address { |
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uint64_t u64; |
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struct { |
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uint64_t upper:2; |
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uint64_t reserved:13; |
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uint64_t io:1; |
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uint64_t did:5; |
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uint64_t subdid:3; |
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uint64_t reserved2:4; |
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uint64_t endian_swap:2; |
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uint64_t reserved3:10; |
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uint64_t bus:8; |
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uint64_t dev:5; |
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uint64_t func:3; |
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uint64_t reg:8; |
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} s; |
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}; |
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int (*octeon_pcibios_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin); |
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enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID; |
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/** |
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* Map a PCI device to the appropriate interrupt line |
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* |
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* @dev: The Linux PCI device structure for the device to map |
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* @slot: The slot number for this device on __BUS 0__. Linux |
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* enumerates through all the bridges and figures out the |
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* slot on Bus 0 where this device eventually hooks to. |
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* @pin: The PCI interrupt pin read from the device, then swizzled |
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* as it goes through each bridge. |
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* Returns Interrupt number for the device |
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*/ |
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int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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{ |
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if (octeon_pcibios_map_irq) |
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return octeon_pcibios_map_irq(dev, slot, pin); |
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else |
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panic("octeon_pcibios_map_irq not set."); |
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} |
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/* |
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* Called to perform platform specific PCI setup |
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*/ |
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int pcibios_plat_dev_init(struct pci_dev *dev) |
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{ |
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uint16_t config; |
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uint32_t dconfig; |
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int pos; |
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/* |
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* Force the Cache line setting to 64 bytes. The standard |
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* Linux bus scan doesn't seem to set it. Octeon really has |
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* 128 byte lines, but Intel bridges get really upset if you |
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* try and set values above 64 bytes. Value is specified in |
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* 32bit words. |
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*/ |
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4); |
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/* Set latency timers for all devices */ |
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64); |
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/* Enable reporting System errors and parity errors on all devices */ |
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/* Enable parity checking and error reporting */ |
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pci_read_config_word(dev, PCI_COMMAND, &config); |
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config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR; |
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pci_write_config_word(dev, PCI_COMMAND, config); |
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if (dev->subordinate) { |
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/* Set latency timers on sub bridges */ |
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pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 64); |
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/* More bridge error detection */ |
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pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config); |
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config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; |
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pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config); |
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} |
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/* Enable the PCIe normal error reporting */ |
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config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */ |
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config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */ |
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config |= PCI_EXP_DEVCTL_FERE; /* Fatal Error Reporting */ |
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config |= PCI_EXP_DEVCTL_URRE; /* Unsupported Request */ |
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pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config); |
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/* Find the Advanced Error Reporting capability */ |
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pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); |
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if (pos) { |
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/* Clear Uncorrectable Error Status */ |
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, |
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&dconfig); |
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pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, |
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dconfig); |
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/* Enable reporting of all uncorrectable errors */ |
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/* Uncorrectable Error Mask - turned on bits disable errors */ |
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pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0); |
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/* |
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* Leave severity at HW default. This only controls if |
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* errors are reported as uncorrectable or |
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* correctable, not if the error is reported. |
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*/ |
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/* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */ |
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/* Clear Correctable Error Status */ |
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pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig); |
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pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig); |
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/* Enable reporting of all correctable errors */ |
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/* Correctable Error Mask - turned on bits disable errors */ |
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pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0); |
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/* Advanced Error Capabilities */ |
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pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig); |
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/* ECRC Generation Enable */ |
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if (config & PCI_ERR_CAP_ECRC_GENC) |
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config |= PCI_ERR_CAP_ECRC_GENE; |
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/* ECRC Check Enable */ |
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if (config & PCI_ERR_CAP_ECRC_CHKC) |
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config |= PCI_ERR_CAP_ECRC_CHKE; |
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pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig); |
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/* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */ |
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/* Report all errors to the root complex */ |
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pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, |
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PCI_ERR_ROOT_CMD_COR_EN | |
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PCI_ERR_ROOT_CMD_NONFATAL_EN | |
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PCI_ERR_ROOT_CMD_FATAL_EN); |
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/* Clear the Root status register */ |
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pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig); |
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pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig); |
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} |
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return 0; |
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} |
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/** |
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* Return the mapping of PCI device number to IRQ line. Each |
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* character in the return string represents the interrupt |
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* line for the device at that position. Device 1 maps to the |
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* first character, etc. The characters A-D are used for PCI |
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* interrupts. |
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* |
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* Returns PCI interrupt mapping |
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*/ |
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const char *octeon_get_pci_interrupts(void) |
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{ |
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/* |
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* Returning an empty string causes the interrupts to be |
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* routed based on the PCI specification. From the PCI spec: |
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* |
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* INTA# of Device Number 0 is connected to IRQW on the system |
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* board. (Device Number has no significance regarding being |
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* located on the system board or in a connector.) INTA# of |
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* Device Number 1 is connected to IRQX on the system |
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* board. INTA# of Device Number 2 is connected to IRQY on the |
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* system board. INTA# of Device Number 3 is connected to IRQZ |
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* on the system board. The table below describes how each |
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* agent's INTx# lines are connected to the system board |
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* interrupt lines. The following equation can be used to |
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* determine to which INTx# signal on the system board a given |
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* device's INTx# line(s) is connected. |
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* |
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* MB = (D + I) MOD 4 MB = System board Interrupt (IRQW = 0, |
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* IRQX = 1, IRQY = 2, and IRQZ = 3) D = Device Number I = |
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* Interrupt Number (INTA# = 0, INTB# = 1, INTC# = 2, and |
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* INTD# = 3) |
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*/ |
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if (of_machine_is_compatible("dlink,dsr-500n")) |
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return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC"; |
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switch (octeon_bootinfo->board_type) { |
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case CVMX_BOARD_TYPE_NAO38: |
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/* This is really the NAC38 */ |
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return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA"; |
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case CVMX_BOARD_TYPE_EBH3100: |
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case CVMX_BOARD_TYPE_CN3010_EVB_HS5: |
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case CVMX_BOARD_TYPE_CN3005_EVB_HS5: |
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return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA"; |
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case CVMX_BOARD_TYPE_BBGW_REF: |
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return "AABCD"; |
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case CVMX_BOARD_TYPE_CUST_DSR1000N: |
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return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC"; |
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case CVMX_BOARD_TYPE_THUNDER: |
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case CVMX_BOARD_TYPE_EBH3000: |
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default: |
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return ""; |
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} |
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} |
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/** |
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* Map a PCI device to the appropriate interrupt line |
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* |
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* @dev: The Linux PCI device structure for the device to map |
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* @slot: The slot number for this device on __BUS 0__. Linux |
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* enumerates through all the bridges and figures out the |
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* slot on Bus 0 where this device eventually hooks to. |
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* @pin: The PCI interrupt pin read from the device, then swizzled |
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* as it goes through each bridge. |
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* Returns Interrupt number for the device |
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*/ |
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int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev, |
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u8 slot, u8 pin) |
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{ |
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int irq_num; |
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const char *interrupts; |
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int dev_num; |
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/* Get the board specific interrupt mapping */ |
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interrupts = octeon_get_pci_interrupts(); |
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dev_num = dev->devfn >> 3; |
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if (dev_num < strlen(interrupts)) |
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irq_num = ((interrupts[dev_num] - 'A' + pin - 1) & 3) + |
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OCTEON_IRQ_PCI_INT0; |
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else |
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irq_num = ((slot + pin - 3) & 3) + OCTEON_IRQ_PCI_INT0; |
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return irq_num; |
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} |
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/* |
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* Read a value from configuration space |
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*/ |
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static int octeon_read_config(struct pci_bus *bus, unsigned int devfn, |
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int reg, int size, u32 *val) |
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{ |
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union octeon_pci_address pci_addr; |
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pci_addr.u64 = 0; |
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pci_addr.s.upper = 2; |
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pci_addr.s.io = 1; |
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pci_addr.s.did = 3; |
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pci_addr.s.subdid = 1; |
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pci_addr.s.endian_swap = 1; |
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pci_addr.s.bus = bus->number; |
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pci_addr.s.dev = devfn >> 3; |
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pci_addr.s.func = devfn & 0x7; |
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pci_addr.s.reg = reg; |
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switch (size) { |
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case 4: |
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*val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64)); |
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return PCIBIOS_SUCCESSFUL; |
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case 2: |
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*val = le16_to_cpu(cvmx_read64_uint16(pci_addr.u64)); |
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return PCIBIOS_SUCCESSFUL; |
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case 1: |
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*val = cvmx_read64_uint8(pci_addr.u64); |
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return PCIBIOS_SUCCESSFUL; |
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} |
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return PCIBIOS_FUNC_NOT_SUPPORTED; |
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} |
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/* |
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* Write a value to PCI configuration space |
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*/ |
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static int octeon_write_config(struct pci_bus *bus, unsigned int devfn, |
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int reg, int size, u32 val) |
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{ |
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union octeon_pci_address pci_addr; |
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pci_addr.u64 = 0; |
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pci_addr.s.upper = 2; |
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pci_addr.s.io = 1; |
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pci_addr.s.did = 3; |
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pci_addr.s.subdid = 1; |
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pci_addr.s.endian_swap = 1; |
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pci_addr.s.bus = bus->number; |
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pci_addr.s.dev = devfn >> 3; |
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pci_addr.s.func = devfn & 0x7; |
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pci_addr.s.reg = reg; |
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switch (size) { |
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case 4: |
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cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val)); |
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return PCIBIOS_SUCCESSFUL; |
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case 2: |
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cvmx_write64_uint16(pci_addr.u64, cpu_to_le16(val)); |
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return PCIBIOS_SUCCESSFUL; |
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case 1: |
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cvmx_write64_uint8(pci_addr.u64, val); |
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return PCIBIOS_SUCCESSFUL; |
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} |
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return PCIBIOS_FUNC_NOT_SUPPORTED; |
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} |
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static struct pci_ops octeon_pci_ops = { |
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.read = octeon_read_config, |
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.write = octeon_write_config, |
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}; |
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static struct resource octeon_pci_mem_resource = { |
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.start = 0, |
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.end = 0, |
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.name = "Octeon PCI MEM", |
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.flags = IORESOURCE_MEM, |
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}; |
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/* |
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* PCI ports must be above 16KB so the ISA bus filtering in the PCI-X to PCI |
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* bridge |
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*/ |
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static struct resource octeon_pci_io_resource = { |
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.start = 0x4000, |
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.end = OCTEON_PCI_IOSPACE_SIZE - 1, |
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.name = "Octeon PCI IO", |
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.flags = IORESOURCE_IO, |
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}; |
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static struct pci_controller octeon_pci_controller = { |
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.pci_ops = &octeon_pci_ops, |
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.mem_resource = &octeon_pci_mem_resource, |
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.mem_offset = OCTEON_PCI_MEMSPACE_OFFSET, |
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.io_resource = &octeon_pci_io_resource, |
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.io_offset = 0, |
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.io_map_base = OCTEON_PCI_IOSPACE_BASE, |
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}; |
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/* |
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* Low level initialize the Octeon PCI controller |
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*/ |
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static void octeon_pci_initialize(void) |
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{ |
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union cvmx_pci_cfg01 cfg01; |
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union cvmx_npi_ctl_status ctl_status; |
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union cvmx_pci_ctl_status_2 ctl_status_2; |
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union cvmx_pci_cfg19 cfg19; |
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union cvmx_pci_cfg16 cfg16; |
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union cvmx_pci_cfg22 cfg22; |
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union cvmx_pci_cfg56 cfg56; |
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/* Reset the PCI Bus */ |
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cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1); |
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cvmx_read_csr(CVMX_CIU_SOFT_PRST); |
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udelay(2000); /* Hold PCI reset for 2 ms */ |
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ctl_status.u64 = 0; /* cvmx_read_csr(CVMX_NPI_CTL_STATUS); */ |
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ctl_status.s.max_word = 1; |
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ctl_status.s.timer = 1; |
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cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64); |
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/* Deassert PCI reset and advertize PCX Host Mode Device Capability |
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(64b) */ |
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cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4); |
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cvmx_read_csr(CVMX_CIU_SOFT_PRST); |
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udelay(2000); /* Wait 2 ms after deasserting PCI reset */ |
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ctl_status_2.u32 = 0; |
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ctl_status_2.s.tsr_hwm = 1; /* Initializes to 0. Must be set |
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before any PCI reads. */ |
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ctl_status_2.s.bar2pres = 1; /* Enable BAR2 */ |
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ctl_status_2.s.bar2_enb = 1; |
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ctl_status_2.s.bar2_cax = 1; /* Don't use L2 */ |
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ctl_status_2.s.bar2_esx = 1; |
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ctl_status_2.s.pmo_amod = 1; /* Round robin priority */ |
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if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) { |
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/* BAR1 hole */ |
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ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS; |
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ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */ |
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ctl_status_2.s.bb_ca = 1; /* Don't use L2 with big bars */ |
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ctl_status_2.s.bb_es = 1; /* Big bar in byte swap mode */ |
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ctl_status_2.s.bb1 = 1; /* BAR1 is big */ |
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ctl_status_2.s.bb0 = 1; /* BAR0 is big */ |
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} |
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octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32); |
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udelay(2000); /* Wait 2 ms before doing PCI reads */ |
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ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2); |
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pr_notice("PCI Status: %s %s-bit\n", |
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ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI", |
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ctl_status_2.s.ap_64ad ? "64" : "32"); |
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if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) { |
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union cvmx_pci_cnt_reg cnt_reg_start; |
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union cvmx_pci_cnt_reg cnt_reg_end; |
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unsigned long cycles, pci_clock; |
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cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG); |
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cycles = read_c0_cvmcount(); |
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udelay(1000); |
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cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG); |
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cycles = read_c0_cvmcount() - cycles; |
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pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) / |
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(cycles / (mips_hpt_frequency / 1000000)); |
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pr_notice("PCI Clock: %lu MHz\n", pci_clock); |
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} |
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/* |
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* TDOMC must be set to one in PCI mode. TDOMC should be set to 4 |
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* in PCI-X mode to allow four outstanding splits. Otherwise, |
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* should not change from its reset value. Don't write PCI_CFG19 |
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* in PCI mode (0x82000001 reset value), write it to 0x82000004 |
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* after PCI-X mode is known. MRBCI,MDWE,MDRE -> must be zero. |
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* MRBCM -> must be one. |
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*/ |
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if (ctl_status_2.s.ap_pcix) { |
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cfg19.u32 = 0; |
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/* |
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* Target Delayed/Split request outstanding maximum |
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* count. [1..31] and 0=32. NOTE: If the user |
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* programs these bits beyond the Designed Maximum |
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* outstanding count, then the designed maximum table |
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* depth will be used instead. No additional |
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* Deferred/Split transactions will be accepted if |
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* this outstanding maximum count is |
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* reached. Furthermore, no additional deferred/split |
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* transactions will be accepted if the I/O delay/ I/O |
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* Split Request outstanding maximum is reached. |
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*/ |
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cfg19.s.tdomc = 4; |
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/* |
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* Master Deferred Read Request Outstanding Max Count |
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* (PCI only). CR4C[26:24] Max SAC cycles MAX DAC |
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* cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101 |
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* 5 2 110 6 3 111 7 3 For example, if these bits are |
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* programmed to 100, the core can support 2 DAC |
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* cycles, 4 SAC cycles or a combination of 1 DAC and |
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* 2 SAC cycles. NOTE: For the PCI-X maximum |
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* outstanding split transactions, refer to |
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* CRE0[22:20]. |
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*/ |
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cfg19.s.mdrrmc = 2; |
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/* |
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* Master Request (Memory Read) Byte Count/Byte Enable |
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* select. 0 = Byte Enables valid. In PCI mode, a |
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* burst transaction cannot be performed using Memory |
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* Read command=4?h6. 1 = DWORD Byte Count valid |
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* (default). In PCI Mode, the memory read byte |
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* enables are automatically generated by the |
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* core. Note: N3 Master Request transaction sizes are |
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* always determined through the |
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* am_attr[<35:32>|<7:0>] field. |
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*/ |
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cfg19.s.mrbcm = 1; |
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octeon_npi_write32(CVMX_NPI_PCI_CFG19, cfg19.u32); |
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} |
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cfg01.u32 = 0; |
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cfg01.s.msae = 1; /* Memory Space Access Enable */ |
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cfg01.s.me = 1; /* Master Enable */ |
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cfg01.s.pee = 1; /* PERR# Enable */ |
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cfg01.s.see = 1; /* System Error Enable */ |
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cfg01.s.fbbe = 1; /* Fast Back to Back Transaction Enable */ |
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|
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octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32); |
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|
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#ifdef USE_OCTEON_INTERNAL_ARBITER |
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/* |
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* When OCTEON is a PCI host, most systems will use OCTEON's |
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* internal arbiter, so must enable it before any PCI/PCI-X |
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* traffic can occur. |
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*/ |
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{ |
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union cvmx_npi_pci_int_arb_cfg pci_int_arb_cfg; |
|
|
|
pci_int_arb_cfg.u64 = 0; |
|
pci_int_arb_cfg.s.en = 1; /* Internal arbiter enable */ |
|
cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64); |
|
} |
|
#endif /* USE_OCTEON_INTERNAL_ARBITER */ |
|
|
|
/* |
|
* Preferably written to 1 to set MLTD. [RDSATI,TRTAE, |
|
* TWTAE,TMAE,DPPMR -> must be zero. TILT -> must not be set to |
|
* 1..7. |
|
*/ |
|
cfg16.u32 = 0; |
|
cfg16.s.mltd = 1; /* Master Latency Timer Disable */ |
|
octeon_npi_write32(CVMX_NPI_PCI_CFG16, cfg16.u32); |
|
|
|
/* |
|
* Should be written to 0x4ff00. MTTV -> must be zero. |
|
* FLUSH -> must be 1. MRV -> should be 0xFF. |
|
*/ |
|
cfg22.u32 = 0; |
|
/* Master Retry Value [1..255] and 0=infinite */ |
|
cfg22.s.mrv = 0xff; |
|
/* |
|
* AM_DO_FLUSH_I control NOTE: This bit MUST BE ONE for proper |
|
* N3K operation. |
|
*/ |
|
cfg22.s.flush = 1; |
|
octeon_npi_write32(CVMX_NPI_PCI_CFG22, cfg22.u32); |
|
|
|
/* |
|
* MOST Indicates the maximum number of outstanding splits (in -1 |
|
* notation) when OCTEON is in PCI-X mode. PCI-X performance is |
|
* affected by the MOST selection. Should generally be written |
|
* with one of 0x3be807, 0x2be807, 0x1be807, or 0x0be807, |
|
* depending on the desired MOST of 3, 2, 1, or 0, respectively. |
|
*/ |
|
cfg56.u32 = 0; |
|
cfg56.s.pxcid = 7; /* RO - PCI-X Capability ID */ |
|
cfg56.s.ncp = 0xe8; /* RO - Next Capability Pointer */ |
|
cfg56.s.dpere = 1; /* Data Parity Error Recovery Enable */ |
|
cfg56.s.roe = 1; /* Relaxed Ordering Enable */ |
|
cfg56.s.mmbc = 1; /* Maximum Memory Byte Count |
|
[0=512B,1=1024B,2=2048B,3=4096B] */ |
|
cfg56.s.most = 3; /* Maximum outstanding Split transactions [0=1 |
|
.. 7=32] */ |
|
|
|
octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32); |
|
|
|
/* |
|
* Affects PCI performance when OCTEON services reads to its |
|
* BAR1/BAR2. Refer to Section 10.6.1. The recommended values are |
|
* 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and |
|
* PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700, |
|
* these values need to be changed so they won't possibly prefetch off |
|
* of the end of memory if PCI is DMAing a buffer at the end of |
|
* memory. Note that these values differ from their reset values. |
|
*/ |
|
octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_6, 0x21); |
|
octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_C, 0x31); |
|
octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_E, 0x31); |
|
} |
|
|
|
|
|
/* |
|
* Initialize the Octeon PCI controller |
|
*/ |
|
static int __init octeon_pci_setup(void) |
|
{ |
|
union cvmx_npi_mem_access_subidx mem_access; |
|
int index; |
|
|
|
/* Only these chips have PCI */ |
|
if (octeon_has_feature(OCTEON_FEATURE_PCIE)) |
|
return 0; |
|
|
|
if (!octeon_is_pci_host()) { |
|
pr_notice("Not in host mode, PCI Controller not initialized\n"); |
|
return 0; |
|
} |
|
|
|
/* Point pcibios_map_irq() to the PCI version of it */ |
|
octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq; |
|
|
|
/* Only use the big bars on chips that support it */ |
|
if (OCTEON_IS_MODEL(OCTEON_CN31XX) || |
|
OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || |
|
OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1)) |
|
octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_SMALL; |
|
else |
|
octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG; |
|
|
|
/* PCI I/O and PCI MEM values */ |
|
set_io_port_base(OCTEON_PCI_IOSPACE_BASE); |
|
ioport_resource.start = 0; |
|
ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1; |
|
|
|
pr_notice("%s Octeon big bar support\n", |
|
(octeon_dma_bar_type == |
|
OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling"); |
|
|
|
octeon_pci_initialize(); |
|
|
|
mem_access.u64 = 0; |
|
mem_access.s.esr = 1; /* Endian-Swap on read. */ |
|
mem_access.s.esw = 1; /* Endian-Swap on write. */ |
|
mem_access.s.nsr = 0; /* No-Snoop on read. */ |
|
mem_access.s.nsw = 0; /* No-Snoop on write. */ |
|
mem_access.s.ror = 0; /* Relax Read on read. */ |
|
mem_access.s.row = 0; /* Relax Order on write. */ |
|
mem_access.s.ba = 0; /* PCI Address bits [63:36]. */ |
|
cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64); |
|
|
|
/* |
|
* Remap the Octeon BAR 2 above all 32 bit devices |
|
* (0x8000000000ul). This is done here so it is remapped |
|
* before the readl()'s below. We don't want BAR2 overlapping |
|
* with BAR0/BAR1 during these reads. |
|
*/ |
|
octeon_npi_write32(CVMX_NPI_PCI_CFG08, |
|
(u32)(OCTEON_BAR2_PCI_ADDRESS & 0xffffffffull)); |
|
octeon_npi_write32(CVMX_NPI_PCI_CFG09, |
|
(u32)(OCTEON_BAR2_PCI_ADDRESS >> 32)); |
|
|
|
if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) { |
|
/* Remap the Octeon BAR 0 to 0-2GB */ |
|
octeon_npi_write32(CVMX_NPI_PCI_CFG04, 0); |
|
octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0); |
|
|
|
/* |
|
* Remap the Octeon BAR 1 to map 2GB-4GB (minus the |
|
* BAR 1 hole). |
|
*/ |
|
octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30); |
|
octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0); |
|
|
|
/* BAR1 movable mappings set for identity mapping */ |
|
octeon_bar1_pci_phys = 0x80000000ull; |
|
for (index = 0; index < 32; index++) { |
|
union cvmx_pci_bar1_indexx bar1_index; |
|
|
|
bar1_index.u32 = 0; |
|
/* Address bits[35:22] sent to L2C */ |
|
bar1_index.s.addr_idx = |
|
(octeon_bar1_pci_phys >> 22) + index; |
|
/* Don't put PCI accesses in L2. */ |
|
bar1_index.s.ca = 1; |
|
/* Endian Swap Mode */ |
|
bar1_index.s.end_swp = 1; |
|
/* Set '1' when the selected address range is valid. */ |
|
bar1_index.s.addr_v = 1; |
|
octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), |
|
bar1_index.u32); |
|
} |
|
|
|
/* Devices go after BAR1 */ |
|
octeon_pci_mem_resource.start = |
|
OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) - |
|
(OCTEON_PCI_BAR1_HOLE_SIZE << 20); |
|
octeon_pci_mem_resource.end = |
|
octeon_pci_mem_resource.start + (1ul << 30); |
|
} else { |
|
/* Remap the Octeon BAR 0 to map 128MB-(128MB+4KB) */ |
|
octeon_npi_write32(CVMX_NPI_PCI_CFG04, 128ul << 20); |
|
octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0); |
|
|
|
/* Remap the Octeon BAR 1 to map 0-128MB */ |
|
octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0); |
|
octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0); |
|
|
|
/* BAR1 movable regions contiguous to cover the swiotlb */ |
|
octeon_bar1_pci_phys = |
|
virt_to_phys(octeon_swiotlb) & ~((1ull << 22) - 1); |
|
|
|
for (index = 0; index < 32; index++) { |
|
union cvmx_pci_bar1_indexx bar1_index; |
|
|
|
bar1_index.u32 = 0; |
|
/* Address bits[35:22] sent to L2C */ |
|
bar1_index.s.addr_idx = |
|
(octeon_bar1_pci_phys >> 22) + index; |
|
/* Don't put PCI accesses in L2. */ |
|
bar1_index.s.ca = 1; |
|
/* Endian Swap Mode */ |
|
bar1_index.s.end_swp = 1; |
|
/* Set '1' when the selected address range is valid. */ |
|
bar1_index.s.addr_v = 1; |
|
octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), |
|
bar1_index.u32); |
|
} |
|
|
|
/* Devices go after BAR0 */ |
|
octeon_pci_mem_resource.start = |
|
OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) + |
|
(4ul << 10); |
|
octeon_pci_mem_resource.end = |
|
octeon_pci_mem_resource.start + (1ul << 30); |
|
} |
|
|
|
register_pci_controller(&octeon_pci_controller); |
|
|
|
/* |
|
* Clear any errors that might be pending from before the bus |
|
* was setup properly. |
|
*/ |
|
cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1); |
|
|
|
if (IS_ERR(platform_device_register_simple("octeon_pci_edac", |
|
-1, NULL, 0))) |
|
pr_err("Registration of co_pci_edac failed!\n"); |
|
|
|
octeon_pci_dma_init(); |
|
|
|
return 0; |
|
} |
|
|
|
arch_initcall(octeon_pci_setup);
|
|
|