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351 lines
9.7 KiB
351 lines
9.7 KiB
/* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 2008 Maxime Bizon <[email protected]> |
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*/ |
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#include <linux/types.h> |
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#include <linux/pci.h> |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/delay.h> |
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#include <linux/clk.h> |
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#include <asm/bootinfo.h> |
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#include <bcm63xx_reset.h> |
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#include "pci-bcm63xx.h" |
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/* |
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* Allow PCI to be disabled at runtime depending on board nvram |
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* configuration |
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*/ |
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int bcm63xx_pci_enabled; |
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static struct resource bcm_pci_mem_resource = { |
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.name = "bcm63xx PCI memory space", |
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.start = BCM_PCI_MEM_BASE_PA, |
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.end = BCM_PCI_MEM_END_PA, |
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.flags = IORESOURCE_MEM |
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}; |
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static struct resource bcm_pci_io_resource = { |
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.name = "bcm63xx PCI IO space", |
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.start = BCM_PCI_IO_BASE_PA, |
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#ifdef CONFIG_CARDBUS |
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.end = BCM_PCI_IO_HALF_PA, |
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#else |
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.end = BCM_PCI_IO_END_PA, |
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#endif |
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.flags = IORESOURCE_IO |
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}; |
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struct pci_controller bcm63xx_controller = { |
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.pci_ops = &bcm63xx_pci_ops, |
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.io_resource = &bcm_pci_io_resource, |
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.mem_resource = &bcm_pci_mem_resource, |
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}; |
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/* |
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* We handle cardbus via a fake Cardbus bridge, memory and io spaces |
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* have to be clearly separated from PCI one since we have different |
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* memory decoder. |
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*/ |
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#ifdef CONFIG_CARDBUS |
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static struct resource bcm_cb_mem_resource = { |
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.name = "bcm63xx Cardbus memory space", |
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.start = BCM_CB_MEM_BASE_PA, |
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.end = BCM_CB_MEM_END_PA, |
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.flags = IORESOURCE_MEM |
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}; |
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static struct resource bcm_cb_io_resource = { |
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.name = "bcm63xx Cardbus IO space", |
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.start = BCM_PCI_IO_HALF_PA + 1, |
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.end = BCM_PCI_IO_END_PA, |
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.flags = IORESOURCE_IO |
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}; |
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struct pci_controller bcm63xx_cb_controller = { |
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.pci_ops = &bcm63xx_cb_ops, |
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.io_resource = &bcm_cb_io_resource, |
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.mem_resource = &bcm_cb_mem_resource, |
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}; |
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#endif |
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static struct resource bcm_pcie_mem_resource = { |
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.name = "bcm63xx PCIe memory space", |
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.start = BCM_PCIE_MEM_BASE_PA, |
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.end = BCM_PCIE_MEM_END_PA, |
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.flags = IORESOURCE_MEM, |
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}; |
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static struct resource bcm_pcie_io_resource = { |
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.name = "bcm63xx PCIe IO space", |
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.start = 0, |
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.end = 0, |
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.flags = 0, |
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}; |
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struct pci_controller bcm63xx_pcie_controller = { |
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.pci_ops = &bcm63xx_pcie_ops, |
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.io_resource = &bcm_pcie_io_resource, |
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.mem_resource = &bcm_pcie_mem_resource, |
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}; |
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static u32 bcm63xx_int_cfg_readl(u32 reg) |
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{ |
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u32 tmp; |
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tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK; |
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tmp |= MPI_PCICFGCTL_WRITEEN_MASK; |
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bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG); |
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iob(); |
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return bcm_mpi_readl(MPI_PCICFGDATA_REG); |
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} |
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static void bcm63xx_int_cfg_writel(u32 val, u32 reg) |
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{ |
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u32 tmp; |
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tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK; |
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tmp |= MPI_PCICFGCTL_WRITEEN_MASK; |
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bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG); |
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bcm_mpi_writel(val, MPI_PCICFGDATA_REG); |
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} |
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void __iomem *pci_iospace_start; |
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static void __init bcm63xx_reset_pcie(void) |
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{ |
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u32 val; |
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u32 reg; |
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/* enable SERDES */ |
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if (BCMCPU_IS_6328()) |
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reg = MISC_SERDES_CTRL_6328_REG; |
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else |
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reg = MISC_SERDES_CTRL_6362_REG; |
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val = bcm_misc_readl(reg); |
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val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN; |
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bcm_misc_writel(val, reg); |
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/* reset the PCIe core */ |
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bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1); |
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bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1); |
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mdelay(10); |
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bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0); |
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mdelay(10); |
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bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 0); |
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mdelay(200); |
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} |
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static struct clk *pcie_clk; |
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static int __init bcm63xx_register_pcie(void) |
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{ |
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u32 val; |
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/* enable clock */ |
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pcie_clk = clk_get(NULL, "pcie"); |
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if (IS_ERR_OR_NULL(pcie_clk)) |
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return -ENODEV; |
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clk_prepare_enable(pcie_clk); |
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bcm63xx_reset_pcie(); |
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/* configure the PCIe bridge */ |
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val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG); |
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val |= OPT1_RD_BE_OPT_EN; |
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val |= OPT1_RD_REPLY_BE_FIX_EN; |
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val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN; |
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val |= OPT1_L1_INT_STATUS_MASK_POL; |
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bcm_pcie_writel(val, PCIE_BRIDGE_OPT1_REG); |
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/* setup the interrupts */ |
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val = bcm_pcie_readl(PCIE_BRIDGE_RC_INT_MASK_REG); |
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val |= PCIE_RC_INT_A | PCIE_RC_INT_B | PCIE_RC_INT_C | PCIE_RC_INT_D; |
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bcm_pcie_writel(val, PCIE_BRIDGE_RC_INT_MASK_REG); |
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val = bcm_pcie_readl(PCIE_BRIDGE_OPT2_REG); |
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/* enable credit checking and error checking */ |
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val |= OPT2_TX_CREDIT_CHK_EN; |
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val |= OPT2_UBUS_UR_DECODE_DIS; |
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/* set device bus/func for the pcie device */ |
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val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT); |
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val |= OPT2_CFG_TYPE1_BD_SEL; |
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bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG); |
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/* setup class code as bridge */ |
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val = bcm_pcie_readl(PCIE_IDVAL3_REG); |
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val &= ~IDVAL3_CLASS_CODE_MASK; |
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val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT); |
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bcm_pcie_writel(val, PCIE_IDVAL3_REG); |
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/* disable bar1 size */ |
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val = bcm_pcie_readl(PCIE_CONFIG2_REG); |
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val &= ~CONFIG2_BAR1_SIZE_MASK; |
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bcm_pcie_writel(val, PCIE_CONFIG2_REG); |
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/* set bar0 to little endian */ |
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val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT; |
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val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT; |
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val |= BASEMASK_REMAP_EN; |
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bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG); |
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val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT; |
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bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG); |
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register_pci_controller(&bcm63xx_pcie_controller); |
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return 0; |
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} |
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static int __init bcm63xx_register_pci(void) |
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{ |
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unsigned int mem_size; |
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u32 val; |
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/* |
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* configuration access are done through IO space, remap 4 |
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* first bytes to access it from CPU. |
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* |
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* this means that no io access from CPU should happen while |
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* we do a configuration cycle, but there's no way we can add |
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* a spinlock for each io access, so this is currently kind of |
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* broken on SMP. |
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*/ |
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pci_iospace_start = ioremap(BCM_PCI_IO_BASE_PA, 4); |
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if (!pci_iospace_start) |
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return -ENOMEM; |
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/* setup local bus to PCI access (PCI memory) */ |
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val = BCM_PCI_MEM_BASE_PA & MPI_L2P_BASE_MASK; |
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bcm_mpi_writel(val, MPI_L2PMEMBASE1_REG); |
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bcm_mpi_writel(~(BCM_PCI_MEM_SIZE - 1), MPI_L2PMEMRANGE1_REG); |
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bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PMEMREMAP1_REG); |
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/* set Cardbus IDSEL (type 0 cfg access on primary bus for |
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* this IDSEL will be done on Cardbus instead) */ |
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val = bcm_pcmcia_readl(PCMCIA_C1_REG); |
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val &= ~PCMCIA_C1_CBIDSEL_MASK; |
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val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT); |
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bcm_pcmcia_writel(val, PCMCIA_C1_REG); |
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#ifdef CONFIG_CARDBUS |
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/* setup local bus to PCI access (Cardbus memory) */ |
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val = BCM_CB_MEM_BASE_PA & MPI_L2P_BASE_MASK; |
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bcm_mpi_writel(val, MPI_L2PMEMBASE2_REG); |
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bcm_mpi_writel(~(BCM_CB_MEM_SIZE - 1), MPI_L2PMEMRANGE2_REG); |
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val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK; |
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bcm_mpi_writel(val, MPI_L2PMEMREMAP2_REG); |
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#else |
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/* disable second access windows */ |
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bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG); |
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#endif |
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/* setup local bus to PCI access (IO memory), we have only 1 |
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* IO window for both PCI and cardbus, but it cannot handle |
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* both at the same time, assume standard PCI for now, if |
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* cardbus card has IO zone, PCI fixup will change window to |
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* cardbus */ |
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val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK; |
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bcm_mpi_writel(val, MPI_L2PIOBASE_REG); |
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bcm_mpi_writel(~(BCM_PCI_IO_SIZE - 1), MPI_L2PIORANGE_REG); |
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bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PIOREMAP_REG); |
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/* enable PCI related GPIO pins */ |
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bcm_mpi_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK, MPI_LOCBUSCTL_REG); |
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/* setup PCI to local bus access, used by PCI device to target |
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* local RAM while bus mastering */ |
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bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3); |
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if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) |
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val = MPI_SP0_REMAP_ENABLE_MASK; |
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else |
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val = 0; |
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bcm_mpi_writel(val, MPI_SP0_REMAP_REG); |
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bcm63xx_int_cfg_writel(0x0, PCI_BASE_ADDRESS_4); |
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bcm_mpi_writel(0, MPI_SP1_REMAP_REG); |
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mem_size = bcm63xx_get_memory_size(); |
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/* 6348 before rev b0 exposes only 16 MB of RAM memory through |
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* PCI, throw a warning if we have more memory */ |
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if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() & 0xf0) == 0xa0) { |
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if (mem_size > (16 * 1024 * 1024)) |
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printk(KERN_WARNING "bcm63xx: this CPU " |
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"revision cannot handle more than 16MB " |
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"of RAM for PCI bus mastering\n"); |
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} else { |
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/* setup sp0 range to local RAM size */ |
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bcm_mpi_writel(~(mem_size - 1), MPI_SP0_RANGE_REG); |
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bcm_mpi_writel(0, MPI_SP1_RANGE_REG); |
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} |
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/* change host bridge retry counter to infinite number of |
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* retry, needed for some broadcom wifi cards with Silicon |
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* Backplane bus where access to srom seems very slow */ |
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val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS); |
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val &= ~REG_TIMER_RETRY_MASK; |
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bcm63xx_int_cfg_writel(val, BCMPCI_REG_TIMERS); |
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/* enable memory decoder and bus mastering */ |
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val = bcm63xx_int_cfg_readl(PCI_COMMAND); |
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val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
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bcm63xx_int_cfg_writel(val, PCI_COMMAND); |
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/* enable read prefetching & disable byte swapping for bus |
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* mastering transfers */ |
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val = bcm_mpi_readl(MPI_PCIMODESEL_REG); |
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val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK; |
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val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK; |
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val &= ~MPI_PCIMODESEL_PREFETCH_MASK; |
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val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT); |
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bcm_mpi_writel(val, MPI_PCIMODESEL_REG); |
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/* enable pci interrupt */ |
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val = bcm_mpi_readl(MPI_LOCINT_REG); |
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val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT); |
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bcm_mpi_writel(val, MPI_LOCINT_REG); |
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register_pci_controller(&bcm63xx_controller); |
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#ifdef CONFIG_CARDBUS |
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register_pci_controller(&bcm63xx_cb_controller); |
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#endif |
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/* mark memory space used for IO mapping as reserved */ |
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request_mem_region(BCM_PCI_IO_BASE_PA, BCM_PCI_IO_SIZE, |
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"bcm63xx PCI IO space"); |
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return 0; |
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} |
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static int __init bcm63xx_pci_init(void) |
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{ |
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if (!bcm63xx_pci_enabled) |
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return -ENODEV; |
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switch (bcm63xx_get_cpu_id()) { |
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case BCM6328_CPU_ID: |
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case BCM6362_CPU_ID: |
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return bcm63xx_register_pcie(); |
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case BCM3368_CPU_ID: |
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case BCM6348_CPU_ID: |
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case BCM6358_CPU_ID: |
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case BCM6368_CPU_ID: |
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return bcm63xx_register_pci(); |
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default: |
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return -ENODEV; |
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} |
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} |
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arch_initcall(bcm63xx_pci_init);
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