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333 lines
8.8 KiB
333 lines
8.8 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2015 Imagination Technologies |
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* Author: Paul Burton <[email protected]> |
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*/ |
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#include <linux/bug.h> |
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#include <linux/kernel.h> |
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#include <linux/libfdt.h> |
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#include <linux/of_fdt.h> |
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#include <linux/sizes.h> |
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#include <asm/addrspace.h> |
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#include <asm/bootinfo.h> |
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#include <asm/fw/fw.h> |
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#include <asm/mips-boards/generic.h> |
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#include <asm/mips-boards/malta.h> |
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#include <asm/mips-cps.h> |
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#include <asm/page.h> |
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#define ROCIT_REG_BASE 0x1f403000 |
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#define ROCIT_CONFIG_GEN1 (ROCIT_REG_BASE + 0x04) |
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#define ROCIT_CONFIG_GEN1_MEMMAP_SHIFT 8 |
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#define ROCIT_CONFIG_GEN1_MEMMAP_MASK (0xf << 8) |
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static unsigned char fdt_buf[16 << 10] __initdata; |
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/* determined physical memory size, not overridden by command line args */ |
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extern unsigned long physical_memsize; |
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enum mem_map { |
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MEM_MAP_V1 = 0, |
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MEM_MAP_V2, |
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}; |
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#define MAX_MEM_ARRAY_ENTRIES 2 |
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static __init int malta_scon(void) |
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{ |
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int scon = MIPS_REVISION_SCONID; |
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if (scon != MIPS_REVISION_SCON_OTHER) |
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return scon; |
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switch (MIPS_REVISION_CORID) { |
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case MIPS_REVISION_CORID_QED_RM5261: |
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case MIPS_REVISION_CORID_CORE_LV: |
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case MIPS_REVISION_CORID_CORE_FPGA: |
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case MIPS_REVISION_CORID_CORE_FPGAR2: |
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return MIPS_REVISION_SCON_GT64120; |
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case MIPS_REVISION_CORID_CORE_EMUL_BON: |
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case MIPS_REVISION_CORID_BONITO64: |
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case MIPS_REVISION_CORID_CORE_20K: |
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return MIPS_REVISION_SCON_BONITO; |
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case MIPS_REVISION_CORID_CORE_MSC: |
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case MIPS_REVISION_CORID_CORE_FPGA2: |
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case MIPS_REVISION_CORID_CORE_24K: |
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return MIPS_REVISION_SCON_SOCIT; |
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case MIPS_REVISION_CORID_CORE_FPGA3: |
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case MIPS_REVISION_CORID_CORE_FPGA4: |
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case MIPS_REVISION_CORID_CORE_FPGA5: |
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case MIPS_REVISION_CORID_CORE_EMUL_MSC: |
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default: |
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return MIPS_REVISION_SCON_ROCIT; |
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} |
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} |
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static unsigned __init gen_fdt_mem_array(__be32 *mem_array, unsigned long size, |
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enum mem_map map) |
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{ |
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unsigned long size_preio; |
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unsigned entries; |
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entries = 1; |
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mem_array[0] = cpu_to_be32(PHYS_OFFSET); |
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if (IS_ENABLED(CONFIG_EVA)) { |
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/* |
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* The current Malta EVA configuration is "special" in that it |
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* always makes use of addresses in the upper half of the 32 bit |
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* physical address map, which gives it a contiguous region of |
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* DDR but limits it to 2GB. |
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*/ |
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mem_array[1] = cpu_to_be32(size); |
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goto done; |
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} |
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size_preio = min_t(unsigned long, size, SZ_256M); |
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mem_array[1] = cpu_to_be32(size_preio); |
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size -= size_preio; |
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if (!size) |
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goto done; |
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if (map == MEM_MAP_V2) { |
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/* |
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* We have a flat 32 bit physical memory map with DDR filling |
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* all 4GB of the memory map, apart from the I/O region which |
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* obscures 256MB from 0x10000000-0x1fffffff. |
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* |
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* Therefore we discard the 256MB behind the I/O region. |
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*/ |
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if (size <= SZ_256M) |
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goto done; |
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size -= SZ_256M; |
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/* Make use of the memory following the I/O region */ |
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entries++; |
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mem_array[2] = cpu_to_be32(PHYS_OFFSET + SZ_512M); |
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mem_array[3] = cpu_to_be32(size); |
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} else { |
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/* |
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* We have a 32 bit physical memory map with a 2GB DDR region |
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* aliased in the upper & lower halves of it. The I/O region |
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* obscures 256MB from 0x10000000-0x1fffffff in the low alias |
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* but the DDR it obscures is accessible via the high alias. |
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* |
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* Simply access everything beyond the lowest 256MB of DDR using |
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* the high alias. |
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*/ |
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entries++; |
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mem_array[2] = cpu_to_be32(PHYS_OFFSET + SZ_2G + SZ_256M); |
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mem_array[3] = cpu_to_be32(size); |
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} |
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done: |
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BUG_ON(entries > MAX_MEM_ARRAY_ENTRIES); |
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return entries; |
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} |
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static void __init append_memory(void *fdt, int root_off) |
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{ |
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__be32 mem_array[2 * MAX_MEM_ARRAY_ENTRIES]; |
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unsigned long memsize; |
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unsigned mem_entries; |
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int i, err, mem_off; |
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enum mem_map mem_map; |
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u32 config; |
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char *var, param_name[10], *var_names[] = { |
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"ememsize", "memsize", |
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}; |
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/* if a memory node already exists, leave it alone */ |
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mem_off = fdt_path_offset(fdt, "/memory"); |
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if (mem_off >= 0) |
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return; |
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/* find memory size from the bootloader environment */ |
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for (i = 0; i < ARRAY_SIZE(var_names); i++) { |
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var = fw_getenv(var_names[i]); |
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if (!var) |
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continue; |
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err = kstrtoul(var, 0, &physical_memsize); |
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if (!err) |
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break; |
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pr_warn("Failed to read the '%s' env variable '%s'\n", |
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var_names[i], var); |
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} |
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if (!physical_memsize) { |
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pr_warn("The bootloader didn't provide memsize: defaulting to 32MB\n"); |
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physical_memsize = 32 << 20; |
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} |
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if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) { |
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/* |
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* SOC-it swaps, or perhaps doesn't swap, when DMA'ing |
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* the last word of physical memory. |
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*/ |
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physical_memsize -= PAGE_SIZE; |
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} |
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/* default to using all available RAM */ |
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memsize = physical_memsize; |
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/* allow the user to override the usable memory */ |
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for (i = 0; i < ARRAY_SIZE(var_names); i++) { |
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snprintf(param_name, sizeof(param_name), "%s=", var_names[i]); |
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var = strstr(arcs_cmdline, param_name); |
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if (!var) |
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continue; |
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memsize = memparse(var + strlen(param_name), NULL); |
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} |
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/* if the user says there's more RAM than we thought, believe them */ |
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physical_memsize = max_t(unsigned long, physical_memsize, memsize); |
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/* detect the memory map in use */ |
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if (malta_scon() == MIPS_REVISION_SCON_ROCIT) { |
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/* ROCit has a register indicating the memory map in use */ |
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config = readl((void __iomem *)CKSEG1ADDR(ROCIT_CONFIG_GEN1)); |
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mem_map = config & ROCIT_CONFIG_GEN1_MEMMAP_MASK; |
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mem_map >>= ROCIT_CONFIG_GEN1_MEMMAP_SHIFT; |
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} else { |
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/* if not using ROCit, presume the v1 memory map */ |
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mem_map = MEM_MAP_V1; |
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} |
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if (mem_map > MEM_MAP_V2) |
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panic("Unsupported physical memory map v%u detected", |
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(unsigned int)mem_map); |
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/* append memory to the DT */ |
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mem_off = fdt_add_subnode(fdt, root_off, "memory"); |
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if (mem_off < 0) |
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panic("Unable to add memory node to DT: %d", mem_off); |
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err = fdt_setprop_string(fdt, mem_off, "device_type", "memory"); |
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if (err) |
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panic("Unable to set memory node device_type: %d", err); |
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mem_entries = gen_fdt_mem_array(mem_array, physical_memsize, mem_map); |
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err = fdt_setprop(fdt, mem_off, "reg", mem_array, |
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mem_entries * 2 * sizeof(mem_array[0])); |
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if (err) |
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panic("Unable to set memory regs property: %d", err); |
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mem_entries = gen_fdt_mem_array(mem_array, memsize, mem_map); |
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err = fdt_setprop(fdt, mem_off, "linux,usable-memory", mem_array, |
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mem_entries * 2 * sizeof(mem_array[0])); |
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if (err) |
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panic("Unable to set linux,usable-memory property: %d", err); |
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} |
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static void __init remove_gic(void *fdt) |
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{ |
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int err, gic_off, i8259_off, cpu_off; |
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void __iomem *biu_base; |
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uint32_t cpu_phandle, sc_cfg; |
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/* if we have a CM which reports a GIC is present, leave the DT alone */ |
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err = mips_cm_probe(); |
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if (!err && (read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX)) |
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return; |
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if (malta_scon() == MIPS_REVISION_SCON_ROCIT) { |
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/* |
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* On systems using the RocIT system controller a GIC may be |
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* present without a CM. Detect whether that is the case. |
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*/ |
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biu_base = ioremap(MSC01_BIU_REG_BASE, |
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MSC01_BIU_ADDRSPACE_SZ); |
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sc_cfg = __raw_readl(biu_base + MSC01_SC_CFG_OFS); |
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if (sc_cfg & MSC01_SC_CFG_GICPRES_MSK) { |
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/* enable the GIC at the system controller level */ |
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sc_cfg |= BIT(MSC01_SC_CFG_GICENA_SHF); |
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__raw_writel(sc_cfg, biu_base + MSC01_SC_CFG_OFS); |
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return; |
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} |
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} |
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gic_off = fdt_node_offset_by_compatible(fdt, -1, "mti,gic"); |
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if (gic_off < 0) { |
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pr_warn("malta-dtshim: unable to find DT GIC node: %d\n", |
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gic_off); |
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return; |
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} |
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err = fdt_nop_node(fdt, gic_off); |
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if (err) |
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pr_warn("malta-dtshim: unable to nop GIC node\n"); |
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i8259_off = fdt_node_offset_by_compatible(fdt, -1, "intel,i8259"); |
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if (i8259_off < 0) { |
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pr_warn("malta-dtshim: unable to find DT i8259 node: %d\n", |
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i8259_off); |
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return; |
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} |
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cpu_off = fdt_node_offset_by_compatible(fdt, -1, |
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"mti,cpu-interrupt-controller"); |
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if (cpu_off < 0) { |
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pr_warn("malta-dtshim: unable to find CPU intc node: %d\n", |
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cpu_off); |
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return; |
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} |
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cpu_phandle = fdt_get_phandle(fdt, cpu_off); |
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if (!cpu_phandle) { |
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pr_warn("malta-dtshim: unable to get CPU intc phandle\n"); |
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return; |
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} |
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err = fdt_setprop_u32(fdt, i8259_off, "interrupt-parent", cpu_phandle); |
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if (err) { |
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pr_warn("malta-dtshim: unable to set i8259 interrupt-parent: %d\n", |
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err); |
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return; |
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} |
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err = fdt_setprop_u32(fdt, i8259_off, "interrupts", 2); |
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if (err) { |
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pr_warn("malta-dtshim: unable to set i8259 interrupts: %d\n", |
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err); |
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return; |
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} |
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} |
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void __init *malta_dt_shim(void *fdt) |
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{ |
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int root_off, len, err; |
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const char *compat; |
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if (fdt_check_header(fdt)) |
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panic("Corrupt DT"); |
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err = fdt_open_into(fdt, fdt_buf, sizeof(fdt_buf)); |
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if (err) |
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panic("Unable to open FDT: %d", err); |
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root_off = fdt_path_offset(fdt_buf, "/"); |
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if (root_off < 0) |
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panic("No / node in DT"); |
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compat = fdt_getprop(fdt_buf, root_off, "compatible", &len); |
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if (!compat) |
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panic("No root compatible property in DT: %d", len); |
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/* if this isn't Malta, leave the DT alone */ |
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if (strncmp(compat, "mti,malta", len)) |
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return fdt; |
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append_memory(fdt_buf, root_off); |
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remove_gic(fdt_buf); |
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err = fdt_pack(fdt_buf); |
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if (err) |
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panic("Unable to pack FDT: %d\n", err); |
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return fdt_buf; |
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}
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