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583 lines
14 KiB
583 lines
14 KiB
/* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 1996 David S. Miller ([email protected]) |
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* Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle [email protected] |
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* Carsten Langgaard, [email protected] |
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* Copyright (C) 2002 MIPS Technologies, Inc. All rights reserved. |
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*/ |
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#include <linux/cpu_pm.h> |
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#include <linux/init.h> |
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#include <linux/sched.h> |
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#include <linux/smp.h> |
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#include <linux/mm.h> |
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#include <linux/hugetlb.h> |
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#include <linux/export.h> |
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|
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#include <asm/cpu.h> |
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#include <asm/cpu-type.h> |
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#include <asm/bootinfo.h> |
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#include <asm/hazards.h> |
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#include <asm/mmu_context.h> |
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#include <asm/tlb.h> |
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#include <asm/tlbmisc.h> |
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|
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extern void build_tlb_refill_handler(void); |
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|
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/* |
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* LOONGSON-2 has a 4 entry itlb which is a subset of jtlb, LOONGSON-3 has |
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* a 4 entry itlb and a 4 entry dtlb which are subsets of jtlb. Unfortunately, |
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* itlb/dtlb are not totally transparent to software. |
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*/ |
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static inline void flush_micro_tlb(void) |
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{ |
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switch (current_cpu_type()) { |
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case CPU_LOONGSON2EF: |
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write_c0_diag(LOONGSON_DIAG_ITLB); |
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break; |
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case CPU_LOONGSON64: |
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write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB); |
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break; |
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default: |
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break; |
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} |
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} |
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|
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static inline void flush_micro_tlb_vm(struct vm_area_struct *vma) |
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{ |
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if (vma->vm_flags & VM_EXEC) |
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flush_micro_tlb(); |
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} |
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|
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void local_flush_tlb_all(void) |
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{ |
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unsigned long flags; |
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unsigned long old_ctx; |
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int entry, ftlbhighset; |
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|
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local_irq_save(flags); |
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/* Save old context and create impossible VPN2 value */ |
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old_ctx = read_c0_entryhi(); |
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htw_stop(); |
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write_c0_entrylo0(0); |
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write_c0_entrylo1(0); |
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|
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entry = num_wired_entries(); |
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|
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/* |
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* Blast 'em all away. |
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* If there are any wired entries, fall back to iterating |
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*/ |
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if (cpu_has_tlbinv && !entry) { |
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if (current_cpu_data.tlbsizevtlb) { |
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write_c0_index(0); |
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mtc0_tlbw_hazard(); |
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tlbinvf(); /* invalidate VTLB */ |
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} |
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ftlbhighset = current_cpu_data.tlbsizevtlb + |
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current_cpu_data.tlbsizeftlbsets; |
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for (entry = current_cpu_data.tlbsizevtlb; |
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entry < ftlbhighset; |
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entry++) { |
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write_c0_index(entry); |
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mtc0_tlbw_hazard(); |
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tlbinvf(); /* invalidate one FTLB set */ |
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} |
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} else { |
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while (entry < current_cpu_data.tlbsize) { |
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/* Make sure all entries differ. */ |
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write_c0_entryhi(UNIQUE_ENTRYHI(entry)); |
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write_c0_index(entry); |
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mtc0_tlbw_hazard(); |
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tlb_write_indexed(); |
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entry++; |
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} |
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} |
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tlbw_use_hazard(); |
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write_c0_entryhi(old_ctx); |
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htw_start(); |
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flush_micro_tlb(); |
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local_irq_restore(flags); |
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} |
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EXPORT_SYMBOL(local_flush_tlb_all); |
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|
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void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, |
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unsigned long end) |
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{ |
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struct mm_struct *mm = vma->vm_mm; |
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int cpu = smp_processor_id(); |
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|
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if (cpu_context(cpu, mm) != 0) { |
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unsigned long size, flags; |
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|
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local_irq_save(flags); |
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start = round_down(start, PAGE_SIZE << 1); |
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end = round_up(end, PAGE_SIZE << 1); |
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size = (end - start) >> (PAGE_SHIFT + 1); |
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if (size <= (current_cpu_data.tlbsizeftlbsets ? |
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current_cpu_data.tlbsize / 8 : |
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current_cpu_data.tlbsize / 2)) { |
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unsigned long old_entryhi, old_mmid; |
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int newpid = cpu_asid(cpu, mm); |
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|
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old_entryhi = read_c0_entryhi(); |
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if (cpu_has_mmid) { |
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old_mmid = read_c0_memorymapid(); |
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write_c0_memorymapid(newpid); |
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} |
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|
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htw_stop(); |
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while (start < end) { |
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int idx; |
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|
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if (cpu_has_mmid) |
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write_c0_entryhi(start); |
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else |
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write_c0_entryhi(start | newpid); |
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start += (PAGE_SIZE << 1); |
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mtc0_tlbw_hazard(); |
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tlb_probe(); |
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tlb_probe_hazard(); |
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idx = read_c0_index(); |
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write_c0_entrylo0(0); |
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write_c0_entrylo1(0); |
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if (idx < 0) |
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continue; |
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/* Make sure all entries differ. */ |
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write_c0_entryhi(UNIQUE_ENTRYHI(idx)); |
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mtc0_tlbw_hazard(); |
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tlb_write_indexed(); |
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} |
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tlbw_use_hazard(); |
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write_c0_entryhi(old_entryhi); |
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if (cpu_has_mmid) |
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write_c0_memorymapid(old_mmid); |
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htw_start(); |
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} else { |
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drop_mmu_context(mm); |
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} |
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flush_micro_tlb(); |
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local_irq_restore(flags); |
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} |
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} |
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|
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void local_flush_tlb_kernel_range(unsigned long start, unsigned long end) |
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{ |
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unsigned long size, flags; |
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|
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local_irq_save(flags); |
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT; |
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size = (size + 1) >> 1; |
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if (size <= (current_cpu_data.tlbsizeftlbsets ? |
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current_cpu_data.tlbsize / 8 : |
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current_cpu_data.tlbsize / 2)) { |
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int pid = read_c0_entryhi(); |
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|
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start &= (PAGE_MASK << 1); |
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end += ((PAGE_SIZE << 1) - 1); |
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end &= (PAGE_MASK << 1); |
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htw_stop(); |
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|
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while (start < end) { |
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int idx; |
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|
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write_c0_entryhi(start); |
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start += (PAGE_SIZE << 1); |
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mtc0_tlbw_hazard(); |
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tlb_probe(); |
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tlb_probe_hazard(); |
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idx = read_c0_index(); |
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write_c0_entrylo0(0); |
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write_c0_entrylo1(0); |
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if (idx < 0) |
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continue; |
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/* Make sure all entries differ. */ |
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write_c0_entryhi(UNIQUE_ENTRYHI(idx)); |
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mtc0_tlbw_hazard(); |
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tlb_write_indexed(); |
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} |
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tlbw_use_hazard(); |
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write_c0_entryhi(pid); |
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htw_start(); |
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} else { |
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local_flush_tlb_all(); |
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} |
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flush_micro_tlb(); |
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local_irq_restore(flags); |
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} |
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|
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void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) |
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{ |
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int cpu = smp_processor_id(); |
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|
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if (cpu_context(cpu, vma->vm_mm) != 0) { |
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unsigned long old_mmid; |
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unsigned long flags, old_entryhi; |
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int idx; |
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|
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page &= (PAGE_MASK << 1); |
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local_irq_save(flags); |
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old_entryhi = read_c0_entryhi(); |
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htw_stop(); |
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if (cpu_has_mmid) { |
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old_mmid = read_c0_memorymapid(); |
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write_c0_entryhi(page); |
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write_c0_memorymapid(cpu_asid(cpu, vma->vm_mm)); |
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} else { |
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write_c0_entryhi(page | cpu_asid(cpu, vma->vm_mm)); |
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} |
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mtc0_tlbw_hazard(); |
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tlb_probe(); |
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tlb_probe_hazard(); |
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idx = read_c0_index(); |
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write_c0_entrylo0(0); |
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write_c0_entrylo1(0); |
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if (idx < 0) |
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goto finish; |
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/* Make sure all entries differ. */ |
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write_c0_entryhi(UNIQUE_ENTRYHI(idx)); |
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mtc0_tlbw_hazard(); |
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tlb_write_indexed(); |
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tlbw_use_hazard(); |
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|
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finish: |
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write_c0_entryhi(old_entryhi); |
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if (cpu_has_mmid) |
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write_c0_memorymapid(old_mmid); |
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htw_start(); |
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flush_micro_tlb_vm(vma); |
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local_irq_restore(flags); |
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} |
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} |
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|
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/* |
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* This one is only used for pages with the global bit set so we don't care |
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* much about the ASID. |
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*/ |
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void local_flush_tlb_one(unsigned long page) |
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{ |
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unsigned long flags; |
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int oldpid, idx; |
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|
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local_irq_save(flags); |
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oldpid = read_c0_entryhi(); |
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htw_stop(); |
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page &= (PAGE_MASK << 1); |
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write_c0_entryhi(page); |
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mtc0_tlbw_hazard(); |
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tlb_probe(); |
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tlb_probe_hazard(); |
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idx = read_c0_index(); |
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write_c0_entrylo0(0); |
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write_c0_entrylo1(0); |
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if (idx >= 0) { |
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/* Make sure all entries differ. */ |
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write_c0_entryhi(UNIQUE_ENTRYHI(idx)); |
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mtc0_tlbw_hazard(); |
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tlb_write_indexed(); |
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tlbw_use_hazard(); |
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} |
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write_c0_entryhi(oldpid); |
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htw_start(); |
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flush_micro_tlb(); |
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local_irq_restore(flags); |
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} |
|
|
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/* |
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* We will need multiple versions of update_mmu_cache(), one that just |
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* updates the TLB with the new pte(s), and another which also checks |
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* for the R4k "end of page" hardware bug and does the needy. |
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*/ |
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void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) |
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{ |
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unsigned long flags; |
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pgd_t *pgdp; |
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p4d_t *p4dp; |
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pud_t *pudp; |
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pmd_t *pmdp; |
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pte_t *ptep; |
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int idx, pid; |
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|
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/* |
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* Handle debugger faulting in for debugee. |
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*/ |
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if (current->active_mm != vma->vm_mm) |
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return; |
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|
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local_irq_save(flags); |
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|
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htw_stop(); |
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address &= (PAGE_MASK << 1); |
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if (cpu_has_mmid) { |
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write_c0_entryhi(address); |
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} else { |
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pid = read_c0_entryhi() & cpu_asid_mask(¤t_cpu_data); |
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write_c0_entryhi(address | pid); |
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} |
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pgdp = pgd_offset(vma->vm_mm, address); |
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mtc0_tlbw_hazard(); |
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tlb_probe(); |
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tlb_probe_hazard(); |
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p4dp = p4d_offset(pgdp, address); |
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pudp = pud_offset(p4dp, address); |
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pmdp = pmd_offset(pudp, address); |
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idx = read_c0_index(); |
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#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT |
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/* this could be a huge page */ |
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if (pmd_huge(*pmdp)) { |
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unsigned long lo; |
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write_c0_pagemask(PM_HUGE_MASK); |
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ptep = (pte_t *)pmdp; |
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lo = pte_to_entrylo(pte_val(*ptep)); |
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write_c0_entrylo0(lo); |
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write_c0_entrylo1(lo + (HPAGE_SIZE >> 7)); |
|
|
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mtc0_tlbw_hazard(); |
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if (idx < 0) |
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tlb_write_random(); |
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else |
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tlb_write_indexed(); |
|
tlbw_use_hazard(); |
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write_c0_pagemask(PM_DEFAULT_MASK); |
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} else |
|
#endif |
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{ |
|
ptep = pte_offset_map(pmdp, address); |
|
|
|
#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) |
|
#ifdef CONFIG_XPA |
|
write_c0_entrylo0(pte_to_entrylo(ptep->pte_high)); |
|
if (cpu_has_xpa) |
|
writex_c0_entrylo0(ptep->pte_low & _PFNX_MASK); |
|
ptep++; |
|
write_c0_entrylo1(pte_to_entrylo(ptep->pte_high)); |
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if (cpu_has_xpa) |
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writex_c0_entrylo1(ptep->pte_low & _PFNX_MASK); |
|
#else |
|
write_c0_entrylo0(ptep->pte_high); |
|
ptep++; |
|
write_c0_entrylo1(ptep->pte_high); |
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#endif |
|
#else |
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write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++))); |
|
write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep))); |
|
#endif |
|
mtc0_tlbw_hazard(); |
|
if (idx < 0) |
|
tlb_write_random(); |
|
else |
|
tlb_write_indexed(); |
|
} |
|
tlbw_use_hazard(); |
|
htw_start(); |
|
flush_micro_tlb_vm(vma); |
|
local_irq_restore(flags); |
|
} |
|
|
|
void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, |
|
unsigned long entryhi, unsigned long pagemask) |
|
{ |
|
#ifdef CONFIG_XPA |
|
panic("Broken for XPA kernels"); |
|
#else |
|
unsigned int old_mmid; |
|
unsigned long flags; |
|
unsigned long wired; |
|
unsigned long old_pagemask; |
|
unsigned long old_ctx; |
|
|
|
local_irq_save(flags); |
|
if (cpu_has_mmid) { |
|
old_mmid = read_c0_memorymapid(); |
|
write_c0_memorymapid(MMID_KERNEL_WIRED); |
|
} |
|
/* Save old context and create impossible VPN2 value */ |
|
old_ctx = read_c0_entryhi(); |
|
htw_stop(); |
|
old_pagemask = read_c0_pagemask(); |
|
wired = num_wired_entries(); |
|
write_c0_wired(wired + 1); |
|
write_c0_index(wired); |
|
tlbw_use_hazard(); /* What is the hazard here? */ |
|
write_c0_pagemask(pagemask); |
|
write_c0_entryhi(entryhi); |
|
write_c0_entrylo0(entrylo0); |
|
write_c0_entrylo1(entrylo1); |
|
mtc0_tlbw_hazard(); |
|
tlb_write_indexed(); |
|
tlbw_use_hazard(); |
|
|
|
write_c0_entryhi(old_ctx); |
|
if (cpu_has_mmid) |
|
write_c0_memorymapid(old_mmid); |
|
tlbw_use_hazard(); /* What is the hazard here? */ |
|
htw_start(); |
|
write_c0_pagemask(old_pagemask); |
|
local_flush_tlb_all(); |
|
local_irq_restore(flags); |
|
#endif |
|
} |
|
|
|
#ifdef CONFIG_TRANSPARENT_HUGEPAGE |
|
|
|
int has_transparent_hugepage(void) |
|
{ |
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static unsigned int mask = -1; |
|
|
|
if (mask == -1) { /* first call comes during __init */ |
|
unsigned long flags; |
|
|
|
local_irq_save(flags); |
|
write_c0_pagemask(PM_HUGE_MASK); |
|
back_to_back_c0_hazard(); |
|
mask = read_c0_pagemask(); |
|
write_c0_pagemask(PM_DEFAULT_MASK); |
|
local_irq_restore(flags); |
|
} |
|
return mask == PM_HUGE_MASK; |
|
} |
|
EXPORT_SYMBOL(has_transparent_hugepage); |
|
|
|
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
|
|
|
/* |
|
* Used for loading TLB entries before trap_init() has started, when we |
|
* don't actually want to add a wired entry which remains throughout the |
|
* lifetime of the system |
|
*/ |
|
|
|
int temp_tlb_entry; |
|
|
|
__init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, |
|
unsigned long entryhi, unsigned long pagemask) |
|
{ |
|
int ret = 0; |
|
unsigned long flags; |
|
unsigned long wired; |
|
unsigned long old_pagemask; |
|
unsigned long old_ctx; |
|
|
|
local_irq_save(flags); |
|
/* Save old context and create impossible VPN2 value */ |
|
htw_stop(); |
|
old_ctx = read_c0_entryhi(); |
|
old_pagemask = read_c0_pagemask(); |
|
wired = num_wired_entries(); |
|
if (--temp_tlb_entry < wired) { |
|
printk(KERN_WARNING |
|
"No TLB space left for add_temporary_entry\n"); |
|
ret = -ENOSPC; |
|
goto out; |
|
} |
|
|
|
write_c0_index(temp_tlb_entry); |
|
write_c0_pagemask(pagemask); |
|
write_c0_entryhi(entryhi); |
|
write_c0_entrylo0(entrylo0); |
|
write_c0_entrylo1(entrylo1); |
|
mtc0_tlbw_hazard(); |
|
tlb_write_indexed(); |
|
tlbw_use_hazard(); |
|
|
|
write_c0_entryhi(old_ctx); |
|
write_c0_pagemask(old_pagemask); |
|
htw_start(); |
|
out: |
|
local_irq_restore(flags); |
|
return ret; |
|
} |
|
|
|
static int ntlb; |
|
static int __init set_ntlb(char *str) |
|
{ |
|
get_option(&str, &ntlb); |
|
return 1; |
|
} |
|
|
|
__setup("ntlb=", set_ntlb); |
|
|
|
/* |
|
* Configure TLB (for init or after a CPU has been powered off). |
|
*/ |
|
static void r4k_tlb_configure(void) |
|
{ |
|
/* |
|
* You should never change this register: |
|
* - On R4600 1.7 the tlbp never hits for pages smaller than |
|
* the value in the c0_pagemask register. |
|
* - The entire mm handling assumes the c0_pagemask register to |
|
* be set to fixed-size pages. |
|
*/ |
|
write_c0_pagemask(PM_DEFAULT_MASK); |
|
back_to_back_c0_hazard(); |
|
if (read_c0_pagemask() != PM_DEFAULT_MASK) |
|
panic("MMU doesn't support PAGE_SIZE=0x%lx", PAGE_SIZE); |
|
|
|
write_c0_wired(0); |
|
if (current_cpu_type() == CPU_R10000 || |
|
current_cpu_type() == CPU_R12000 || |
|
current_cpu_type() == CPU_R14000 || |
|
current_cpu_type() == CPU_R16000) |
|
write_c0_framemask(0); |
|
|
|
if (cpu_has_rixi) { |
|
/* |
|
* Enable the no read, no exec bits, and enable large physical |
|
* address. |
|
*/ |
|
#ifdef CONFIG_64BIT |
|
set_c0_pagegrain(PG_RIE | PG_XIE | PG_ELPA); |
|
#else |
|
set_c0_pagegrain(PG_RIE | PG_XIE); |
|
#endif |
|
} |
|
|
|
temp_tlb_entry = current_cpu_data.tlbsize - 1; |
|
|
|
/* From this point on the ARC firmware is dead. */ |
|
local_flush_tlb_all(); |
|
|
|
/* Did I tell you that ARC SUCKS? */ |
|
} |
|
|
|
void tlb_init(void) |
|
{ |
|
r4k_tlb_configure(); |
|
|
|
if (ntlb) { |
|
if (ntlb > 1 && ntlb <= current_cpu_data.tlbsize) { |
|
int wired = current_cpu_data.tlbsize - ntlb; |
|
write_c0_wired(wired); |
|
write_c0_index(wired-1); |
|
printk("Restricting TLB to %d entries\n", ntlb); |
|
} else |
|
printk("Ignoring invalid argument ntlb=%d\n", ntlb); |
|
} |
|
|
|
build_tlb_refill_handler(); |
|
} |
|
|
|
static int r4k_tlb_pm_notifier(struct notifier_block *self, unsigned long cmd, |
|
void *v) |
|
{ |
|
switch (cmd) { |
|
case CPU_PM_ENTER_FAILED: |
|
case CPU_PM_EXIT: |
|
r4k_tlb_configure(); |
|
break; |
|
} |
|
|
|
return NOTIFY_OK; |
|
} |
|
|
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static struct notifier_block r4k_tlb_pm_notifier_block = { |
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.notifier_call = r4k_tlb_pm_notifier, |
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}; |
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static int __init r4k_tlb_init_pm(void) |
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{ |
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return cpu_pm_register_notifier(&r4k_tlb_pm_notifier_block); |
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} |
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arch_initcall(r4k_tlb_init_pm);
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