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264 lines
6.2 KiB
264 lines
6.2 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2006 Chris Dearman ([email protected]), |
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*/ |
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#include <linux/init.h> |
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#include <linux/kernel.h> |
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#include <linux/sched.h> |
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#include <linux/mm.h> |
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#include <asm/cpu-type.h> |
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#include <asm/mipsregs.h> |
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#include <asm/bcache.h> |
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#include <asm/cacheops.h> |
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#include <asm/page.h> |
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#include <asm/mmu_context.h> |
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#include <asm/r4kcache.h> |
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#include <asm/mips-cps.h> |
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#include <asm/bootinfo.h> |
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/* |
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* MIPS32/MIPS64 L2 cache handling |
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*/ |
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/* |
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* Writeback and invalidate the secondary cache before DMA. |
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*/ |
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static void mips_sc_wback_inv(unsigned long addr, unsigned long size) |
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{ |
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blast_scache_range(addr, addr + size); |
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} |
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/* |
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* Invalidate the secondary cache before DMA. |
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*/ |
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static void mips_sc_inv(unsigned long addr, unsigned long size) |
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{ |
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unsigned long lsize = cpu_scache_line_size(); |
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unsigned long almask = ~(lsize - 1); |
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cache_op(Hit_Writeback_Inv_SD, addr & almask); |
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cache_op(Hit_Writeback_Inv_SD, (addr + size - 1) & almask); |
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blast_inv_scache_range(addr, addr + size); |
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} |
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static void mips_sc_enable(void) |
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{ |
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/* L2 cache is permanently enabled */ |
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} |
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static void mips_sc_disable(void) |
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{ |
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/* L2 cache is permanently enabled */ |
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} |
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static void mips_sc_prefetch_enable(void) |
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{ |
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unsigned long pftctl; |
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if (mips_cm_revision() < CM_REV_CM2_5) |
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return; |
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/* |
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* If there is one or more L2 prefetch unit present then enable |
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* prefetching for both code & data, for all ports. |
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*/ |
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pftctl = read_gcr_l2_pft_control(); |
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if (pftctl & CM_GCR_L2_PFT_CONTROL_NPFT) { |
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pftctl &= ~CM_GCR_L2_PFT_CONTROL_PAGEMASK; |
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pftctl |= PAGE_MASK & CM_GCR_L2_PFT_CONTROL_PAGEMASK; |
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pftctl |= CM_GCR_L2_PFT_CONTROL_PFTEN; |
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write_gcr_l2_pft_control(pftctl); |
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set_gcr_l2_pft_control_b(CM_GCR_L2_PFT_CONTROL_B_PORTID | |
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CM_GCR_L2_PFT_CONTROL_B_CEN); |
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} |
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} |
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static void mips_sc_prefetch_disable(void) |
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{ |
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if (mips_cm_revision() < CM_REV_CM2_5) |
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return; |
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clear_gcr_l2_pft_control(CM_GCR_L2_PFT_CONTROL_PFTEN); |
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clear_gcr_l2_pft_control_b(CM_GCR_L2_PFT_CONTROL_B_PORTID | |
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CM_GCR_L2_PFT_CONTROL_B_CEN); |
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} |
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static bool mips_sc_prefetch_is_enabled(void) |
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{ |
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unsigned long pftctl; |
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if (mips_cm_revision() < CM_REV_CM2_5) |
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return false; |
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pftctl = read_gcr_l2_pft_control(); |
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if (!(pftctl & CM_GCR_L2_PFT_CONTROL_NPFT)) |
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return false; |
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return !!(pftctl & CM_GCR_L2_PFT_CONTROL_PFTEN); |
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} |
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static struct bcache_ops mips_sc_ops = { |
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.bc_enable = mips_sc_enable, |
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.bc_disable = mips_sc_disable, |
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.bc_wback_inv = mips_sc_wback_inv, |
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.bc_inv = mips_sc_inv, |
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.bc_prefetch_enable = mips_sc_prefetch_enable, |
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.bc_prefetch_disable = mips_sc_prefetch_disable, |
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.bc_prefetch_is_enabled = mips_sc_prefetch_is_enabled, |
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}; |
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/* |
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* Check if the L2 cache controller is activated on a particular platform. |
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* MTI's L2 controller and the L2 cache controller of Broadcom's BMIPS |
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* cores both use c0_config2's bit 12 as "L2 Bypass" bit, that is the |
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* cache being disabled. However there is no guarantee for this to be |
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* true on all platforms. In an act of stupidity the spec defined bits |
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* 12..15 as implementation defined so below function will eventually have |
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* to be replaced by a platform specific probe. |
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*/ |
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static inline int mips_sc_is_activated(struct cpuinfo_mips *c) |
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{ |
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unsigned int config2 = read_c0_config2(); |
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unsigned int tmp; |
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/* Check the bypass bit (L2B) */ |
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switch (current_cpu_type()) { |
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case CPU_34K: |
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case CPU_74K: |
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case CPU_1004K: |
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case CPU_1074K: |
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case CPU_INTERAPTIV: |
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case CPU_PROAPTIV: |
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case CPU_P5600: |
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case CPU_BMIPS5000: |
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case CPU_QEMU_GENERIC: |
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case CPU_P6600: |
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if (config2 & (1 << 12)) |
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return 0; |
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} |
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tmp = (config2 >> 4) & 0x0f; |
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if (0 < tmp && tmp <= 7) |
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c->scache.linesz = 2 << tmp; |
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else |
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return 0; |
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return 1; |
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} |
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static int mips_sc_probe_cm3(void) |
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{ |
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struct cpuinfo_mips *c = ¤t_cpu_data; |
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unsigned long cfg = read_gcr_l2_config(); |
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unsigned long sets, line_sz, assoc; |
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if (cfg & CM_GCR_L2_CONFIG_BYPASS) |
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return 0; |
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sets = cfg & CM_GCR_L2_CONFIG_SET_SIZE; |
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sets >>= __ffs(CM_GCR_L2_CONFIG_SET_SIZE); |
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if (sets) |
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c->scache.sets = 64 << sets; |
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line_sz = cfg & CM_GCR_L2_CONFIG_LINE_SIZE; |
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line_sz >>= __ffs(CM_GCR_L2_CONFIG_LINE_SIZE); |
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if (line_sz) |
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c->scache.linesz = 2 << line_sz; |
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assoc = cfg & CM_GCR_L2_CONFIG_ASSOC; |
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assoc >>= __ffs(CM_GCR_L2_CONFIG_ASSOC); |
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c->scache.ways = assoc + 1; |
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c->scache.waysize = c->scache.sets * c->scache.linesz; |
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c->scache.waybit = __ffs(c->scache.waysize); |
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if (c->scache.linesz) { |
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c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; |
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c->options |= MIPS_CPU_INCLUSIVE_CACHES; |
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return 1; |
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} |
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return 0; |
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} |
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static inline int mips_sc_probe(void) |
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{ |
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struct cpuinfo_mips *c = ¤t_cpu_data; |
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unsigned int config1, config2; |
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unsigned int tmp; |
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/* Mark as not present until probe completed */ |
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c->scache.flags |= MIPS_CACHE_NOT_PRESENT; |
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if (mips_cm_revision() >= CM_REV_CM3) |
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return mips_sc_probe_cm3(); |
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/* Ignore anything but MIPSxx processors */ |
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if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | |
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MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 | |
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MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5 | |
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MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))) |
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return 0; |
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/* Does this MIPS32/MIPS64 CPU have a config2 register? */ |
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config1 = read_c0_config1(); |
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if (!(config1 & MIPS_CONF_M)) |
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return 0; |
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config2 = read_c0_config2(); |
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if (!mips_sc_is_activated(c)) |
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return 0; |
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tmp = (config2 >> 8) & 0x0f; |
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if (tmp <= 7) |
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c->scache.sets = 64 << tmp; |
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else |
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return 0; |
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tmp = (config2 >> 0) & 0x0f; |
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if (tmp <= 7) |
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c->scache.ways = tmp + 1; |
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else |
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return 0; |
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if (current_cpu_type() == CPU_XBURST) { |
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switch (mips_machtype) { |
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/* |
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* According to config2 it would be 5-ways, but that is |
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* contradicted by all documentation. |
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*/ |
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case MACH_INGENIC_JZ4770: |
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case MACH_INGENIC_JZ4775: |
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c->scache.ways = 4; |
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break; |
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/* |
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* According to config2 it would be 5-ways and 512-sets, |
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* but that is contradicted by all documentation. |
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*/ |
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case MACH_INGENIC_X1000: |
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case MACH_INGENIC_X1000E: |
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c->scache.sets = 256; |
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c->scache.ways = 4; |
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break; |
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} |
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} |
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c->scache.waysize = c->scache.sets * c->scache.linesz; |
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c->scache.waybit = __ffs(c->scache.waysize); |
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c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; |
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return 1; |
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} |
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int mips_sc_init(void) |
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{ |
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int found = mips_sc_probe(); |
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if (found) { |
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mips_sc_enable(); |
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mips_sc_prefetch_enable(); |
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bcops = &mips_sc_ops; |
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} |
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return found; |
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}
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