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70 lines
1.5 KiB
70 lines
1.5 KiB
/* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 2006 Cavium Networks |
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* Cache error handler |
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*/ |
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#include <asm/asm.h> |
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#include <asm/regdef.h> |
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#include <asm/mipsregs.h> |
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#include <asm/stackframe.h> |
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/* |
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* Handle cache error. Indicate to the second level handler whether |
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* the exception is recoverable. |
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*/ |
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LEAF(except_vec2_octeon) |
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.set push |
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.set mips64r2 |
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.set noreorder |
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.set noat |
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/* due to an errata we need to read the COP0 CacheErr (Dcache) |
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* before any cache/DRAM access */ |
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rdhwr k0, $0 /* get core_id */ |
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PTR_LA k1, cache_err_dcache |
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sll k0, k0, 3 |
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PTR_ADDU k1, k0, k1 /* k1 = &cache_err_dcache[core_id] */ |
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dmfc0 k0, CP0_CACHEERR, 1 |
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sd k0, (k1) |
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dmtc0 $0, CP0_CACHEERR, 1 |
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/* check whether this is a nested exception */ |
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mfc0 k1, CP0_STATUS |
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andi k1, k1, ST0_EXL |
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beqz k1, 1f |
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nop |
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j cache_parity_error_octeon_non_recoverable |
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nop |
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/* exception is recoverable */ |
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1: j handle_cache_err |
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nop |
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.set pop |
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END(except_vec2_octeon) |
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/* We need to jump to handle_cache_err so that the previous handler |
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* can fit within 0x80 bytes. We also move from 0xFFFFFFFFAXXXXXXX |
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* space (uncached) to the 0xFFFFFFFF8XXXXXXX space (cached). */ |
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LEAF(handle_cache_err) |
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.set push |
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.set noreorder |
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.set noat |
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SAVE_ALL |
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KMODE |
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jal cache_parity_error_octeon_recoverable |
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nop |
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j ret_from_exception |
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nop |
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.set pop |
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END(handle_cache_err)
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