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569 lines
16 KiB
569 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (C) 2001,2002,2003 Broadcom Corporation |
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*/ |
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#include <linux/sched.h> |
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#include <asm/mipsregs.h> |
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#include <asm/sibyte/sb1250.h> |
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#include <asm/sibyte/sb1250_regs.h> |
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|
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#if !defined(CONFIG_SIBYTE_BUS_WATCHER) || defined(CONFIG_SIBYTE_BW_TRACE) |
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#include <asm/io.h> |
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#include <asm/sibyte/sb1250_scd.h> |
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#endif |
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|
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/* |
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* We'd like to dump the L2_ECC_TAG register on errors, but errata make |
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* that unsafe... So for now we don't. (BCM1250/BCM112x erratum SOC-48.) |
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*/ |
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#undef DUMP_L2_ECC_TAG_ON_ERROR |
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|
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/* SB1 definitions */ |
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|
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/* XXX should come from config1 XXX */ |
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#define SB1_CACHE_INDEX_MASK 0x1fe0 |
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|
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#define CP0_ERRCTL_RECOVERABLE (1 << 31) |
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#define CP0_ERRCTL_DCACHE (1 << 30) |
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#define CP0_ERRCTL_ICACHE (1 << 29) |
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#define CP0_ERRCTL_MULTIBUS (1 << 23) |
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#define CP0_ERRCTL_MC_TLB (1 << 15) |
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#define CP0_ERRCTL_MC_TIMEOUT (1 << 14) |
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#define CP0_CERRI_TAG_PARITY (1 << 29) |
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#define CP0_CERRI_DATA_PARITY (1 << 28) |
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#define CP0_CERRI_EXTERNAL (1 << 26) |
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|
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#define CP0_CERRI_IDX_VALID(c) (!((c) & CP0_CERRI_EXTERNAL)) |
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#define CP0_CERRI_DATA (CP0_CERRI_DATA_PARITY) |
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|
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#define CP0_CERRD_MULTIPLE (1 << 31) |
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#define CP0_CERRD_TAG_STATE (1 << 30) |
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#define CP0_CERRD_TAG_ADDRESS (1 << 29) |
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#define CP0_CERRD_DATA_SBE (1 << 28) |
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#define CP0_CERRD_DATA_DBE (1 << 27) |
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#define CP0_CERRD_EXTERNAL (1 << 26) |
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#define CP0_CERRD_LOAD (1 << 25) |
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#define CP0_CERRD_STORE (1 << 24) |
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#define CP0_CERRD_FILLWB (1 << 23) |
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#define CP0_CERRD_COHERENCY (1 << 22) |
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#define CP0_CERRD_DUPTAG (1 << 21) |
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|
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#define CP0_CERRD_DPA_VALID(c) (!((c) & CP0_CERRD_EXTERNAL)) |
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#define CP0_CERRD_IDX_VALID(c) \ |
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(((c) & (CP0_CERRD_LOAD | CP0_CERRD_STORE)) ? (!((c) & CP0_CERRD_EXTERNAL)) : 0) |
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#define CP0_CERRD_CAUSES \ |
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(CP0_CERRD_LOAD | CP0_CERRD_STORE | CP0_CERRD_FILLWB | CP0_CERRD_COHERENCY | CP0_CERRD_DUPTAG) |
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#define CP0_CERRD_TYPES \ |
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(CP0_CERRD_TAG_STATE | CP0_CERRD_TAG_ADDRESS | CP0_CERRD_DATA_SBE | CP0_CERRD_DATA_DBE | CP0_CERRD_EXTERNAL) |
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#define CP0_CERRD_DATA (CP0_CERRD_DATA_SBE | CP0_CERRD_DATA_DBE) |
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|
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static uint32_t extract_ic(unsigned short addr, int data); |
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static uint32_t extract_dc(unsigned short addr, int data); |
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|
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static inline void breakout_errctl(unsigned int val) |
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{ |
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if (val & CP0_ERRCTL_RECOVERABLE) |
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printk(" recoverable"); |
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if (val & CP0_ERRCTL_DCACHE) |
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printk(" dcache"); |
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if (val & CP0_ERRCTL_ICACHE) |
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printk(" icache"); |
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if (val & CP0_ERRCTL_MULTIBUS) |
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printk(" multiple-buserr"); |
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printk("\n"); |
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} |
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|
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static inline void breakout_cerri(unsigned int val) |
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{ |
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if (val & CP0_CERRI_TAG_PARITY) |
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printk(" tag-parity"); |
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if (val & CP0_CERRI_DATA_PARITY) |
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printk(" data-parity"); |
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if (val & CP0_CERRI_EXTERNAL) |
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printk(" external"); |
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printk("\n"); |
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} |
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|
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static inline void breakout_cerrd(unsigned int val) |
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{ |
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switch (val & CP0_CERRD_CAUSES) { |
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case CP0_CERRD_LOAD: |
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printk(" load,"); |
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break; |
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case CP0_CERRD_STORE: |
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printk(" store,"); |
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break; |
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case CP0_CERRD_FILLWB: |
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printk(" fill/wb,"); |
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break; |
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case CP0_CERRD_COHERENCY: |
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printk(" coherency,"); |
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break; |
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case CP0_CERRD_DUPTAG: |
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printk(" duptags,"); |
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break; |
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default: |
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printk(" NO CAUSE,"); |
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break; |
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} |
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if (!(val & CP0_CERRD_TYPES)) |
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printk(" NO TYPE"); |
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else { |
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if (val & CP0_CERRD_MULTIPLE) |
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printk(" multi-err"); |
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if (val & CP0_CERRD_TAG_STATE) |
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printk(" tag-state"); |
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if (val & CP0_CERRD_TAG_ADDRESS) |
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printk(" tag-address"); |
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if (val & CP0_CERRD_DATA_SBE) |
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printk(" data-SBE"); |
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if (val & CP0_CERRD_DATA_DBE) |
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printk(" data-DBE"); |
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if (val & CP0_CERRD_EXTERNAL) |
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printk(" external"); |
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} |
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printk("\n"); |
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} |
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|
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#ifndef CONFIG_SIBYTE_BUS_WATCHER |
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|
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static void check_bus_watcher(void) |
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{ |
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uint32_t status, l2_err, memio_err; |
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#ifdef DUMP_L2_ECC_TAG_ON_ERROR |
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uint64_t l2_tag; |
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#endif |
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|
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/* Destructive read, clears register and interrupt */ |
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status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS)); |
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/* Bit 31 is always on, but there's no #define for that */ |
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if (status & ~(1UL << 31)) { |
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l2_err = csr_in32(IOADDR(A_BUS_L2_ERRORS)); |
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#ifdef DUMP_L2_ECC_TAG_ON_ERROR |
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l2_tag = in64(IOADDR(A_L2_ECC_TAG)); |
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#endif |
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memio_err = csr_in32(IOADDR(A_BUS_MEM_IO_ERRORS)); |
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printk("Bus watcher error counters: %08x %08x\n", l2_err, memio_err); |
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printk("\nLast recorded signature:\n"); |
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printk("Request %02x from %d, answered by %d with Dcode %d\n", |
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(unsigned int)(G_SCD_BERR_TID(status) & 0x3f), |
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(int)(G_SCD_BERR_TID(status) >> 6), |
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(int)G_SCD_BERR_RID(status), |
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(int)G_SCD_BERR_DCODE(status)); |
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#ifdef DUMP_L2_ECC_TAG_ON_ERROR |
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printk("Last L2 tag w/ bad ECC: %016llx\n", l2_tag); |
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#endif |
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} else { |
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printk("Bus watcher indicates no error\n"); |
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} |
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} |
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#else |
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extern void check_bus_watcher(void); |
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#endif |
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asmlinkage void sb1_cache_error(void) |
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{ |
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uint32_t errctl, cerr_i, cerr_d, dpalo, dpahi, eepc, res; |
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unsigned long long cerr_dpa; |
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|
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#ifdef CONFIG_SIBYTE_BW_TRACE |
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/* Freeze the trace buffer now */ |
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csr_out32(M_SCD_TRACE_CFG_FREEZE, IOADDR(A_SCD_TRACE_CFG)); |
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printk("Trace buffer frozen\n"); |
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#endif |
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printk("Cache error exception on CPU %x:\n", |
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(read_c0_prid() >> 25) & 0x7); |
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|
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__asm__ __volatile__ ( |
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" .set push\n\t" |
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" .set mips64\n\t" |
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" .set noat\n\t" |
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" mfc0 %0, $26\n\t" |
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" mfc0 %1, $27\n\t" |
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" mfc0 %2, $27, 1\n\t" |
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" dmfc0 $1, $27, 3\n\t" |
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" dsrl32 %3, $1, 0 \n\t" |
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" sll %4, $1, 0 \n\t" |
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" mfc0 %5, $30\n\t" |
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" .set pop" |
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: "=r" (errctl), "=r" (cerr_i), "=r" (cerr_d), |
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"=r" (dpahi), "=r" (dpalo), "=r" (eepc)); |
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|
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cerr_dpa = (((uint64_t)dpahi) << 32) | dpalo; |
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printk(" c0_errorepc == %08x\n", eepc); |
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printk(" c0_errctl == %08x", errctl); |
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breakout_errctl(errctl); |
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if (errctl & CP0_ERRCTL_ICACHE) { |
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printk(" c0_cerr_i == %08x", cerr_i); |
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breakout_cerri(cerr_i); |
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if (CP0_CERRI_IDX_VALID(cerr_i)) { |
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/* Check index of EPC, allowing for delay slot */ |
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if (((eepc & SB1_CACHE_INDEX_MASK) != (cerr_i & SB1_CACHE_INDEX_MASK)) && |
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((eepc & SB1_CACHE_INDEX_MASK) != ((cerr_i & SB1_CACHE_INDEX_MASK) - 4))) |
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printk(" cerr_i idx doesn't match eepc\n"); |
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else { |
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res = extract_ic(cerr_i & SB1_CACHE_INDEX_MASK, |
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(cerr_i & CP0_CERRI_DATA) != 0); |
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if (!(res & cerr_i)) |
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printk("...didn't see indicated icache problem\n"); |
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} |
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} |
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} |
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if (errctl & CP0_ERRCTL_DCACHE) { |
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printk(" c0_cerr_d == %08x", cerr_d); |
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breakout_cerrd(cerr_d); |
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if (CP0_CERRD_DPA_VALID(cerr_d)) { |
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printk(" c0_cerr_dpa == %010llx\n", cerr_dpa); |
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if (!CP0_CERRD_IDX_VALID(cerr_d)) { |
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res = extract_dc(cerr_dpa & SB1_CACHE_INDEX_MASK, |
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(cerr_d & CP0_CERRD_DATA) != 0); |
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if (!(res & cerr_d)) |
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printk("...didn't see indicated dcache problem\n"); |
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} else { |
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if ((cerr_dpa & SB1_CACHE_INDEX_MASK) != (cerr_d & SB1_CACHE_INDEX_MASK)) |
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printk(" cerr_d idx doesn't match cerr_dpa\n"); |
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else { |
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res = extract_dc(cerr_d & SB1_CACHE_INDEX_MASK, |
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(cerr_d & CP0_CERRD_DATA) != 0); |
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if (!(res & cerr_d)) |
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printk("...didn't see indicated problem\n"); |
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} |
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} |
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} |
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} |
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check_bus_watcher(); |
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|
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/* |
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* Calling panic() when a fatal cache error occurs scrambles the |
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* state of the system (and the cache), making it difficult to |
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* investigate after the fact. However, if you just stall the CPU, |
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* the other CPU may keep on running, which is typically very |
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* undesirable. |
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*/ |
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#ifdef CONFIG_SB1_CERR_STALL |
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while (1) |
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; |
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#else |
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panic("unhandled cache error"); |
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#endif |
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} |
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/* Parity lookup table. */ |
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static const uint8_t parity[256] = { |
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, |
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, |
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, |
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, |
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, |
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, |
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, |
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, |
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, |
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, |
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, |
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, |
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, |
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, |
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1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, |
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0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0 |
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}; |
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|
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/* Masks to select bits for Hamming parity, mask_72_64[i] for bit[i] */ |
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static const uint64_t mask_72_64[8] = { |
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0x0738C808099264FFULL, |
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0x38C808099264FF07ULL, |
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0xC808099264FF0738ULL, |
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0x08099264FF0738C8ULL, |
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0x099264FF0738C808ULL, |
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0x9264FF0738C80809ULL, |
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0x64FF0738C8080992ULL, |
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0xFF0738C808099264ULL |
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}; |
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|
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/* Calculate the parity on a range of bits */ |
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static char range_parity(uint64_t dword, int max, int min) |
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{ |
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char parity = 0; |
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int i; |
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dword >>= min; |
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for (i=max-min; i>=0; i--) { |
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if (dword & 0x1) |
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parity = !parity; |
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dword >>= 1; |
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} |
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return parity; |
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} |
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|
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/* Calculate the 4-bit even byte-parity for an instruction */ |
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static unsigned char inst_parity(uint32_t word) |
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{ |
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int i, j; |
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char parity = 0; |
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for (j=0; j<4; j++) { |
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char byte_parity = 0; |
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for (i=0; i<8; i++) { |
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if (word & 0x80000000) |
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byte_parity = !byte_parity; |
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word <<= 1; |
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} |
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parity <<= 1; |
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parity |= byte_parity; |
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} |
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return parity; |
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} |
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|
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static uint32_t extract_ic(unsigned short addr, int data) |
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{ |
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unsigned short way; |
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int valid; |
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uint32_t taghi, taglolo, taglohi; |
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unsigned long long taglo, va; |
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uint64_t tlo_tmp; |
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uint8_t lru; |
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int res = 0; |
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|
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printk("Icache index 0x%04x ", addr); |
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for (way = 0; way < 4; way++) { |
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/* Index-load-tag-I */ |
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__asm__ __volatile__ ( |
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" .set push \n\t" |
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" .set noreorder \n\t" |
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" .set mips64 \n\t" |
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" .set noat \n\t" |
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" cache 4, 0(%3) \n\t" |
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" mfc0 %0, $29 \n\t" |
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" dmfc0 $1, $28 \n\t" |
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" dsrl32 %1, $1, 0 \n\t" |
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" sll %2, $1, 0 \n\t" |
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" .set pop" |
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: "=r" (taghi), "=r" (taglohi), "=r" (taglolo) |
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: "r" ((way << 13) | addr)); |
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|
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taglo = ((unsigned long long)taglohi << 32) | taglolo; |
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if (way == 0) { |
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lru = (taghi >> 14) & 0xff; |
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printk("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n", |
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((addr >> 5) & 0x3), /* bank */ |
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((addr >> 7) & 0x3f), /* index */ |
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(lru & 0x3), |
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((lru >> 2) & 0x3), |
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((lru >> 4) & 0x3), |
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((lru >> 6) & 0x3)); |
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} |
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va = (taglo & 0xC0000FFFFFFFE000ULL) | addr; |
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if ((taglo & (1 << 31)) && (((taglo >> 62) & 0x3) == 3)) |
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va |= 0x3FFFF00000000000ULL; |
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valid = ((taghi >> 29) & 1); |
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if (valid) { |
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tlo_tmp = taglo & 0xfff3ff; |
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if (((taglo >> 10) & 1) ^ range_parity(tlo_tmp, 23, 0)) { |
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printk(" ** bad parity in VTag0/G/ASID\n"); |
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res |= CP0_CERRI_TAG_PARITY; |
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} |
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if (((taglo >> 11) & 1) ^ range_parity(taglo, 63, 24)) { |
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printk(" ** bad parity in R/VTag1\n"); |
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res |= CP0_CERRI_TAG_PARITY; |
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} |
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} |
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if (valid ^ ((taghi >> 27) & 1)) { |
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printk(" ** bad parity for valid bit\n"); |
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res |= CP0_CERRI_TAG_PARITY; |
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} |
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printk(" %d [VA %016llx] [Vld? %d] raw tags: %08X-%016llX\n", |
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way, va, valid, taghi, taglo); |
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|
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if (data) { |
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uint32_t datahi, insta, instb; |
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uint8_t predecode; |
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int offset; |
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|
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/* (hit all banks and ways) */ |
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for (offset = 0; offset < 4; offset++) { |
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/* Index-load-data-I */ |
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__asm__ __volatile__ ( |
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" .set push\n\t" |
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" .set noreorder\n\t" |
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" .set mips64\n\t" |
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" .set noat\n\t" |
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" cache 6, 0(%3) \n\t" |
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" mfc0 %0, $29, 1\n\t" |
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" dmfc0 $1, $28, 1\n\t" |
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" dsrl32 %1, $1, 0 \n\t" |
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" sll %2, $1, 0 \n\t" |
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" .set pop \n" |
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: "=r" (datahi), "=r" (insta), "=r" (instb) |
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: "r" ((way << 13) | addr | (offset << 3))); |
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predecode = (datahi >> 8) & 0xff; |
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if (((datahi >> 16) & 1) != (uint32_t)range_parity(predecode, 7, 0)) { |
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printk(" ** bad parity in predecode\n"); |
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res |= CP0_CERRI_DATA_PARITY; |
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} |
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/* XXXKW should/could check predecode bits themselves */ |
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if (((datahi >> 4) & 0xf) ^ inst_parity(insta)) { |
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printk(" ** bad parity in instruction a\n"); |
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res |= CP0_CERRI_DATA_PARITY; |
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} |
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if ((datahi & 0xf) ^ inst_parity(instb)) { |
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printk(" ** bad parity in instruction b\n"); |
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res |= CP0_CERRI_DATA_PARITY; |
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} |
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printk(" %05X-%08X%08X", datahi, insta, instb); |
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} |
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printk("\n"); |
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} |
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} |
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return res; |
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} |
|
|
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/* Compute the ECC for a data doubleword */ |
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static uint8_t dc_ecc(uint64_t dword) |
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{ |
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uint64_t t; |
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uint32_t w; |
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uint8_t p; |
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int i; |
|
|
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p = 0; |
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for (i = 7; i >= 0; i--) |
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{ |
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p <<= 1; |
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t = dword & mask_72_64[i]; |
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w = (uint32_t)(t >> 32); |
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p ^= (parity[w>>24] ^ parity[(w>>16) & 0xFF] |
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^ parity[(w>>8) & 0xFF] ^ parity[w & 0xFF]); |
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w = (uint32_t)(t & 0xFFFFFFFF); |
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p ^= (parity[w>>24] ^ parity[(w>>16) & 0xFF] |
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^ parity[(w>>8) & 0xFF] ^ parity[w & 0xFF]); |
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} |
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return p; |
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} |
|
|
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struct dc_state { |
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unsigned char val; |
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char *name; |
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}; |
|
|
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static struct dc_state dc_states[] = { |
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{ 0x00, "INVALID" }, |
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{ 0x0f, "COH-SHD" }, |
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{ 0x13, "NCO-E-C" }, |
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{ 0x19, "NCO-E-D" }, |
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{ 0x16, "COH-E-C" }, |
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{ 0x1c, "COH-E-D" }, |
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{ 0xff, "*ERROR*" } |
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}; |
|
|
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#define DC_TAG_VALID(state) \ |
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(((state) == 0x0) || ((state) == 0xf) || ((state) == 0x13) || \ |
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((state) == 0x19) || ((state) == 0x16) || ((state) == 0x1c)) |
|
|
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static char *dc_state_str(unsigned char state) |
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{ |
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struct dc_state *dsc = dc_states; |
|
while (dsc->val != 0xff) { |
|
if (dsc->val == state) |
|
break; |
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dsc++; |
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} |
|
return dsc->name; |
|
} |
|
|
|
static uint32_t extract_dc(unsigned short addr, int data) |
|
{ |
|
int valid, way; |
|
unsigned char state; |
|
uint32_t taghi, taglolo, taglohi; |
|
unsigned long long taglo, pa; |
|
uint8_t ecc, lru; |
|
int res = 0; |
|
|
|
printk("Dcache index 0x%04x ", addr); |
|
for (way = 0; way < 4; way++) { |
|
__asm__ __volatile__ ( |
|
" .set push\n\t" |
|
" .set noreorder\n\t" |
|
" .set mips64\n\t" |
|
" .set noat\n\t" |
|
" cache 5, 0(%3)\n\t" /* Index-load-tag-D */ |
|
" mfc0 %0, $29, 2\n\t" |
|
" dmfc0 $1, $28, 2\n\t" |
|
" dsrl32 %1, $1, 0\n\t" |
|
" sll %2, $1, 0\n\t" |
|
" .set pop" |
|
: "=r" (taghi), "=r" (taglohi), "=r" (taglolo) |
|
: "r" ((way << 13) | addr)); |
|
|
|
taglo = ((unsigned long long)taglohi << 32) | taglolo; |
|
pa = (taglo & 0xFFFFFFE000ULL) | addr; |
|
if (way == 0) { |
|
lru = (taghi >> 14) & 0xff; |
|
printk("[Bank %d Set 0x%02x] LRU > %d %d %d %d > MRU\n", |
|
((addr >> 11) & 0x2) | ((addr >> 5) & 1), /* bank */ |
|
((addr >> 6) & 0x3f), /* index */ |
|
(lru & 0x3), |
|
((lru >> 2) & 0x3), |
|
((lru >> 4) & 0x3), |
|
((lru >> 6) & 0x3)); |
|
} |
|
state = (taghi >> 25) & 0x1f; |
|
valid = DC_TAG_VALID(state); |
|
printk(" %d [PA %010llx] [state %s (%02x)] raw tags: %08X-%016llX\n", |
|
way, pa, dc_state_str(state), state, taghi, taglo); |
|
if (valid) { |
|
if (((taglo >> 11) & 1) ^ range_parity(taglo, 39, 26)) { |
|
printk(" ** bad parity in PTag1\n"); |
|
res |= CP0_CERRD_TAG_ADDRESS; |
|
} |
|
if (((taglo >> 10) & 1) ^ range_parity(taglo, 25, 13)) { |
|
printk(" ** bad parity in PTag0\n"); |
|
res |= CP0_CERRD_TAG_ADDRESS; |
|
} |
|
} else { |
|
res |= CP0_CERRD_TAG_STATE; |
|
} |
|
|
|
if (data) { |
|
uint32_t datalohi, datalolo, datahi; |
|
unsigned long long datalo; |
|
int offset; |
|
char bad_ecc = 0; |
|
|
|
for (offset = 0; offset < 4; offset++) { |
|
/* Index-load-data-D */ |
|
__asm__ __volatile__ ( |
|
" .set push\n\t" |
|
" .set noreorder\n\t" |
|
" .set mips64\n\t" |
|
" .set noat\n\t" |
|
" cache 7, 0(%3)\n\t" /* Index-load-data-D */ |
|
" mfc0 %0, $29, 3\n\t" |
|
" dmfc0 $1, $28, 3\n\t" |
|
" dsrl32 %1, $1, 0 \n\t" |
|
" sll %2, $1, 0 \n\t" |
|
" .set pop" |
|
: "=r" (datahi), "=r" (datalohi), "=r" (datalolo) |
|
: "r" ((way << 13) | addr | (offset << 3))); |
|
datalo = ((unsigned long long)datalohi << 32) | datalolo; |
|
ecc = dc_ecc(datalo); |
|
if (ecc != datahi) { |
|
int bits; |
|
bad_ecc |= 1 << (3-offset); |
|
ecc ^= datahi; |
|
bits = hweight8(ecc); |
|
res |= (bits == 1) ? CP0_CERRD_DATA_SBE : CP0_CERRD_DATA_DBE; |
|
} |
|
printk(" %02X-%016llX", datahi, datalo); |
|
} |
|
printk("\n"); |
|
if (bad_ecc) |
|
printk(" dwords w/ bad ECC: %d %d %d %d\n", |
|
!!(bad_ecc & 8), !!(bad_ecc & 4), |
|
!!(bad_ecc & 2), !!(bad_ecc & 1)); |
|
} |
|
} |
|
return res; |
|
}
|
|
|