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278 lines
6.4 KiB
278 lines
6.4 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* IEEE754 floating point arithmetic |
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* single precision: MADDF.f (Fused Multiply Add) |
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* MADDF.fmt: FPR[fd] = FPR[fd] + (FPR[fs] x FPR[ft]) |
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* |
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* MIPS floating point support |
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* Copyright (C) 2015 Imagination Technologies, Ltd. |
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* Author: Markos Chandras <[email protected]> |
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*/ |
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#include "ieee754sp.h" |
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static union ieee754sp _sp_maddf(union ieee754sp z, union ieee754sp x, |
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union ieee754sp y, enum maddf_flags flags) |
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{ |
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int re; |
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int rs; |
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unsigned int rm; |
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u64 rm64; |
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u64 zm64; |
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int s; |
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COMPXSP; |
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COMPYSP; |
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COMPZSP; |
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EXPLODEXSP; |
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EXPLODEYSP; |
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EXPLODEZSP; |
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FLUSHXSP; |
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FLUSHYSP; |
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FLUSHZSP; |
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ieee754_clearcx(); |
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rs = xs ^ ys; |
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if (flags & MADDF_NEGATE_PRODUCT) |
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rs ^= 1; |
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if (flags & MADDF_NEGATE_ADDITION) |
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zs ^= 1; |
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/* |
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* Handle the cases when at least one of x, y or z is a NaN. |
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* Order of precedence is sNaN, qNaN and z, x, y. |
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*/ |
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if (zc == IEEE754_CLASS_SNAN) |
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return ieee754sp_nanxcpt(z); |
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if (xc == IEEE754_CLASS_SNAN) |
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return ieee754sp_nanxcpt(x); |
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if (yc == IEEE754_CLASS_SNAN) |
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return ieee754sp_nanxcpt(y); |
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if (zc == IEEE754_CLASS_QNAN) |
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return z; |
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if (xc == IEEE754_CLASS_QNAN) |
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return x; |
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if (yc == IEEE754_CLASS_QNAN) |
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return y; |
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if (zc == IEEE754_CLASS_DNORM) |
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SPDNORMZ; |
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/* ZERO z cases are handled separately below */ |
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switch (CLPAIR(xc, yc)) { |
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/* |
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* Infinity handling |
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*/ |
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO): |
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF): |
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ieee754_setcx(IEEE754_INVALID_OPERATION); |
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return ieee754sp_indef(); |
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF): |
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF): |
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM): |
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM): |
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF): |
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if ((zc == IEEE754_CLASS_INF) && (zs != rs)) { |
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/* |
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* Cases of addition of infinities with opposite signs |
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* or subtraction of infinities with same signs. |
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*/ |
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ieee754_setcx(IEEE754_INVALID_OPERATION); |
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return ieee754sp_indef(); |
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} |
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/* |
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* z is here either not an infinity, or an infinity having the |
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* same sign as product (x*y). The result must be an infinity, |
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* and its sign is determined only by the sign of product (x*y). |
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*/ |
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return ieee754sp_inf(rs); |
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO): |
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM): |
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM): |
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO): |
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO): |
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if (zc == IEEE754_CLASS_INF) |
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return ieee754sp_inf(zs); |
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if (zc == IEEE754_CLASS_ZERO) { |
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/* Handle cases +0 + (-0) and similar ones. */ |
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if (zs == rs) |
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/* |
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* Cases of addition of zeros of equal signs |
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* or subtraction of zeroes of opposite signs. |
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* The sign of the resulting zero is in any |
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* such case determined only by the sign of z. |
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*/ |
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return z; |
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return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD); |
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} |
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/* x*y is here 0, and z is not 0, so just return z */ |
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return z; |
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM): |
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SPDNORMX; |
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fallthrough; |
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM): |
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if (zc == IEEE754_CLASS_INF) |
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return ieee754sp_inf(zs); |
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SPDNORMY; |
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break; |
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM): |
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if (zc == IEEE754_CLASS_INF) |
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return ieee754sp_inf(zs); |
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SPDNORMX; |
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break; |
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM): |
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if (zc == IEEE754_CLASS_INF) |
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return ieee754sp_inf(zs); |
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/* continue to real computations */ |
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} |
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/* Finally get to do some computation */ |
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/* |
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* Do the multiplication bit first |
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* |
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* rm = xm * ym, re = xe + ye basically |
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* |
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* At this point xm and ym should have been normalized. |
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*/ |
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/* rm = xm * ym, re = xe+ye basically */ |
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assert(xm & SP_HIDDEN_BIT); |
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assert(ym & SP_HIDDEN_BIT); |
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re = xe + ye; |
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/* Multiple 24 bit xm and ym to give 48 bit results */ |
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rm64 = (uint64_t)xm * ym; |
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/* Shunt to top of word */ |
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rm64 = rm64 << 16; |
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/* Put explicit bit at bit 62 if necessary */ |
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if ((int64_t) rm64 < 0) { |
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rm64 = rm64 >> 1; |
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re++; |
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} |
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assert(rm64 & (1 << 62)); |
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if (zc == IEEE754_CLASS_ZERO) { |
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/* |
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* Move explicit bit from bit 62 to bit 26 since the |
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* ieee754sp_format code expects the mantissa to be |
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* 27 bits wide (24 + 3 rounding bits). |
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*/ |
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rm = XSPSRS64(rm64, (62 - 26)); |
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return ieee754sp_format(rs, re, rm); |
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} |
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/* Move explicit bit from bit 23 to bit 62 */ |
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zm64 = (uint64_t)zm << (62 - 23); |
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assert(zm64 & (1 << 62)); |
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/* Make the exponents the same */ |
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if (ze > re) { |
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/* |
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* Have to shift r fraction right to align. |
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*/ |
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s = ze - re; |
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rm64 = XSPSRS64(rm64, s); |
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re += s; |
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} else if (re > ze) { |
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/* |
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* Have to shift z fraction right to align. |
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*/ |
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s = re - ze; |
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zm64 = XSPSRS64(zm64, s); |
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ze += s; |
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} |
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assert(ze == re); |
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assert(ze <= SP_EMAX); |
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/* Do the addition */ |
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if (zs == rs) { |
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/* |
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* Generate 64 bit result by adding two 63 bit numbers |
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* leaving result in zm64, zs and ze. |
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*/ |
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zm64 = zm64 + rm64; |
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if ((int64_t)zm64 < 0) { /* carry out */ |
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zm64 = XSPSRS1(zm64); |
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ze++; |
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} |
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} else { |
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if (zm64 >= rm64) { |
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zm64 = zm64 - rm64; |
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} else { |
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zm64 = rm64 - zm64; |
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zs = rs; |
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} |
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if (zm64 == 0) |
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return ieee754sp_zero(ieee754_csr.rm == FPU_CSR_RD); |
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/* |
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* Put explicit bit at bit 62 if necessary. |
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*/ |
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while ((zm64 >> 62) == 0) { |
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zm64 <<= 1; |
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ze--; |
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} |
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} |
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/* |
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* Move explicit bit from bit 62 to bit 26 since the |
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* ieee754sp_format code expects the mantissa to be |
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* 27 bits wide (24 + 3 rounding bits). |
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*/ |
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zm = XSPSRS64(zm64, (62 - 26)); |
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return ieee754sp_format(zs, ze, zm); |
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} |
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union ieee754sp ieee754sp_maddf(union ieee754sp z, union ieee754sp x, |
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union ieee754sp y) |
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{ |
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return _sp_maddf(z, x, y, 0); |
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} |
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union ieee754sp ieee754sp_msubf(union ieee754sp z, union ieee754sp x, |
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union ieee754sp y) |
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{ |
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return _sp_maddf(z, x, y, MADDF_NEGATE_PRODUCT); |
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} |
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union ieee754sp ieee754sp_madd(union ieee754sp z, union ieee754sp x, |
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union ieee754sp y) |
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{ |
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return _sp_maddf(z, x, y, 0); |
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} |
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union ieee754sp ieee754sp_msub(union ieee754sp z, union ieee754sp x, |
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union ieee754sp y) |
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{ |
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return _sp_maddf(z, x, y, MADDF_NEGATE_ADDITION); |
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} |
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union ieee754sp ieee754sp_nmadd(union ieee754sp z, union ieee754sp x, |
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union ieee754sp y) |
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{ |
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return _sp_maddf(z, x, y, MADDF_NEGATE_PRODUCT|MADDF_NEGATE_ADDITION); |
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} |
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union ieee754sp ieee754sp_nmsub(union ieee754sp z, union ieee754sp x, |
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union ieee754sp y) |
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{ |
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return _sp_maddf(z, x, y, MADDF_NEGATE_PRODUCT); |
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}
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