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232 lines
6.1 KiB
232 lines
6.1 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (c) 2014 Zhang, Keguang <[email protected]> |
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*/ |
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#include <linux/clk.h> |
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#include <linux/interrupt.h> |
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#include <linux/sizes.h> |
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#include <asm/time.h> |
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#include <loongson1.h> |
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#include <platform.h> |
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#ifdef CONFIG_CEVT_CSRC_LS1X |
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#if defined(CONFIG_TIMER_USE_PWM1) |
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#define LS1X_TIMER_BASE LS1X_PWM1_BASE |
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#define LS1X_TIMER_IRQ LS1X_PWM1_IRQ |
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#elif defined(CONFIG_TIMER_USE_PWM2) |
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#define LS1X_TIMER_BASE LS1X_PWM2_BASE |
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#define LS1X_TIMER_IRQ LS1X_PWM2_IRQ |
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#elif defined(CONFIG_TIMER_USE_PWM3) |
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#define LS1X_TIMER_BASE LS1X_PWM3_BASE |
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#define LS1X_TIMER_IRQ LS1X_PWM3_IRQ |
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#else |
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#define LS1X_TIMER_BASE LS1X_PWM0_BASE |
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#define LS1X_TIMER_IRQ LS1X_PWM0_IRQ |
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#endif |
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DEFINE_RAW_SPINLOCK(ls1x_timer_lock); |
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static void __iomem *timer_reg_base; |
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static uint32_t ls1x_jiffies_per_tick; |
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static inline void ls1x_pwmtimer_set_period(uint32_t period) |
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{ |
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__raw_writel(period, timer_reg_base + PWM_HRC); |
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__raw_writel(period, timer_reg_base + PWM_LRC); |
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} |
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static inline void ls1x_pwmtimer_restart(void) |
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{ |
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__raw_writel(0x0, timer_reg_base + PWM_CNT); |
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__raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL); |
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} |
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void __init ls1x_pwmtimer_init(void) |
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{ |
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timer_reg_base = ioremap(LS1X_TIMER_BASE, SZ_16); |
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if (!timer_reg_base) |
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panic("Failed to remap timer registers"); |
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ls1x_jiffies_per_tick = DIV_ROUND_CLOSEST(mips_hpt_frequency, HZ); |
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ls1x_pwmtimer_set_period(ls1x_jiffies_per_tick); |
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ls1x_pwmtimer_restart(); |
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} |
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static u64 ls1x_clocksource_read(struct clocksource *cs) |
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{ |
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unsigned long flags; |
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int count; |
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u32 jifs; |
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static int old_count; |
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static u32 old_jifs; |
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raw_spin_lock_irqsave(&ls1x_timer_lock, flags); |
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/* |
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* Although our caller may have the read side of xtime_lock, |
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* this is now a seqlock, and we are cheating in this routine |
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* by having side effects on state that we cannot undo if |
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* there is a collision on the seqlock and our caller has to |
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* retry. (Namely, old_jifs and old_count.) So we must treat |
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* jiffies as volatile despite the lock. We read jiffies |
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* before latching the timer count to guarantee that although |
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* the jiffies value might be older than the count (that is, |
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* the counter may underflow between the last point where |
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* jiffies was incremented and the point where we latch the |
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* count), it cannot be newer. |
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*/ |
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jifs = jiffies; |
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/* read the count */ |
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count = __raw_readl(timer_reg_base + PWM_CNT); |
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/* |
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* It's possible for count to appear to go the wrong way for this |
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* reason: |
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* |
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* The timer counter underflows, but we haven't handled the resulting |
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* interrupt and incremented jiffies yet. |
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* |
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* Previous attempts to handle these cases intelligently were buggy, so |
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* we just do the simple thing now. |
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*/ |
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if (count < old_count && jifs == old_jifs) |
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count = old_count; |
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old_count = count; |
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old_jifs = jifs; |
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raw_spin_unlock_irqrestore(&ls1x_timer_lock, flags); |
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return (u64) (jifs * ls1x_jiffies_per_tick) + count; |
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} |
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static struct clocksource ls1x_clocksource = { |
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.name = "ls1x-pwmtimer", |
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.read = ls1x_clocksource_read, |
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.mask = CLOCKSOURCE_MASK(24), |
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.flags = CLOCK_SOURCE_IS_CONTINUOUS, |
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}; |
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static irqreturn_t ls1x_clockevent_isr(int irq, void *devid) |
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{ |
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struct clock_event_device *cd = devid; |
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ls1x_pwmtimer_restart(); |
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cd->event_handler(cd); |
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return IRQ_HANDLED; |
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} |
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static int ls1x_clockevent_set_state_periodic(struct clock_event_device *cd) |
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{ |
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raw_spin_lock(&ls1x_timer_lock); |
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ls1x_pwmtimer_set_period(ls1x_jiffies_per_tick); |
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ls1x_pwmtimer_restart(); |
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__raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL); |
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raw_spin_unlock(&ls1x_timer_lock); |
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return 0; |
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} |
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static int ls1x_clockevent_tick_resume(struct clock_event_device *cd) |
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{ |
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raw_spin_lock(&ls1x_timer_lock); |
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__raw_writel(INT_EN | CNT_EN, timer_reg_base + PWM_CTRL); |
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raw_spin_unlock(&ls1x_timer_lock); |
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return 0; |
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} |
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static int ls1x_clockevent_set_state_shutdown(struct clock_event_device *cd) |
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{ |
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raw_spin_lock(&ls1x_timer_lock); |
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__raw_writel(__raw_readl(timer_reg_base + PWM_CTRL) & ~CNT_EN, |
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timer_reg_base + PWM_CTRL); |
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raw_spin_unlock(&ls1x_timer_lock); |
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return 0; |
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} |
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static int ls1x_clockevent_set_next(unsigned long evt, |
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struct clock_event_device *cd) |
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{ |
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raw_spin_lock(&ls1x_timer_lock); |
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ls1x_pwmtimer_set_period(evt); |
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ls1x_pwmtimer_restart(); |
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raw_spin_unlock(&ls1x_timer_lock); |
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return 0; |
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} |
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static struct clock_event_device ls1x_clockevent = { |
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.name = "ls1x-pwmtimer", |
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.features = CLOCK_EVT_FEAT_PERIODIC, |
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.rating = 300, |
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.irq = LS1X_TIMER_IRQ, |
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.set_next_event = ls1x_clockevent_set_next, |
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.set_state_shutdown = ls1x_clockevent_set_state_shutdown, |
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.set_state_periodic = ls1x_clockevent_set_state_periodic, |
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.set_state_oneshot = ls1x_clockevent_set_state_shutdown, |
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.tick_resume = ls1x_clockevent_tick_resume, |
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}; |
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static void __init ls1x_time_init(void) |
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{ |
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struct clock_event_device *cd = &ls1x_clockevent; |
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int ret; |
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if (!mips_hpt_frequency) |
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panic("Invalid timer clock rate"); |
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ls1x_pwmtimer_init(); |
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clockevent_set_clock(cd, mips_hpt_frequency); |
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cd->max_delta_ns = clockevent_delta2ns(0xffffff, cd); |
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cd->max_delta_ticks = 0xffffff; |
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cd->min_delta_ns = clockevent_delta2ns(0x000300, cd); |
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cd->min_delta_ticks = 0x000300; |
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cd->cpumask = cpumask_of(smp_processor_id()); |
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clockevents_register_device(cd); |
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ls1x_clocksource.rating = 200 + mips_hpt_frequency / 10000000; |
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ret = clocksource_register_hz(&ls1x_clocksource, mips_hpt_frequency); |
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if (ret) |
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panic(KERN_ERR "Failed to register clocksource: %d\n", ret); |
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if (request_irq(LS1X_TIMER_IRQ, ls1x_clockevent_isr, |
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IRQF_PERCPU | IRQF_TIMER, "ls1x-pwmtimer", |
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&ls1x_clockevent)) |
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pr_err("Failed to register ls1x-pwmtimer interrupt\n"); |
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} |
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#endif /* CONFIG_CEVT_CSRC_LS1X */ |
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void __init plat_time_init(void) |
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{ |
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struct clk *clk = NULL; |
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/* initialize LS1X clocks */ |
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ls1x_clk_init(); |
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#ifdef CONFIG_CEVT_CSRC_LS1X |
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/* setup LS1X PWM timer */ |
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clk = clk_get(NULL, "ls1x-pwmtimer"); |
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if (IS_ERR(clk)) |
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panic("unable to get timer clock, err=%ld", PTR_ERR(clk)); |
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mips_hpt_frequency = clk_get_rate(clk); |
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ls1x_time_init(); |
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#else |
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/* setup mips r4k timer */ |
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clk = clk_get(NULL, "cpu_clk"); |
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if (IS_ERR(clk)) |
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panic("unable to get cpu clock, err=%ld", PTR_ERR(clk)); |
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mips_hpt_frequency = clk_get_rate(clk) / 2; |
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#endif /* CONFIG_CEVT_CSRC_LS1X */ |
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}
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