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143 lines
4.0 KiB
143 lines
4.0 KiB
/* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* KVM/MIPS: Binary Patching for privileged instructions, reduces traps. |
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* |
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved. |
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* Authors: Sanjay Lal <[email protected]> |
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*/ |
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#include <linux/errno.h> |
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#include <linux/err.h> |
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#include <linux/highmem.h> |
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#include <linux/kvm_host.h> |
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#include <linux/uaccess.h> |
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#include <linux/vmalloc.h> |
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#include <linux/fs.h> |
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#include <linux/memblock.h> |
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#include <asm/cacheflush.h> |
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#include "commpage.h" |
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/** |
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* kvm_mips_trans_replace() - Replace trapping instruction in guest memory. |
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* @vcpu: Virtual CPU. |
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* @opc: PC of instruction to replace. |
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* @replace: Instruction to write |
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*/ |
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static int kvm_mips_trans_replace(struct kvm_vcpu *vcpu, u32 *opc, |
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union mips_instruction replace) |
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{ |
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unsigned long vaddr = (unsigned long)opc; |
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int err; |
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retry: |
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/* The GVA page table is still active so use the Linux TLB handlers */ |
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kvm_trap_emul_gva_lockless_begin(vcpu); |
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err = put_user(replace.word, opc); |
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kvm_trap_emul_gva_lockless_end(vcpu); |
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if (unlikely(err)) { |
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/* |
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* We write protect clean pages in GVA page table so normal |
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* Linux TLB mod handler doesn't silently dirty the page. |
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* Its also possible we raced with a GVA invalidation. |
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* Try to force the page to become dirty. |
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*/ |
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err = kvm_trap_emul_gva_fault(vcpu, vaddr, true); |
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if (unlikely(err)) { |
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kvm_info("%s: Address unwriteable: %p\n", |
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__func__, opc); |
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return -EFAULT; |
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} |
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/* |
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* Try again. This will likely trigger a TLB refill, which will |
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* fetch the new dirty entry from the GVA page table, which |
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* should then succeed. |
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*/ |
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goto retry; |
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} |
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__local_flush_icache_user_range(vaddr, vaddr + 4); |
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return 0; |
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} |
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int kvm_mips_trans_cache_index(union mips_instruction inst, u32 *opc, |
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struct kvm_vcpu *vcpu) |
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{ |
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union mips_instruction nop_inst = { 0 }; |
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/* Replace the CACHE instruction, with a NOP */ |
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return kvm_mips_trans_replace(vcpu, opc, nop_inst); |
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} |
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/* |
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* Address based CACHE instructions are transformed into synci(s). A little |
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* heavy for just D-cache invalidates, but avoids an expensive trap |
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*/ |
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int kvm_mips_trans_cache_va(union mips_instruction inst, u32 *opc, |
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struct kvm_vcpu *vcpu) |
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{ |
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union mips_instruction synci_inst = { 0 }; |
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synci_inst.i_format.opcode = bcond_op; |
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synci_inst.i_format.rs = inst.i_format.rs; |
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synci_inst.i_format.rt = synci_op; |
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if (cpu_has_mips_r6) |
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synci_inst.i_format.simmediate = inst.spec3_format.simmediate; |
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else |
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synci_inst.i_format.simmediate = inst.i_format.simmediate; |
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return kvm_mips_trans_replace(vcpu, opc, synci_inst); |
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} |
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int kvm_mips_trans_mfc0(union mips_instruction inst, u32 *opc, |
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struct kvm_vcpu *vcpu) |
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{ |
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union mips_instruction mfc0_inst = { 0 }; |
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u32 rd, sel; |
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rd = inst.c0r_format.rd; |
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sel = inst.c0r_format.sel; |
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if (rd == MIPS_CP0_ERRCTL && sel == 0) { |
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mfc0_inst.r_format.opcode = spec_op; |
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mfc0_inst.r_format.rd = inst.c0r_format.rt; |
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mfc0_inst.r_format.func = add_op; |
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} else { |
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mfc0_inst.i_format.opcode = lw_op; |
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mfc0_inst.i_format.rt = inst.c0r_format.rt; |
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mfc0_inst.i_format.simmediate = KVM_GUEST_COMMPAGE_ADDR | |
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offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]); |
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#ifdef CONFIG_CPU_BIG_ENDIAN |
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if (sizeof(vcpu->arch.cop0->reg[0][0]) == 8) |
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mfc0_inst.i_format.simmediate |= 4; |
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#endif |
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} |
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return kvm_mips_trans_replace(vcpu, opc, mfc0_inst); |
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} |
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int kvm_mips_trans_mtc0(union mips_instruction inst, u32 *opc, |
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struct kvm_vcpu *vcpu) |
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{ |
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union mips_instruction mtc0_inst = { 0 }; |
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u32 rd, sel; |
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rd = inst.c0r_format.rd; |
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sel = inst.c0r_format.sel; |
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mtc0_inst.i_format.opcode = sw_op; |
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mtc0_inst.i_format.rt = inst.c0r_format.rt; |
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mtc0_inst.i_format.simmediate = KVM_GUEST_COMMPAGE_ADDR | |
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offsetof(struct kvm_mips_commpage, cop0.reg[rd][sel]); |
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#ifdef CONFIG_CPU_BIG_ENDIAN |
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if (sizeof(vcpu->arch.cop0->reg[0][0]) == 8) |
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mtc0_inst.i_format.simmediate |= 4; |
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#endif |
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return kvm_mips_trans_replace(vcpu, opc, mtc0_inst); |
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}
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