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193 lines
5.7 KiB
193 lines
5.7 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 1995, 1996, 2001 Ralf Baechle |
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* Copyright (C) 2001, 2004 MIPS Technologies, Inc. |
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* Copyright (C) 2004 Maciej W. Rozycki |
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*/ |
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#include <linux/delay.h> |
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#include <linux/kernel.h> |
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#include <linux/sched.h> |
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#include <linux/seq_file.h> |
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#include <asm/bootinfo.h> |
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#include <asm/cpu.h> |
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#include <asm/cpu-features.h> |
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#include <asm/idle.h> |
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#include <asm/mipsregs.h> |
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#include <asm/processor.h> |
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#include <asm/prom.h> |
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unsigned int vced_count, vcei_count; |
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/* |
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* * No lock; only written during early bootup by CPU 0. |
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* */ |
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static RAW_NOTIFIER_HEAD(proc_cpuinfo_chain); |
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int __ref register_proc_cpuinfo_notifier(struct notifier_block *nb) |
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{ |
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return raw_notifier_chain_register(&proc_cpuinfo_chain, nb); |
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} |
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int proc_cpuinfo_notifier_call_chain(unsigned long val, void *v) |
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{ |
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return raw_notifier_call_chain(&proc_cpuinfo_chain, val, v); |
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} |
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static int show_cpuinfo(struct seq_file *m, void *v) |
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{ |
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struct proc_cpuinfo_notifier_args proc_cpuinfo_notifier_args; |
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unsigned long n = (unsigned long) v - 1; |
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unsigned int version = cpu_data[n].processor_id; |
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unsigned int fp_vers = cpu_data[n].fpu_id; |
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char fmt [64]; |
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int i; |
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#ifdef CONFIG_SMP |
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if (!cpu_online(n)) |
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return 0; |
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#endif |
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/* |
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* For the first processor also print the system type |
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*/ |
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if (n == 0) { |
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seq_printf(m, "system type\t\t: %s\n", get_system_type()); |
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if (mips_get_machine_name()) |
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seq_printf(m, "machine\t\t\t: %s\n", |
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mips_get_machine_name()); |
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} |
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seq_printf(m, "processor\t\t: %ld\n", n); |
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sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", |
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cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : ""); |
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seq_printf(m, fmt, __cpu_name[n], |
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(version >> 4) & 0x0f, version & 0x0f, |
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(fp_vers >> 4) & 0x0f, fp_vers & 0x0f); |
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seq_printf(m, "BogoMIPS\t\t: %u.%02u\n", |
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cpu_data[n].udelay_val / (500000/HZ), |
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(cpu_data[n].udelay_val / (5000/HZ)) % 100); |
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seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no"); |
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seq_printf(m, "microsecond timers\t: %s\n", |
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cpu_has_counter ? "yes" : "no"); |
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seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize); |
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seq_printf(m, "extra interrupt vector\t: %s\n", |
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cpu_has_divec ? "yes" : "no"); |
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seq_printf(m, "hardware watchpoint\t: %s", |
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cpu_has_watch ? "yes, " : "no\n"); |
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if (cpu_has_watch) { |
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seq_printf(m, "count: %d, address/irw mask: [", |
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cpu_data[n].watch_reg_count); |
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for (i = 0; i < cpu_data[n].watch_reg_count; i++) |
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seq_printf(m, "%s0x%04x", i ? ", " : "" , |
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cpu_data[n].watch_reg_masks[i]); |
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seq_printf(m, "]\n"); |
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} |
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seq_printf(m, "isa\t\t\t:"); |
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if (cpu_has_mips_1) |
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seq_printf(m, " mips1"); |
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if (cpu_has_mips_2) |
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seq_printf(m, "%s", " mips2"); |
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if (cpu_has_mips_3) |
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seq_printf(m, "%s", " mips3"); |
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if (cpu_has_mips_4) |
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seq_printf(m, "%s", " mips4"); |
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if (cpu_has_mips_5) |
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seq_printf(m, "%s", " mips5"); |
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if (cpu_has_mips32r1) |
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seq_printf(m, "%s", " mips32r1"); |
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if (cpu_has_mips32r2) |
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seq_printf(m, "%s", " mips32r2"); |
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if (cpu_has_mips32r5) |
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seq_printf(m, "%s", " mips32r5"); |
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if (cpu_has_mips32r6) |
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seq_printf(m, "%s", " mips32r6"); |
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if (cpu_has_mips64r1) |
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seq_printf(m, "%s", " mips64r1"); |
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if (cpu_has_mips64r2) |
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seq_printf(m, "%s", " mips64r2"); |
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if (cpu_has_mips64r5) |
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seq_printf(m, "%s", " mips64r5"); |
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if (cpu_has_mips64r6) |
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seq_printf(m, "%s", " mips64r6"); |
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seq_printf(m, "\n"); |
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seq_printf(m, "ASEs implemented\t:"); |
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if (cpu_has_mips16) seq_printf(m, "%s", " mips16"); |
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if (cpu_has_mips16e2) seq_printf(m, "%s", " mips16e2"); |
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if (cpu_has_mdmx) seq_printf(m, "%s", " mdmx"); |
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if (cpu_has_mips3d) seq_printf(m, "%s", " mips3d"); |
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if (cpu_has_smartmips) seq_printf(m, "%s", " smartmips"); |
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if (cpu_has_dsp) seq_printf(m, "%s", " dsp"); |
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if (cpu_has_dsp2) seq_printf(m, "%s", " dsp2"); |
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if (cpu_has_dsp3) seq_printf(m, "%s", " dsp3"); |
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if (cpu_has_mipsmt) seq_printf(m, "%s", " mt"); |
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if (cpu_has_mmips) seq_printf(m, "%s", " micromips"); |
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if (cpu_has_vz) seq_printf(m, "%s", " vz"); |
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if (cpu_has_msa) seq_printf(m, "%s", " msa"); |
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if (cpu_has_eva) seq_printf(m, "%s", " eva"); |
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if (cpu_has_htw) seq_printf(m, "%s", " htw"); |
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if (cpu_has_xpa) seq_printf(m, "%s", " xpa"); |
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if (cpu_has_loongson_mmi) seq_printf(m, "%s", " loongson-mmi"); |
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if (cpu_has_loongson_cam) seq_printf(m, "%s", " loongson-cam"); |
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if (cpu_has_loongson_ext) seq_printf(m, "%s", " loongson-ext"); |
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if (cpu_has_loongson_ext2) seq_printf(m, "%s", " loongson-ext2"); |
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seq_printf(m, "\n"); |
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if (cpu_has_mmips) { |
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seq_printf(m, "micromips kernel\t: %s\n", |
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(read_c0_config3() & MIPS_CONF3_ISA_OE) ? "yes" : "no"); |
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} |
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seq_printf(m, "shadow register sets\t: %d\n", |
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cpu_data[n].srsets); |
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seq_printf(m, "kscratch registers\t: %d\n", |
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hweight8(cpu_data[n].kscratch_mask)); |
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seq_printf(m, "package\t\t\t: %d\n", cpu_data[n].package); |
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seq_printf(m, "core\t\t\t: %d\n", cpu_core(&cpu_data[n])); |
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#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6) |
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if (cpu_has_mipsmt) |
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seq_printf(m, "VPE\t\t\t: %d\n", cpu_vpe_id(&cpu_data[n])); |
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else if (cpu_has_vp) |
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seq_printf(m, "VP\t\t\t: %d\n", cpu_vpe_id(&cpu_data[n])); |
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#endif |
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sprintf(fmt, "VCE%%c exceptions\t\t: %s\n", |
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cpu_has_vce ? "%u" : "not available"); |
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seq_printf(m, fmt, 'D', vced_count); |
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seq_printf(m, fmt, 'I', vcei_count); |
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proc_cpuinfo_notifier_args.m = m; |
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proc_cpuinfo_notifier_args.n = n; |
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raw_notifier_call_chain(&proc_cpuinfo_chain, 0, |
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&proc_cpuinfo_notifier_args); |
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seq_printf(m, "\n"); |
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return 0; |
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} |
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static void *c_start(struct seq_file *m, loff_t *pos) |
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{ |
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unsigned long i = *pos; |
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return i < NR_CPUS ? (void *) (i + 1) : NULL; |
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} |
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static void *c_next(struct seq_file *m, void *v, loff_t *pos) |
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{ |
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++*pos; |
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return c_start(m, pos); |
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} |
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static void c_stop(struct seq_file *m, void *v) |
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{ |
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} |
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const struct seq_operations cpuinfo_op = { |
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.start = c_start, |
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.next = c_next, |
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.stop = c_stop, |
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.show = show_cpuinfo, |
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};
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