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682 lines
14 KiB
682 lines
14 KiB
/* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle |
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc. |
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* Copyright (C) 2002, 2007 Maciej W. Rozycki |
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* Copyright (C) 2001, 2012 MIPS Technologies, Inc. All rights reserved. |
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*/ |
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#include <linux/init.h> |
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|
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#include <asm/asm.h> |
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#include <asm/asmmacro.h> |
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#include <asm/cacheops.h> |
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#include <asm/irqflags.h> |
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#include <asm/regdef.h> |
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#include <asm/fpregdef.h> |
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#include <asm/mipsregs.h> |
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#include <asm/stackframe.h> |
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#include <asm/sync.h> |
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#include <asm/war.h> |
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#include <asm/thread_info.h> |
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__INIT |
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|
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/* |
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* General exception vector for all other CPUs. |
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* |
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* Be careful when changing this, it has to be at most 128 bytes |
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* to fit into space reserved for the exception handler. |
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*/ |
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NESTED(except_vec3_generic, 0, sp) |
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.set push |
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.set noat |
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mfc0 k1, CP0_CAUSE |
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andi k1, k1, 0x7c |
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#ifdef CONFIG_64BIT |
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dsll k1, k1, 1 |
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#endif |
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PTR_L k0, exception_handlers(k1) |
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jr k0 |
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.set pop |
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END(except_vec3_generic) |
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|
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/* |
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* General exception handler for CPUs with virtual coherency exception. |
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* |
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* Be careful when changing this, it has to be at most 256 (as a special |
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* exception) bytes to fit into space reserved for the exception handler. |
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*/ |
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NESTED(except_vec3_r4000, 0, sp) |
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.set push |
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.set arch=r4000 |
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.set noat |
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mfc0 k1, CP0_CAUSE |
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li k0, 31<<2 |
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andi k1, k1, 0x7c |
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.set push |
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.set noreorder |
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.set nomacro |
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beq k1, k0, handle_vced |
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li k0, 14<<2 |
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beq k1, k0, handle_vcei |
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#ifdef CONFIG_64BIT |
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dsll k1, k1, 1 |
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#endif |
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.set pop |
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PTR_L k0, exception_handlers(k1) |
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jr k0 |
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/* |
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* Big shit, we now may have two dirty primary cache lines for the same |
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* physical address. We can safely invalidate the line pointed to by |
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* c0_badvaddr because after return from this exception handler the |
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* load / store will be re-executed. |
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*/ |
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handle_vced: |
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MFC0 k0, CP0_BADVADDR |
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li k1, -4 # Is this ... |
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and k0, k1 # ... really needed? |
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mtc0 zero, CP0_TAGLO |
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cache Index_Store_Tag_D, (k0) |
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cache Hit_Writeback_Inv_SD, (k0) |
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#ifdef CONFIG_PROC_FS |
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PTR_LA k0, vced_count |
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lw k1, (k0) |
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addiu k1, 1 |
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sw k1, (k0) |
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#endif |
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eret |
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handle_vcei: |
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MFC0 k0, CP0_BADVADDR |
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cache Hit_Writeback_Inv_SD, (k0) # also cleans pi |
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#ifdef CONFIG_PROC_FS |
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PTR_LA k0, vcei_count |
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lw k1, (k0) |
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addiu k1, 1 |
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sw k1, (k0) |
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#endif |
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eret |
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.set pop |
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END(except_vec3_r4000) |
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__FINIT |
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.align 5 /* 32 byte rollback region */ |
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LEAF(__r4k_wait) |
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.set push |
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.set noreorder |
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/* start of rollback region */ |
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LONG_L t0, TI_FLAGS($28) |
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nop |
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andi t0, _TIF_NEED_RESCHED |
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bnez t0, 1f |
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nop |
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nop |
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nop |
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#ifdef CONFIG_CPU_MICROMIPS |
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nop |
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nop |
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nop |
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nop |
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#endif |
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.set MIPS_ISA_ARCH_LEVEL_RAW |
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wait |
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/* end of rollback region (the region size must be power of two) */ |
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1: |
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jr ra |
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nop |
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.set pop |
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END(__r4k_wait) |
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.macro BUILD_ROLLBACK_PROLOGUE handler |
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FEXPORT(rollback_\handler) |
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.set push |
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.set noat |
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MFC0 k0, CP0_EPC |
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PTR_LA k1, __r4k_wait |
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ori k0, 0x1f /* 32 byte rollback region */ |
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xori k0, 0x1f |
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bne k0, k1, \handler |
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MTC0 k0, CP0_EPC |
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.set pop |
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.endm |
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.align 5 |
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BUILD_ROLLBACK_PROLOGUE handle_int |
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NESTED(handle_int, PT_SIZE, sp) |
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.cfi_signal_frame |
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#ifdef CONFIG_TRACE_IRQFLAGS |
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/* |
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* Check to see if the interrupted code has just disabled |
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* interrupts and ignore this interrupt for now if so. |
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* |
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* local_irq_disable() disables interrupts and then calls |
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* trace_hardirqs_off() to track the state. If an interrupt is taken |
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* after interrupts are disabled but before the state is updated |
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* it will appear to restore_all that it is incorrectly returning with |
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* interrupts disabled |
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*/ |
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.set push |
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.set noat |
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mfc0 k0, CP0_STATUS |
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) |
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and k0, ST0_IEP |
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bnez k0, 1f |
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mfc0 k0, CP0_EPC |
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.set noreorder |
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j k0 |
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rfe |
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#else |
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and k0, ST0_IE |
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bnez k0, 1f |
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eret |
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#endif |
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1: |
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.set pop |
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#endif |
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SAVE_ALL docfi=1 |
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CLI |
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TRACE_IRQS_OFF |
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LONG_L s0, TI_REGS($28) |
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LONG_S sp, TI_REGS($28) |
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/* |
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* SAVE_ALL ensures we are using a valid kernel stack for the thread. |
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* Check if we are already using the IRQ stack. |
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*/ |
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move s1, sp # Preserve the sp |
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|
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/* Get IRQ stack for this CPU */ |
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ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG |
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#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) |
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lui k1, %hi(irq_stack) |
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#else |
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lui k1, %highest(irq_stack) |
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daddiu k1, %higher(irq_stack) |
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dsll k1, 16 |
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daddiu k1, %hi(irq_stack) |
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dsll k1, 16 |
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#endif |
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LONG_SRL k0, SMP_CPUID_PTRSHIFT |
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LONG_ADDU k1, k0 |
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LONG_L t0, %lo(irq_stack)(k1) |
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# Check if already on IRQ stack |
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PTR_LI t1, ~(_THREAD_SIZE-1) |
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and t1, t1, sp |
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beq t0, t1, 2f |
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/* Switch to IRQ stack */ |
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li t1, _IRQ_STACK_START |
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PTR_ADD sp, t0, t1 |
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/* Save task's sp on IRQ stack so that unwinding can follow it */ |
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LONG_S s1, 0(sp) |
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2: |
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jal plat_irq_dispatch |
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/* Restore sp */ |
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move sp, s1 |
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j ret_from_irq |
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#ifdef CONFIG_CPU_MICROMIPS |
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nop |
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#endif |
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END(handle_int) |
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__INIT |
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/* |
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* Special interrupt vector for MIPS64 ISA & embedded MIPS processors. |
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* This is a dedicated interrupt exception vector which reduces the |
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* interrupt processing overhead. The jump instruction will be replaced |
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* at the initialization time. |
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* |
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* Be careful when changing this, it has to be at most 128 bytes |
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* to fit into space reserved for the exception handler. |
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*/ |
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NESTED(except_vec4, 0, sp) |
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1: j 1b /* Dummy, will be replaced */ |
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END(except_vec4) |
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/* |
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* EJTAG debug exception handler. |
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* The EJTAG debug exception entry point is 0xbfc00480, which |
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* normally is in the boot PROM, so the boot PROM must do an |
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* unconditional jump to this vector. |
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*/ |
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NESTED(except_vec_ejtag_debug, 0, sp) |
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j ejtag_debug_handler |
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#ifdef CONFIG_CPU_MICROMIPS |
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nop |
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#endif |
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END(except_vec_ejtag_debug) |
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__FINIT |
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/* |
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* Vectored interrupt handler. |
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* This prototype is copied to ebase + n*IntCtl.VS and patched |
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* to invoke the handler |
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*/ |
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BUILD_ROLLBACK_PROLOGUE except_vec_vi |
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NESTED(except_vec_vi, 0, sp) |
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SAVE_SOME docfi=1 |
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SAVE_AT docfi=1 |
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.set push |
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.set noreorder |
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PTR_LA v1, except_vec_vi_handler |
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FEXPORT(except_vec_vi_lui) |
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lui v0, 0 /* Patched */ |
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jr v1 |
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FEXPORT(except_vec_vi_ori) |
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ori v0, 0 /* Patched */ |
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.set pop |
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END(except_vec_vi) |
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EXPORT(except_vec_vi_end) |
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/* |
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* Common Vectored Interrupt code |
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* Complete the register saves and invoke the handler which is passed in $v0 |
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*/ |
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NESTED(except_vec_vi_handler, 0, sp) |
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SAVE_TEMP |
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SAVE_STATIC |
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CLI |
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#ifdef CONFIG_TRACE_IRQFLAGS |
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move s0, v0 |
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TRACE_IRQS_OFF |
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move v0, s0 |
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#endif |
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LONG_L s0, TI_REGS($28) |
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LONG_S sp, TI_REGS($28) |
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/* |
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* SAVE_ALL ensures we are using a valid kernel stack for the thread. |
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* Check if we are already using the IRQ stack. |
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*/ |
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move s1, sp # Preserve the sp |
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|
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/* Get IRQ stack for this CPU */ |
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ASM_CPUID_MFC0 k0, ASM_SMP_CPUID_REG |
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#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) |
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lui k1, %hi(irq_stack) |
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#else |
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lui k1, %highest(irq_stack) |
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daddiu k1, %higher(irq_stack) |
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dsll k1, 16 |
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daddiu k1, %hi(irq_stack) |
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dsll k1, 16 |
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#endif |
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LONG_SRL k0, SMP_CPUID_PTRSHIFT |
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LONG_ADDU k1, k0 |
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LONG_L t0, %lo(irq_stack)(k1) |
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# Check if already on IRQ stack |
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PTR_LI t1, ~(_THREAD_SIZE-1) |
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and t1, t1, sp |
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beq t0, t1, 2f |
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/* Switch to IRQ stack */ |
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li t1, _IRQ_STACK_START |
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PTR_ADD sp, t0, t1 |
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/* Save task's sp on IRQ stack so that unwinding can follow it */ |
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LONG_S s1, 0(sp) |
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2: |
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jalr v0 |
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/* Restore sp */ |
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move sp, s1 |
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j ret_from_irq |
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END(except_vec_vi_handler) |
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/* |
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* EJTAG debug exception handler. |
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*/ |
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NESTED(ejtag_debug_handler, PT_SIZE, sp) |
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.set push |
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.set noat |
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MTC0 k0, CP0_DESAVE |
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mfc0 k0, CP0_DEBUG |
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andi k0, k0, MIPS_DEBUG_DBP # Check for SDBBP. |
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beqz k0, ejtag_return |
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#ifdef CONFIG_SMP |
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1: PTR_LA k0, ejtag_debug_buffer_spinlock |
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__SYNC(full, loongson3_war) |
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2: ll k0, 0(k0) |
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bnez k0, 2b |
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PTR_LA k0, ejtag_debug_buffer_spinlock |
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sc k0, 0(k0) |
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beqz k0, 1b |
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# ifdef CONFIG_WEAK_REORDERING_BEYOND_LLSC |
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sync |
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# endif |
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PTR_LA k0, ejtag_debug_buffer |
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LONG_S k1, 0(k0) |
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ASM_CPUID_MFC0 k1, ASM_SMP_CPUID_REG |
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PTR_SRL k1, SMP_CPUID_PTRSHIFT |
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PTR_SLL k1, LONGLOG |
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PTR_LA k0, ejtag_debug_buffer_per_cpu |
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PTR_ADDU k0, k1 |
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PTR_LA k1, ejtag_debug_buffer |
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LONG_L k1, 0(k1) |
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LONG_S k1, 0(k0) |
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PTR_LA k0, ejtag_debug_buffer_spinlock |
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sw zero, 0(k0) |
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#else |
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PTR_LA k0, ejtag_debug_buffer |
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LONG_S k1, 0(k0) |
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#endif |
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SAVE_ALL |
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move a0, sp |
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jal ejtag_exception_handler |
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RESTORE_ALL |
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#ifdef CONFIG_SMP |
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ASM_CPUID_MFC0 k1, ASM_SMP_CPUID_REG |
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PTR_SRL k1, SMP_CPUID_PTRSHIFT |
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PTR_SLL k1, LONGLOG |
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PTR_LA k0, ejtag_debug_buffer_per_cpu |
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PTR_ADDU k0, k1 |
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LONG_L k1, 0(k0) |
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#else |
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PTR_LA k0, ejtag_debug_buffer |
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LONG_L k1, 0(k0) |
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#endif |
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ejtag_return: |
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back_to_back_c0_hazard |
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MFC0 k0, CP0_DESAVE |
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.set mips32 |
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deret |
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.set pop |
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END(ejtag_debug_handler) |
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/* |
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* This buffer is reserved for the use of the EJTAG debug |
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* handler. |
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*/ |
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.data |
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EXPORT(ejtag_debug_buffer) |
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.fill LONGSIZE |
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#ifdef CONFIG_SMP |
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EXPORT(ejtag_debug_buffer_spinlock) |
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.fill LONGSIZE |
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EXPORT(ejtag_debug_buffer_per_cpu) |
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.fill LONGSIZE * NR_CPUS |
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#endif |
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.previous |
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__INIT |
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/* |
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* NMI debug exception handler for MIPS reference boards. |
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* The NMI debug exception entry point is 0xbfc00000, which |
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* normally is in the boot PROM, so the boot PROM must do a |
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* unconditional jump to this vector. |
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*/ |
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NESTED(except_vec_nmi, 0, sp) |
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j nmi_handler |
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#ifdef CONFIG_CPU_MICROMIPS |
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nop |
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#endif |
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END(except_vec_nmi) |
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__FINIT |
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NESTED(nmi_handler, PT_SIZE, sp) |
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.cfi_signal_frame |
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.set push |
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.set noat |
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/* |
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* Clear ERL - restore segment mapping |
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* Clear BEV - required for page fault exception handler to work |
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*/ |
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mfc0 k0, CP0_STATUS |
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ori k0, k0, ST0_EXL |
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li k1, ~(ST0_BEV | ST0_ERL) |
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and k0, k0, k1 |
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mtc0 k0, CP0_STATUS |
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_ehb |
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SAVE_ALL |
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move a0, sp |
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jal nmi_exception_handler |
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/* nmi_exception_handler never returns */ |
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.set pop |
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END(nmi_handler) |
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.macro __build_clear_none |
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.endm |
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.macro __build_clear_sti |
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TRACE_IRQS_ON |
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STI |
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.endm |
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.macro __build_clear_cli |
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CLI |
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TRACE_IRQS_OFF |
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.endm |
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.macro __build_clear_fpe |
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CLI |
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TRACE_IRQS_OFF |
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.set push |
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/* gas fails to assemble cfc1 for some archs (octeon).*/ \ |
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.set mips1 |
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SET_HARDFLOAT |
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cfc1 a1, fcr31 |
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.set pop |
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.endm |
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.macro __build_clear_msa_fpe |
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CLI |
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TRACE_IRQS_OFF |
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_cfcmsa a1, MSA_CSR |
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.endm |
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.macro __build_clear_ade |
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MFC0 t0, CP0_BADVADDR |
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PTR_S t0, PT_BVADDR(sp) |
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KMODE |
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.endm |
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.macro __build_clear_gsexc |
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.set push |
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/* |
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* We need to specify a selector to access the CP0.Diag1 (GSCause) |
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* register. All GSExc-equipped processors have MIPS32. |
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*/ |
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.set mips32 |
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mfc0 a1, CP0_DIAGNOSTIC1 |
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.set pop |
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TRACE_IRQS_ON |
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STI |
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.endm |
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.macro __BUILD_silent exception |
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.endm |
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|
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/* Gas tries to parse the ASM_PRINT argument as a string containing |
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string escapes and emits bogus warnings if it believes to |
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recognize an unknown escape code. So make the arguments |
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start with an n and gas will believe \n is ok ... */ |
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.macro __BUILD_verbose nexception |
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LONG_L a1, PT_EPC(sp) |
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#ifdef CONFIG_32BIT |
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ASM_PRINT("Got \nexception at %08lx\012") |
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#endif |
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#ifdef CONFIG_64BIT |
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ASM_PRINT("Got \nexception at %016lx\012") |
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#endif |
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.endm |
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.macro __BUILD_count exception |
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LONG_L t0,exception_count_\exception |
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LONG_ADDIU t0, 1 |
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LONG_S t0,exception_count_\exception |
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.comm exception_count\exception, 8, 8 |
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.endm |
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.macro __BUILD_HANDLER exception handler clear verbose ext |
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.align 5 |
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NESTED(handle_\exception, PT_SIZE, sp) |
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.cfi_signal_frame |
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.set noat |
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SAVE_ALL |
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FEXPORT(handle_\exception\ext) |
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__build_clear_\clear |
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.set at |
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__BUILD_\verbose \exception |
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move a0, sp |
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jal do_\handler |
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j ret_from_exception |
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END(handle_\exception) |
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.endm |
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.macro BUILD_HANDLER exception handler clear verbose |
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__BUILD_HANDLER \exception \handler \clear \verbose _int |
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.endm |
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BUILD_HANDLER adel ade ade silent /* #4 */ |
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BUILD_HANDLER ades ade ade silent /* #5 */ |
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BUILD_HANDLER ibe be cli silent /* #6 */ |
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BUILD_HANDLER dbe be cli silent /* #7 */ |
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BUILD_HANDLER bp bp sti silent /* #9 */ |
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BUILD_HANDLER ri ri sti silent /* #10 */ |
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BUILD_HANDLER cpu cpu sti silent /* #11 */ |
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BUILD_HANDLER ov ov sti silent /* #12 */ |
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BUILD_HANDLER tr tr sti silent /* #13 */ |
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BUILD_HANDLER msa_fpe msa_fpe msa_fpe silent /* #14 */ |
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#ifdef CONFIG_MIPS_FP_SUPPORT |
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BUILD_HANDLER fpe fpe fpe silent /* #15 */ |
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#endif |
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BUILD_HANDLER ftlb ftlb none silent /* #16 */ |
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BUILD_HANDLER gsexc gsexc gsexc silent /* #16 */ |
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BUILD_HANDLER msa msa sti silent /* #21 */ |
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BUILD_HANDLER mdmx mdmx sti silent /* #22 */ |
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#ifdef CONFIG_HARDWARE_WATCHPOINTS |
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/* |
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* For watch, interrupts will be enabled after the watch |
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* registers are read. |
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*/ |
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BUILD_HANDLER watch watch cli silent /* #23 */ |
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#else |
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BUILD_HANDLER watch watch sti verbose /* #23 */ |
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#endif |
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BUILD_HANDLER mcheck mcheck cli verbose /* #24 */ |
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BUILD_HANDLER mt mt sti silent /* #25 */ |
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BUILD_HANDLER dsp dsp sti silent /* #26 */ |
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BUILD_HANDLER reserved reserved sti verbose /* others */ |
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|
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.align 5 |
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LEAF(handle_ri_rdhwr_tlbp) |
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.set push |
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.set noat |
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.set noreorder |
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/* check if TLB contains a entry for EPC */ |
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MFC0 k1, CP0_ENTRYHI |
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andi k1, MIPS_ENTRYHI_ASID | MIPS_ENTRYHI_ASIDX |
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MFC0 k0, CP0_EPC |
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PTR_SRL k0, _PAGE_SHIFT + 1 |
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PTR_SLL k0, _PAGE_SHIFT + 1 |
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or k1, k0 |
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MTC0 k1, CP0_ENTRYHI |
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mtc0_tlbw_hazard |
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tlbp |
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tlb_probe_hazard |
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mfc0 k1, CP0_INDEX |
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.set pop |
|
bltz k1, handle_ri /* slow path */ |
|
/* fall thru */ |
|
END(handle_ri_rdhwr_tlbp) |
|
|
|
LEAF(handle_ri_rdhwr) |
|
.set push |
|
.set noat |
|
.set noreorder |
|
/* MIPS32: 0x7c03e83b: rdhwr v1,$29 */ |
|
/* microMIPS: 0x007d6b3c: rdhwr v1,$29 */ |
|
MFC0 k1, CP0_EPC |
|
#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS64_R2) |
|
and k0, k1, 1 |
|
beqz k0, 1f |
|
xor k1, k0 |
|
lhu k0, (k1) |
|
lhu k1, 2(k1) |
|
ins k1, k0, 16, 16 |
|
lui k0, 0x007d |
|
b docheck |
|
ori k0, 0x6b3c |
|
1: |
|
lui k0, 0x7c03 |
|
lw k1, (k1) |
|
ori k0, 0xe83b |
|
#else |
|
andi k0, k1, 1 |
|
bnez k0, handle_ri |
|
lui k0, 0x7c03 |
|
lw k1, (k1) |
|
ori k0, 0xe83b |
|
#endif |
|
.set reorder |
|
docheck: |
|
bne k0, k1, handle_ri /* if not ours */ |
|
|
|
isrdhwr: |
|
/* The insn is rdhwr. No need to check CAUSE.BD here. */ |
|
get_saved_sp /* k1 := current_thread_info */ |
|
.set noreorder |
|
MFC0 k0, CP0_EPC |
|
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) |
|
ori k1, _THREAD_MASK |
|
xori k1, _THREAD_MASK |
|
LONG_L v1, TI_TP_VALUE(k1) |
|
LONG_ADDIU k0, 4 |
|
jr k0 |
|
rfe |
|
#else |
|
#ifndef CONFIG_CPU_DADDI_WORKAROUNDS |
|
LONG_ADDIU k0, 4 /* stall on $k0 */ |
|
#else |
|
.set at=v1 |
|
LONG_ADDIU k0, 4 |
|
.set noat |
|
#endif |
|
MTC0 k0, CP0_EPC |
|
/* I hope three instructions between MTC0 and ERET are enough... */ |
|
ori k1, _THREAD_MASK |
|
xori k1, _THREAD_MASK |
|
LONG_L v1, TI_TP_VALUE(k1) |
|
.set push |
|
.set arch=r4000 |
|
eret |
|
.set pop |
|
#endif |
|
.set pop |
|
END(handle_ri_rdhwr) |
|
|
|
#ifdef CONFIG_CPU_R4X00_BUGS64 |
|
/* A temporary overflow handler used by check_daddi(). */ |
|
|
|
__INIT |
|
|
|
BUILD_HANDLER daddi_ov daddi_ov none silent /* #12 */ |
|
#endif
|
|
|