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209 lines
7.6 KiB
209 lines
7.6 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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#ifndef __MIPS_ASM_SYNC_H__ |
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#define __MIPS_ASM_SYNC_H__ |
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/* |
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* sync types are defined by the MIPS64 Instruction Set documentation in Volume |
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* II-A of the MIPS Architecture Reference Manual, which can be found here: |
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* |
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* https://www.mips.com/?do-download=the-mips64-instruction-set-v6-06 |
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* |
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* Two types of barrier are provided: |
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* |
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* 1) Completion barriers, which ensure that a memory operation has actually |
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* completed & often involve stalling the CPU pipeline to do so. |
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* |
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* 2) Ordering barriers, which only ensure that affected memory operations |
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* won't be reordered in the CPU pipeline in a manner that violates the |
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* restrictions imposed by the barrier. |
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* |
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* Ordering barriers can be more efficient than completion barriers, since: |
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* |
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* a) Ordering barriers only require memory access instructions which preceed |
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* them in program order (older instructions) to reach a point in the |
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* load/store datapath beyond which reordering is not possible before |
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* allowing memory access instructions which follow them (younger |
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* instructions) to be performed. That is, older instructions don't |
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* actually need to complete - they just need to get far enough that all |
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* other coherent CPUs will observe their completion before they observe |
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* the effects of younger instructions. |
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* |
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* b) Multiple variants of ordering barrier are provided which allow the |
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* effects to be restricted to different combinations of older or younger |
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* loads or stores. By way of example, if we only care that stores older |
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* than a barrier are observed prior to stores that are younger than a |
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* barrier & don't care about the ordering of loads then the 'wmb' |
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* ordering barrier can be used. Limiting the barrier's effects to stores |
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* allows loads to continue unaffected & potentially allows the CPU to |
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* make progress faster than if younger loads had to wait for older stores |
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* to complete. |
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*/ |
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/* |
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* No sync instruction at all; used to allow code to nullify the effect of the |
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* __SYNC() macro without needing lots of #ifdefery. |
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*/ |
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#define __SYNC_none -1 |
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/* |
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* A full completion barrier; all memory accesses appearing prior to this sync |
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* instruction in program order must complete before any memory accesses |
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* appearing after this sync instruction in program order. |
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*/ |
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#define __SYNC_full 0x00 |
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/* |
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* For now we use a full completion barrier to implement all sync types, until |
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* we're satisfied that lightweight ordering barriers defined by MIPSr6 are |
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* sufficient to uphold our desired memory model. |
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*/ |
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#define __SYNC_aq __SYNC_full |
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#define __SYNC_rl __SYNC_full |
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#define __SYNC_mb __SYNC_full |
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/* |
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* ...except on Cavium Octeon CPUs, which have been using the 'wmb' ordering |
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* barrier since 2010 & omit 'rmb' barriers because the CPUs don't perform |
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* speculative reads. |
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*/ |
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#ifdef CONFIG_CPU_CAVIUM_OCTEON |
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# define __SYNC_rmb __SYNC_none |
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# define __SYNC_wmb 0x04 |
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#else |
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# define __SYNC_rmb __SYNC_full |
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# define __SYNC_wmb __SYNC_full |
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#endif |
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/* |
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* A GINV sync is a little different; it doesn't relate directly to loads or |
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* stores, but instead causes synchronization of an icache or TLB global |
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* invalidation operation triggered by the ginvi or ginvt instructions |
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* respectively. In cases where we need to know that a ginvi or ginvt operation |
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* has been performed by all coherent CPUs, we must issue a sync instruction of |
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* this type. Once this instruction graduates all coherent CPUs will have |
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* observed the invalidation. |
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*/ |
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#define __SYNC_ginv 0x14 |
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/* Trivial; indicate that we always need this sync instruction. */ |
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#define __SYNC_always (1 << 0) |
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/* |
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* Indicate that we need this sync instruction only on systems with weakly |
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* ordered memory access. In general this is most MIPS systems, but there are |
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* exceptions which provide strongly ordered memory. |
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*/ |
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#ifdef CONFIG_WEAK_ORDERING |
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# define __SYNC_weak_ordering (1 << 1) |
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#else |
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# define __SYNC_weak_ordering 0 |
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#endif |
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/* |
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* Indicate that we need this sync instruction only on systems where LL/SC |
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* don't implicitly provide a memory barrier. In general this is most MIPS |
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* systems. |
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*/ |
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#ifdef CONFIG_WEAK_REORDERING_BEYOND_LLSC |
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# define __SYNC_weak_llsc (1 << 2) |
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#else |
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# define __SYNC_weak_llsc 0 |
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#endif |
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/* |
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* Some Loongson 3 CPUs have a bug wherein execution of a memory access (load, |
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* store or prefetch) in between an LL & SC can cause the SC instruction to |
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* erroneously succeed, breaking atomicity. Whilst it's unusual to write code |
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* containing such sequences, this bug bites harder than we might otherwise |
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* expect due to reordering & speculation: |
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* |
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* 1) A memory access appearing prior to the LL in program order may actually |
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* be executed after the LL - this is the reordering case. |
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* |
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* In order to avoid this we need to place a memory barrier (ie. a SYNC |
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* instruction) prior to every LL instruction, in between it and any earlier |
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* memory access instructions. |
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* |
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* This reordering case is fixed by 3A R2 CPUs, ie. 3A2000 models and later. |
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* |
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* 2) If a conditional branch exists between an LL & SC with a target outside |
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* of the LL-SC loop, for example an exit upon value mismatch in cmpxchg() |
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* or similar, then misprediction of the branch may allow speculative |
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* execution of memory accesses from outside of the LL-SC loop. |
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* |
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* In order to avoid this we need a memory barrier (ie. a SYNC instruction) |
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* at each affected branch target. |
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* |
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* This case affects all current Loongson 3 CPUs. |
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* |
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* The above described cases cause an error in the cache coherence protocol; |
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* such that the Invalidate of a competing LL-SC goes 'missing' and SC |
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* erroneously observes its core still has Exclusive state and lets the SC |
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* proceed. |
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* |
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* Therefore the error only occurs on SMP systems. |
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*/ |
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#ifdef CONFIG_CPU_LOONGSON3_WORKAROUNDS |
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# define __SYNC_loongson3_war (1 << 31) |
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#else |
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# define __SYNC_loongson3_war 0 |
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#endif |
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/* |
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* Some Cavium Octeon CPUs suffer from a bug that causes a single wmb ordering |
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* barrier to be ineffective, requiring the use of 2 in sequence to provide an |
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* effective barrier as noted by commit 6b07d38aaa52 ("MIPS: Octeon: Use |
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* optimized memory barrier primitives."). Here we specify that the affected |
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* sync instructions should be emitted twice. |
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* Note that this expression is evaluated by the assembler (not the compiler), |
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* and that the assembler evaluates '==' as 0 or -1, not 0 or 1. |
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*/ |
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#ifdef CONFIG_CPU_CAVIUM_OCTEON |
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# define __SYNC_rpt(type) (1 - (type == __SYNC_wmb)) |
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#else |
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# define __SYNC_rpt(type) 1 |
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#endif |
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/* |
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* The main event. Here we actually emit a sync instruction of a given type, if |
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* reason is non-zero. |
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* |
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* In future we have the option of emitting entries in a fixups-style table |
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* here that would allow us to opportunistically remove some sync instructions |
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* when we detect at runtime that we're running on a CPU that doesn't need |
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* them. |
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*/ |
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#ifdef CONFIG_CPU_HAS_SYNC |
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# define ____SYNC(_type, _reason, _else) \ |
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.if (( _type ) != -1) && ( _reason ); \ |
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.set push; \ |
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.set MIPS_ISA_LEVEL_RAW; \ |
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.rept __SYNC_rpt(_type); \ |
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sync _type; \ |
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.endr; \ |
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.set pop; \ |
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.else; \ |
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_else; \ |
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.endif |
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#else |
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# define ____SYNC(_type, _reason, _else) |
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#endif |
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/* |
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* Preprocessor magic to expand macros used as arguments before we insert them |
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* into assembly code. |
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*/ |
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#ifdef __ASSEMBLY__ |
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# define ___SYNC(type, reason, else) \ |
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____SYNC(type, reason, else) |
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#else |
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# define ___SYNC(type, reason, else) \ |
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__stringify(____SYNC(type, reason, else)) |
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#endif |
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#define __SYNC(type, reason) \ |
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___SYNC(__SYNC_##type, __SYNC_##reason, ) |
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#define __SYNC_ELSE(type, reason, else) \ |
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___SYNC(__SYNC_##type, __SYNC_##reason, else) |
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#endif /* __MIPS_ASM_SYNC_H__ */
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