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393 lines
14 KiB
393 lines
14 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* ********************************************************************* |
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* BCM1280/BCM1400 Board Support Package |
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* |
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* SCD Constants and Macros File: bcm1480_scd.h |
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* |
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* This module contains constants and macros useful for |
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* manipulating the System Control and Debug module. |
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* |
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* BCM1400 specification level: 1X55_1X80-UM100-R (12/18/03) |
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* |
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********************************************************************* |
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* |
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* Copyright 2000,2001,2002,2003,2004,2005 |
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* Broadcom Corporation. All rights reserved. |
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* |
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********************************************************************* */ |
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#ifndef _BCM1480_SCD_H |
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#define _BCM1480_SCD_H |
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#include <asm/sibyte/sb1250_defs.h> |
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/* ********************************************************************* |
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* Pull in the BCM1250's SCD since lots of stuff is the same. |
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********************************************************************* */ |
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#include <asm/sibyte/sb1250_scd.h> |
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/* ********************************************************************* |
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* Some general notes: |
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* |
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* This file is basically a "what's new" header file. Since the |
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* BCM1250 and the new BCM1480 (and derivatives) share many common |
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* features, this file contains only what's new or changed from |
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* the 1250. (above, you can see that we include the 1250 symbols |
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* to get the base functionality). |
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* |
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* In software, be sure to use the correct symbols, particularly |
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* for blocks that are different between the two chip families. |
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* All BCM1480-specific symbols have _BCM1480_ in their names, |
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* and all BCM1250-specific and "base" functions that are common in |
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* both chips have no special names (this is for compatibility with |
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* older include files). Therefore, if you're working with the |
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* SCD, which is very different on each chip, A_SCD_xxx implies |
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* the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480 |
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* version. |
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********************************************************************* */ |
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/* ********************************************************************* |
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* System control/debug registers |
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********************************************************************* */ |
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/* |
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* System Identification and Revision Register (Table 12) |
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* Register: SCD_SYSTEM_REVISION |
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* This register is field compatible with the 1250. |
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*/ |
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/* |
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* New part definitions |
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*/ |
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#define K_SYS_PART_BCM1480 0x1406 |
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#define K_SYS_PART_BCM1280 0x1206 |
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#define K_SYS_PART_BCM1455 0x1407 |
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#define K_SYS_PART_BCM1255 0x1257 |
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#define K_SYS_PART_BCM1158 0x1156 |
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/* |
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* Manufacturing Information Register (Table 14) |
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* Register: SCD_SYSTEM_MANUF |
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*/ |
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/* |
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* System Configuration Register (Table 15) |
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* Register: SCD_SYSTEM_CFG |
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* Entire register is different from 1250, all new constants below |
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*/ |
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#define M_BCM1480_SYS_RESERVED0 _SB_MAKEMASK1(0) |
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#define M_BCM1480_SYS_HT_MINRSTCNT _SB_MAKEMASK1(1) |
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#define M_BCM1480_SYS_RESERVED2 _SB_MAKEMASK1(2) |
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#define M_BCM1480_SYS_RESERVED3 _SB_MAKEMASK1(3) |
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#define M_BCM1480_SYS_RESERVED4 _SB_MAKEMASK1(4) |
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#define M_BCM1480_SYS_IOB_DIV _SB_MAKEMASK1(5) |
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#define S_BCM1480_SYS_PLL_DIV _SB_MAKE64(6) |
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#define M_BCM1480_SYS_PLL_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV) |
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#define V_BCM1480_SYS_PLL_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV) |
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#define G_BCM1480_SYS_PLL_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV) |
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#define S_BCM1480_SYS_SW_DIV _SB_MAKE64(11) |
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#define M_BCM1480_SYS_SW_DIV _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV) |
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#define V_BCM1480_SYS_SW_DIV(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV) |
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#define G_BCM1480_SYS_SW_DIV(x) _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV) |
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#define M_BCM1480_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16) |
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#define M_BCM1480_SYS_DUART1_ENABLE _SB_MAKEMASK1(17) |
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#define S_BCM1480_SYS_BOOT_MODE _SB_MAKE64(18) |
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#define M_BCM1480_SYS_BOOT_MODE _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE) |
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#define V_BCM1480_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE) |
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#define G_BCM1480_SYS_BOOT_MODE(x) _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE) |
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#define K_BCM1480_SYS_BOOT_MODE_ROM32 0 |
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#define K_BCM1480_SYS_BOOT_MODE_ROM8 1 |
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#define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2 |
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#define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG 3 |
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#define M_BCM1480_SYS_BOOT_MODE_SMBUS _SB_MAKEMASK1(19) |
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#define M_BCM1480_SYS_PCI_HOST _SB_MAKEMASK1(20) |
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#define M_BCM1480_SYS_PCI_ARBITER _SB_MAKEMASK1(21) |
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#define M_BCM1480_SYS_BIG_ENDIAN _SB_MAKEMASK1(22) |
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#define M_BCM1480_SYS_GENCLK_EN _SB_MAKEMASK1(23) |
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#define M_BCM1480_SYS_GEN_PARITY_EN _SB_MAKEMASK1(24) |
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#define M_BCM1480_SYS_RESERVED25 _SB_MAKEMASK1(25) |
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#define S_BCM1480_SYS_CONFIG 26 |
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#define M_BCM1480_SYS_CONFIG _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG) |
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#define V_BCM1480_SYS_CONFIG(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG) |
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#define G_BCM1480_SYS_CONFIG(x) _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG) |
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#define M_BCM1480_SYS_RESERVED32 _SB_MAKEMASK(32, 15) |
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#define S_BCM1480_SYS_NODEID 47 |
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#define M_BCM1480_SYS_NODEID _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID) |
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#define V_BCM1480_SYS_NODEID(x) _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID) |
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#define G_BCM1480_SYS_NODEID(x) _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID) |
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#define M_BCM1480_SYS_CCNUMA_EN _SB_MAKEMASK1(51) |
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#define M_BCM1480_SYS_CPU_RESET_0 _SB_MAKEMASK1(52) |
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#define M_BCM1480_SYS_CPU_RESET_1 _SB_MAKEMASK1(53) |
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#define M_BCM1480_SYS_CPU_RESET_2 _SB_MAKEMASK1(54) |
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#define M_BCM1480_SYS_CPU_RESET_3 _SB_MAKEMASK1(55) |
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#define S_BCM1480_SYS_DISABLECPU0 56 |
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#define M_BCM1480_SYS_DISABLECPU0 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0) |
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#define S_BCM1480_SYS_DISABLECPU1 57 |
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#define M_BCM1480_SYS_DISABLECPU1 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1) |
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#define S_BCM1480_SYS_DISABLECPU2 58 |
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#define M_BCM1480_SYS_DISABLECPU2 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2) |
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#define S_BCM1480_SYS_DISABLECPU3 59 |
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#define M_BCM1480_SYS_DISABLECPU3 _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3) |
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#define M_BCM1480_SYS_SB_SOFTRES _SB_MAKEMASK1(60) |
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#define M_BCM1480_SYS_EXT_RESET _SB_MAKEMASK1(61) |
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#define M_BCM1480_SYS_SYSTEM_RESET _SB_MAKEMASK1(62) |
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#define M_BCM1480_SYS_SW_FLAG _SB_MAKEMASK1(63) |
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/* |
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* Scratch Register (Table 16) |
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* Register: SCD_SYSTEM_SCRATCH |
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* Same as BCM1250 |
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*/ |
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/* |
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* Mailbox Registers (Table 17) |
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* Registers: SCD_MBOX_{0,1}_CPU_x |
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* Same as BCM1250 |
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*/ |
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/* |
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* See bcm1480_int.h for interrupt mapper registers. |
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*/ |
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/* |
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* Watchdog Timer Initial Count Registers (Table 23) |
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* Registers: SCD_WDOG_INIT_CNT_x |
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* |
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* The watchdogs are almost the same as the 1250, except |
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* the configuration register has more bits to control the |
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* other CPUs. |
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*/ |
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/* |
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* Watchdog Timer Configuration Registers (Table 25) |
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* Registers: SCD_WDOG_CFG_x |
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*/ |
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#define M_BCM1480_SCD_WDOG_ENABLE _SB_MAKEMASK1(0) |
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#define S_BCM1480_SCD_WDOG_RESET_TYPE 2 |
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#define M_BCM1480_SCD_WDOG_RESET_TYPE _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE) |
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#define V_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE) |
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#define G_BCM1480_SCD_WDOG_RESET_TYPE(x) _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE) |
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#define K_BCM1480_SCD_WDOG_RESET_FULL 0 /* actually, (x & 1) == 0 */ |
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#define K_BCM1480_SCD_WDOG_RESET_SOFT 1 |
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#define K_BCM1480_SCD_WDOG_RESET_CPU0 3 |
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#define K_BCM1480_SCD_WDOG_RESET_CPU1 5 |
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#define K_BCM1480_SCD_WDOG_RESET_CPU2 9 |
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#define K_BCM1480_SCD_WDOG_RESET_CPU3 17 |
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#define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS 31 |
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#define M_BCM1480_SCD_WDOG_HAS_RESET _SB_MAKEMASK1(8) |
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/* |
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* General Timer Initial Count Registers (Table 26) |
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* Registers: SCD_TIMER_INIT_x |
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* |
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* The timer registers are the same as the BCM1250 |
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*/ |
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/* |
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* ZBbus Count Register (Table 29) |
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* Register: ZBBUS_CYCLE_COUNT |
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* |
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* Same as BCM1250 |
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*/ |
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/* |
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* ZBbus Compare Registers (Table 30) |
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* Registers: ZBBUS_CYCLE_CPx |
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* |
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* Same as BCM1250 |
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*/ |
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/* |
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* System Performance Counter Configuration Register (Table 31) |
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* Register: PERF_CNT_CFG_0 |
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* |
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* SPC_CFG_SRC[0-3] is the same as the 1250. |
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* SPC_CFG_SRC[4-7] only exist on the 1480 |
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* The clear/enable bits are in different locations on the 1250 and 1480. |
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*/ |
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#define S_SPC_CFG_SRC4 32 |
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#define M_SPC_CFG_SRC4 _SB_MAKEMASK(8, S_SPC_CFG_SRC4) |
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#define V_SPC_CFG_SRC4(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC4) |
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#define G_SPC_CFG_SRC4(x) _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4) |
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#define S_SPC_CFG_SRC5 40 |
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#define M_SPC_CFG_SRC5 _SB_MAKEMASK(8, S_SPC_CFG_SRC5) |
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#define V_SPC_CFG_SRC5(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC5) |
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#define G_SPC_CFG_SRC5(x) _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5) |
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#define S_SPC_CFG_SRC6 48 |
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#define M_SPC_CFG_SRC6 _SB_MAKEMASK(8, S_SPC_CFG_SRC6) |
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#define V_SPC_CFG_SRC6(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC6) |
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#define G_SPC_CFG_SRC6(x) _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6) |
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#define S_SPC_CFG_SRC7 56 |
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#define M_SPC_CFG_SRC7 _SB_MAKEMASK(8, S_SPC_CFG_SRC7) |
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#define V_SPC_CFG_SRC7(x) _SB_MAKEVALUE(x, S_SPC_CFG_SRC7) |
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#define G_SPC_CFG_SRC7(x) _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7) |
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/* |
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* System Performance Counter Control Register (Table 32) |
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* Register: PERF_CNT_CFG_1 |
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* BCM1480 specific |
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*/ |
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#define M_BCM1480_SPC_CFG_CLEAR _SB_MAKEMASK1(0) |
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#define M_BCM1480_SPC_CFG_ENABLE _SB_MAKEMASK1(1) |
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#if SIBYTE_HDR_FEATURE_CHIP(1480) |
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#define M_SPC_CFG_CLEAR M_BCM1480_SPC_CFG_CLEAR |
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#define M_SPC_CFG_ENABLE M_BCM1480_SPC_CFG_ENABLE |
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#endif |
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/* |
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* System Performance Counters (Table 33) |
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* Registers: PERF_CNT_x |
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*/ |
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#define S_BCM1480_SPC_CNT_COUNT 0 |
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#define M_BCM1480_SPC_CNT_COUNT _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT) |
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#define V_BCM1480_SPC_CNT_COUNT(x) _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT) |
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#define G_BCM1480_SPC_CNT_COUNT(x) _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT) |
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#define M_BCM1480_SPC_CNT_OFLOW _SB_MAKEMASK1(40) |
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/* |
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* Bus Watcher Error Status Register (Tables 36, 37) |
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* Registers: BUS_ERR_STATUS, BUS_ERR_STATUS_DEBUG |
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* Same as BCM1250. |
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*/ |
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/* |
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* Bus Watcher Error Data Registers (Table 38) |
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* Registers: BUS_ERR_DATA_x |
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* Same as BCM1250. |
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*/ |
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/* |
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* Bus Watcher L2 ECC Counter Register (Table 39) |
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* Register: BUS_L2_ERRORS |
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* Same as BCM1250. |
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*/ |
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/* |
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* Bus Watcher Memory and I/O Error Counter Register (Table 40) |
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* Register: BUS_MEM_IO_ERRORS |
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* Same as BCM1250. |
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*/ |
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/* |
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* Address Trap Registers |
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* |
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* Register layout same as BCM1250, almost. The bus agents |
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* are different, and the address trap configuration bits are |
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* slightly different. |
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*/ |
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#define M_BCM1480_ATRAP_INDEX _SB_MAKEMASK(4, 0) |
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#define M_BCM1480_ATRAP_ADDRESS _SB_MAKEMASK(40, 0) |
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#define S_BCM1480_ATRAP_CFG_CNT 0 |
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#define M_BCM1480_ATRAP_CFG_CNT _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT) |
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#define V_BCM1480_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT) |
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#define G_BCM1480_ATRAP_CFG_CNT(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT) |
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#define M_BCM1480_ATRAP_CFG_WRITE _SB_MAKEMASK1(3) |
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#define M_BCM1480_ATRAP_CFG_ALL _SB_MAKEMASK1(4) |
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#define M_BCM1480_ATRAP_CFG_INV _SB_MAKEMASK1(5) |
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#define M_BCM1480_ATRAP_CFG_USESRC _SB_MAKEMASK1(6) |
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#define M_BCM1480_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7) |
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#define S_BCM1480_ATRAP_CFG_AGENTID 8 |
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#define M_BCM1480_ATRAP_CFG_AGENTID _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID) |
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#define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID) |
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#define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID) |
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#define K_BCM1480_BUS_AGENT_CPU0 0 |
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#define K_BCM1480_BUS_AGENT_CPU1 1 |
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#define K_BCM1480_BUS_AGENT_NC 2 |
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#define K_BCM1480_BUS_AGENT_IOB 3 |
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#define K_BCM1480_BUS_AGENT_SCD 4 |
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#define K_BCM1480_BUS_AGENT_L2C 6 |
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#define K_BCM1480_BUS_AGENT_MC 7 |
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#define K_BCM1480_BUS_AGENT_CPU2 8 |
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#define K_BCM1480_BUS_AGENT_CPU3 9 |
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#define K_BCM1480_BUS_AGENT_PM 10 |
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#define S_BCM1480_ATRAP_CFG_CATTR 12 |
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#define M_BCM1480_ATRAP_CFG_CATTR _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR) |
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#define V_BCM1480_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR) |
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#define G_BCM1480_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR) |
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#define K_BCM1480_ATRAP_CFG_CATTR_IGNORE 0 |
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#define K_BCM1480_ATRAP_CFG_CATTR_UNC 1 |
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#define K_BCM1480_ATRAP_CFG_CATTR_NONCOH 2 |
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#define K_BCM1480_ATRAP_CFG_CATTR_COHERENT 3 |
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#define M_BCM1480_ATRAP_CFG_CATTRINV _SB_MAKEMASK1(14) |
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/* |
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* Trace Event Registers (Table 47) |
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* Same as BCM1250. |
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*/ |
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/* |
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* Trace Sequence Control Registers (Table 48) |
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* Registers: TRACE_SEQUENCE_x |
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* |
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* Same as BCM1250 except for two new fields. |
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*/ |
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#define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN _SB_MAKEMASK1(25) |
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#define S_BCM1480_SCD_TRSEQ_SWFUNC 26 |
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#define M_BCM1480_SCD_TRSEQ_SWFUNC _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC) |
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#define V_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC) |
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#define G_BCM1480_SCD_TRSEQ_SWFUNC(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC) |
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/* |
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* Trace Control Register (Table 49) |
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* Register: TRACE_CFG |
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* |
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* BCM1480 changes to this register (other than location of the CUR_ADDR field) |
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* are defined below. |
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*/ |
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#define S_BCM1480_SCD_TRACE_CFG_MODE 16 |
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#define M_BCM1480_SCD_TRACE_CFG_MODE _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE) |
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#define V_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE) |
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#define G_BCM1480_SCD_TRACE_CFG_MODE(x) _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE) |
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#define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS 0 |
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#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1 |
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#define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID 2 |
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#endif /* _BCM1480_SCD_H */
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