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57 lines
1.4 KiB
57 lines
1.4 KiB
/* |
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* Cobalt IRQ definitions. |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 1997 Cobalt Microserver |
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* Copyright (C) 1997, 2003 Ralf Baechle |
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* Copyright (C) 2001-2003 Liam Davies ([email protected]) |
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* Copyright (C) 2007 Yoichi Yuasa <[email protected]> |
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*/ |
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#ifndef _ASM_COBALT_IRQ_H |
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#define _ASM_COBALT_IRQ_H |
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/* |
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* i8259 interrupts used on Cobalt: |
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* |
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* 8 - RTC |
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* 9 - PCI slot |
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* 14 - IDE0 |
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* 15 - IDE1(no connector on board) |
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*/ |
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#define I8259A_IRQ_BASE 0 |
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#define PCISLOT_IRQ (I8259A_IRQ_BASE + 9) |
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/* |
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* CPU interrupts used on Cobalt: |
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* |
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* 0 - Software interrupt 0 (unused) |
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* 1 - Software interrupt 0 (unused) |
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* 2 - cascade GT64111 |
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* 3 - ethernet or SCSI host controller |
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* 4 - ethernet |
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* 5 - 16550 UART |
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* 6 - cascade i8259 |
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* 7 - CP0 counter |
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*/ |
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#define MIPS_CPU_IRQ_BASE 16 |
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#define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2) |
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#define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3) |
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#define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3) |
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#define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4) |
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#define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4) |
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#define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5) |
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#define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5) |
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#define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6) |
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#define GT641XX_IRQ_BASE 24 |
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#include <asm/irq_gt641xx.h> |
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#define NR_IRQS (GT641XX_PCI_INT3_IRQ + 1) |
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#endif /* _ASM_COBALT_IRQ_H */
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