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658 lines
14 KiB
658 lines
14 KiB
/* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 2003 Ralf Baechle |
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*/ |
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#ifndef _ASM_ASMMACRO_H |
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#define _ASM_ASMMACRO_H |
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#include <asm/hazards.h> |
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#include <asm/asm-offsets.h> |
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#include <asm/msa.h> |
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#ifdef CONFIG_32BIT |
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#include <asm/asmmacro-32.h> |
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#endif |
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#ifdef CONFIG_64BIT |
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#include <asm/asmmacro-64.h> |
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#endif |
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/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */ |
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#undef fp |
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/* |
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* Helper macros for generating raw instruction encodings. |
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*/ |
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#ifdef CONFIG_CPU_MICROMIPS |
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.macro insn32_if_mm enc |
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.insn |
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.hword ((\enc) >> 16) |
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.hword ((\enc) & 0xffff) |
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.endm |
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.macro insn_if_mips enc |
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.endm |
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#else |
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.macro insn32_if_mm enc |
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.endm |
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.macro insn_if_mips enc |
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.insn |
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.word (\enc) |
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.endm |
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#endif |
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#ifdef CONFIG_CPU_HAS_DIEI |
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.macro local_irq_enable reg=t0 |
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ei |
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irq_enable_hazard |
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.endm |
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.macro local_irq_disable reg=t0 |
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di |
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irq_disable_hazard |
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.endm |
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#else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */ |
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.macro local_irq_enable reg=t0 |
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mfc0 \reg, CP0_STATUS |
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ori \reg, \reg, 1 |
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mtc0 \reg, CP0_STATUS |
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irq_enable_hazard |
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.endm |
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.macro local_irq_disable reg=t0 |
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#ifdef CONFIG_PREEMPTION |
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lw \reg, TI_PRE_COUNT($28) |
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addi \reg, \reg, 1 |
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sw \reg, TI_PRE_COUNT($28) |
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#endif |
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mfc0 \reg, CP0_STATUS |
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ori \reg, \reg, 1 |
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xori \reg, \reg, 1 |
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mtc0 \reg, CP0_STATUS |
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irq_disable_hazard |
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#ifdef CONFIG_PREEMPTION |
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lw \reg, TI_PRE_COUNT($28) |
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addi \reg, \reg, -1 |
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sw \reg, TI_PRE_COUNT($28) |
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#endif |
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.endm |
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#endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */ |
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.macro fpu_save_16even thread tmp=t0 |
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.set push |
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SET_HARDFLOAT |
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cfc1 \tmp, fcr31 |
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sdc1 $f0, THREAD_FPR0(\thread) |
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sdc1 $f2, THREAD_FPR2(\thread) |
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sdc1 $f4, THREAD_FPR4(\thread) |
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sdc1 $f6, THREAD_FPR6(\thread) |
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sdc1 $f8, THREAD_FPR8(\thread) |
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sdc1 $f10, THREAD_FPR10(\thread) |
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sdc1 $f12, THREAD_FPR12(\thread) |
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sdc1 $f14, THREAD_FPR14(\thread) |
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sdc1 $f16, THREAD_FPR16(\thread) |
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sdc1 $f18, THREAD_FPR18(\thread) |
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sdc1 $f20, THREAD_FPR20(\thread) |
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sdc1 $f22, THREAD_FPR22(\thread) |
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sdc1 $f24, THREAD_FPR24(\thread) |
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sdc1 $f26, THREAD_FPR26(\thread) |
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sdc1 $f28, THREAD_FPR28(\thread) |
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sdc1 $f30, THREAD_FPR30(\thread) |
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sw \tmp, THREAD_FCR31(\thread) |
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.set pop |
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.endm |
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.macro fpu_save_16odd thread |
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.set push |
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.set mips64r2 |
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.set fp=64 |
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SET_HARDFLOAT |
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sdc1 $f1, THREAD_FPR1(\thread) |
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sdc1 $f3, THREAD_FPR3(\thread) |
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sdc1 $f5, THREAD_FPR5(\thread) |
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sdc1 $f7, THREAD_FPR7(\thread) |
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sdc1 $f9, THREAD_FPR9(\thread) |
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sdc1 $f11, THREAD_FPR11(\thread) |
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sdc1 $f13, THREAD_FPR13(\thread) |
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sdc1 $f15, THREAD_FPR15(\thread) |
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sdc1 $f17, THREAD_FPR17(\thread) |
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sdc1 $f19, THREAD_FPR19(\thread) |
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sdc1 $f21, THREAD_FPR21(\thread) |
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sdc1 $f23, THREAD_FPR23(\thread) |
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sdc1 $f25, THREAD_FPR25(\thread) |
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sdc1 $f27, THREAD_FPR27(\thread) |
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sdc1 $f29, THREAD_FPR29(\thread) |
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sdc1 $f31, THREAD_FPR31(\thread) |
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.set pop |
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.endm |
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.macro fpu_save_double thread status tmp |
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#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \ |
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defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6) |
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sll \tmp, \status, 5 |
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bgez \tmp, 10f |
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fpu_save_16odd \thread |
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10: |
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#endif |
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fpu_save_16even \thread \tmp |
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.endm |
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.macro fpu_restore_16even thread tmp=t0 |
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.set push |
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SET_HARDFLOAT |
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lw \tmp, THREAD_FCR31(\thread) |
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ldc1 $f0, THREAD_FPR0(\thread) |
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ldc1 $f2, THREAD_FPR2(\thread) |
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ldc1 $f4, THREAD_FPR4(\thread) |
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ldc1 $f6, THREAD_FPR6(\thread) |
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ldc1 $f8, THREAD_FPR8(\thread) |
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ldc1 $f10, THREAD_FPR10(\thread) |
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ldc1 $f12, THREAD_FPR12(\thread) |
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ldc1 $f14, THREAD_FPR14(\thread) |
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ldc1 $f16, THREAD_FPR16(\thread) |
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ldc1 $f18, THREAD_FPR18(\thread) |
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ldc1 $f20, THREAD_FPR20(\thread) |
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ldc1 $f22, THREAD_FPR22(\thread) |
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ldc1 $f24, THREAD_FPR24(\thread) |
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ldc1 $f26, THREAD_FPR26(\thread) |
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ldc1 $f28, THREAD_FPR28(\thread) |
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ldc1 $f30, THREAD_FPR30(\thread) |
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ctc1 \tmp, fcr31 |
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.set pop |
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.endm |
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.macro fpu_restore_16odd thread |
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.set push |
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.set mips64r2 |
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.set fp=64 |
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SET_HARDFLOAT |
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ldc1 $f1, THREAD_FPR1(\thread) |
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ldc1 $f3, THREAD_FPR3(\thread) |
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ldc1 $f5, THREAD_FPR5(\thread) |
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ldc1 $f7, THREAD_FPR7(\thread) |
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ldc1 $f9, THREAD_FPR9(\thread) |
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ldc1 $f11, THREAD_FPR11(\thread) |
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ldc1 $f13, THREAD_FPR13(\thread) |
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ldc1 $f15, THREAD_FPR15(\thread) |
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ldc1 $f17, THREAD_FPR17(\thread) |
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ldc1 $f19, THREAD_FPR19(\thread) |
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ldc1 $f21, THREAD_FPR21(\thread) |
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ldc1 $f23, THREAD_FPR23(\thread) |
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ldc1 $f25, THREAD_FPR25(\thread) |
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ldc1 $f27, THREAD_FPR27(\thread) |
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ldc1 $f29, THREAD_FPR29(\thread) |
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ldc1 $f31, THREAD_FPR31(\thread) |
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.set pop |
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.endm |
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.macro fpu_restore_double thread status tmp |
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#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPSR2) || \ |
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defined(CONFIG_CPU_MIPSR5) || defined(CONFIG_CPU_MIPSR6) |
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sll \tmp, \status, 5 |
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bgez \tmp, 10f # 16 register mode? |
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fpu_restore_16odd \thread |
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10: |
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#endif |
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fpu_restore_16even \thread \tmp |
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.endm |
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#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \ |
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defined(CONFIG_CPU_MIPSR6) |
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.macro _EXT rd, rs, p, s |
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ext \rd, \rs, \p, \s |
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.endm |
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#else /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */ |
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.macro _EXT rd, rs, p, s |
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srl \rd, \rs, \p |
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andi \rd, \rd, (1 << \s) - 1 |
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.endm |
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#endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR5 && !CONFIG_CPU_MIPSR6 */ |
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/* |
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* Temporary until all gas have MT ASE support |
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*/ |
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.macro DMT reg=0 |
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.word 0x41600bc1 | (\reg << 16) |
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.endm |
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.macro EMT reg=0 |
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.word 0x41600be1 | (\reg << 16) |
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.endm |
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.macro DVPE reg=0 |
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.word 0x41600001 | (\reg << 16) |
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.endm |
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.macro EVPE reg=0 |
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.word 0x41600021 | (\reg << 16) |
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.endm |
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.macro MFTR rt=0, rd=0, u=0, sel=0 |
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.word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) |
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.endm |
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.macro MTTR rt=0, rd=0, u=0, sel=0 |
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.word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) |
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.endm |
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#ifdef TOOLCHAIN_SUPPORTS_MSA |
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.macro _cfcmsa rd, cs |
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.set push |
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.set mips32r2 |
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.set fp=64 |
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.set msa |
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cfcmsa \rd, $\cs |
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.set pop |
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.endm |
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.macro _ctcmsa cd, rs |
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.set push |
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.set mips32r2 |
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.set fp=64 |
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.set msa |
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ctcmsa $\cd, \rs |
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.set pop |
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.endm |
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.macro ld_b wd, off, base |
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.set push |
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.set mips32r2 |
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.set fp=64 |
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.set msa |
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ld.b $w\wd, \off(\base) |
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.set pop |
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.endm |
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.macro ld_h wd, off, base |
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.set push |
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.set mips32r2 |
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.set fp=64 |
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.set msa |
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ld.h $w\wd, \off(\base) |
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.set pop |
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.endm |
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.macro ld_w wd, off, base |
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.set push |
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.set mips32r2 |
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.set fp=64 |
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.set msa |
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ld.w $w\wd, \off(\base) |
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.set pop |
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.endm |
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.macro ld_d wd, off, base |
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.set push |
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.set mips32r2 |
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.set fp=64 |
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.set msa |
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ld.d $w\wd, \off(\base) |
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.set pop |
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.endm |
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.macro st_b wd, off, base |
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.set push |
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.set mips32r2 |
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.set fp=64 |
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.set msa |
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st.b $w\wd, \off(\base) |
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.set pop |
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.endm |
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.macro st_h wd, off, base |
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.set push |
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.set mips32r2 |
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.set fp=64 |
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.set msa |
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st.h $w\wd, \off(\base) |
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.set pop |
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.endm |
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.macro st_w wd, off, base |
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.set push |
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.set mips32r2 |
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.set fp=64 |
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.set msa |
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st.w $w\wd, \off(\base) |
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.set pop |
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.endm |
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.macro st_d wd, off, base |
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.set push |
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.set mips32r2 |
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.set fp=64 |
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.set msa |
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st.d $w\wd, \off(\base) |
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.set pop |
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.endm |
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.macro copy_s_w ws, n |
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.set push |
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.set mips32r2 |
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.set fp=64 |
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.set msa |
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copy_s.w $1, $w\ws[\n] |
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.set pop |
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.endm |
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.macro copy_s_d ws, n |
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.set push |
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.set mips64r2 |
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.set fp=64 |
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.set msa |
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copy_s.d $1, $w\ws[\n] |
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.set pop |
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.endm |
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.macro insert_w wd, n |
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.set push |
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.set mips32r2 |
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.set fp=64 |
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.set msa |
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insert.w $w\wd[\n], $1 |
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.set pop |
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.endm |
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.macro insert_d wd, n |
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.set push |
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.set mips64r2 |
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.set fp=64 |
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.set msa |
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insert.d $w\wd[\n], $1 |
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.set pop |
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.endm |
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#else |
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/* |
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* Temporary until all toolchains in use include MSA support. |
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*/ |
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.macro _cfcmsa rd, cs |
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.set push |
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.set noat |
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SET_HARDFLOAT |
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insn_if_mips 0x787e0059 | (\cs << 11) |
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insn32_if_mm 0x587e0056 | (\cs << 11) |
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move \rd, $1 |
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.set pop |
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.endm |
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.macro _ctcmsa cd, rs |
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.set push |
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.set noat |
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SET_HARDFLOAT |
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move $1, \rs |
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insn_if_mips 0x783e0819 | (\cd << 6) |
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insn32_if_mm 0x583e0816 | (\cd << 6) |
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.set pop |
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.endm |
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.macro ld_b wd, off, base |
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.set push |
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.set noat |
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SET_HARDFLOAT |
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PTR_ADDU $1, \base, \off |
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insn_if_mips 0x78000820 | (\wd << 6) |
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insn32_if_mm 0x58000807 | (\wd << 6) |
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.set pop |
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.endm |
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.macro ld_h wd, off, base |
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.set push |
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.set noat |
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SET_HARDFLOAT |
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PTR_ADDU $1, \base, \off |
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insn_if_mips 0x78000821 | (\wd << 6) |
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insn32_if_mm 0x58000817 | (\wd << 6) |
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.set pop |
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.endm |
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.macro ld_w wd, off, base |
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.set push |
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.set noat |
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SET_HARDFLOAT |
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PTR_ADDU $1, \base, \off |
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insn_if_mips 0x78000822 | (\wd << 6) |
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insn32_if_mm 0x58000827 | (\wd << 6) |
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.set pop |
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.endm |
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.macro ld_d wd, off, base |
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.set push |
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.set noat |
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SET_HARDFLOAT |
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PTR_ADDU $1, \base, \off |
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insn_if_mips 0x78000823 | (\wd << 6) |
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insn32_if_mm 0x58000837 | (\wd << 6) |
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.set pop |
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.endm |
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.macro st_b wd, off, base |
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.set push |
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.set noat |
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SET_HARDFLOAT |
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PTR_ADDU $1, \base, \off |
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insn_if_mips 0x78000824 | (\wd << 6) |
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insn32_if_mm 0x5800080f | (\wd << 6) |
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.set pop |
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.endm |
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.macro st_h wd, off, base |
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.set push |
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.set noat |
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SET_HARDFLOAT |
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PTR_ADDU $1, \base, \off |
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insn_if_mips 0x78000825 | (\wd << 6) |
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insn32_if_mm 0x5800081f | (\wd << 6) |
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.set pop |
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.endm |
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.macro st_w wd, off, base |
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.set push |
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.set noat |
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SET_HARDFLOAT |
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PTR_ADDU $1, \base, \off |
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insn_if_mips 0x78000826 | (\wd << 6) |
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insn32_if_mm 0x5800082f | (\wd << 6) |
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.set pop |
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.endm |
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.macro st_d wd, off, base |
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.set push |
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.set noat |
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SET_HARDFLOAT |
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PTR_ADDU $1, \base, \off |
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insn_if_mips 0x78000827 | (\wd << 6) |
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insn32_if_mm 0x5800083f | (\wd << 6) |
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.set pop |
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.endm |
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.macro copy_s_w ws, n |
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.set push |
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.set noat |
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SET_HARDFLOAT |
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insn_if_mips 0x78b00059 | (\n << 16) | (\ws << 11) |
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insn32_if_mm 0x58b00056 | (\n << 16) | (\ws << 11) |
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.set pop |
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.endm |
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.macro copy_s_d ws, n |
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.set push |
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.set noat |
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SET_HARDFLOAT |
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insn_if_mips 0x78b80059 | (\n << 16) | (\ws << 11) |
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insn32_if_mm 0x58b80056 | (\n << 16) | (\ws << 11) |
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.set pop |
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.endm |
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.macro insert_w wd, n |
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.set push |
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.set noat |
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SET_HARDFLOAT |
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insn_if_mips 0x79300819 | (\n << 16) | (\wd << 6) |
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insn32_if_mm 0x59300816 | (\n << 16) | (\wd << 6) |
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.set pop |
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.endm |
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.macro insert_d wd, n |
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.set push |
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.set noat |
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SET_HARDFLOAT |
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insn_if_mips 0x79380819 | (\n << 16) | (\wd << 6) |
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insn32_if_mm 0x59380816 | (\n << 16) | (\wd << 6) |
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.set pop |
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.endm |
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#endif |
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#ifdef TOOLCHAIN_SUPPORTS_MSA |
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#define FPR_BASE_OFFS THREAD_FPR0 |
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#define FPR_BASE $1 |
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#else |
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#define FPR_BASE_OFFS 0 |
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#define FPR_BASE \thread |
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#endif |
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.macro msa_save_all thread |
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.set push |
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.set noat |
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#ifdef TOOLCHAIN_SUPPORTS_MSA |
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PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS |
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#endif |
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st_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE |
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st_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE |
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st_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE |
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st_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE |
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st_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE |
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st_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE |
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st_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE |
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st_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE |
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st_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE |
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st_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE |
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st_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE |
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st_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE |
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st_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE |
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st_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE |
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st_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE |
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st_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE |
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st_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE |
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st_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE |
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st_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE |
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st_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE |
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st_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE |
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st_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE |
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st_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE |
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st_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE |
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st_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE |
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st_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE |
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st_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE |
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st_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE |
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st_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE |
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st_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE |
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st_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE |
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st_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE |
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SET_HARDFLOAT |
|
_cfcmsa $1, MSA_CSR |
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sw $1, THREAD_MSA_CSR(\thread) |
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.set pop |
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.endm |
|
|
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.macro msa_restore_all thread |
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.set push |
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.set noat |
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SET_HARDFLOAT |
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lw $1, THREAD_MSA_CSR(\thread) |
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_ctcmsa MSA_CSR, $1 |
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#ifdef TOOLCHAIN_SUPPORTS_MSA |
|
PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS |
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#endif |
|
ld_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE |
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ld_d 1, THREAD_FPR1 - FPR_BASE_OFFS, FPR_BASE |
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ld_d 2, THREAD_FPR2 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 3, THREAD_FPR3 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 4, THREAD_FPR4 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 5, THREAD_FPR5 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 6, THREAD_FPR6 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 7, THREAD_FPR7 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 8, THREAD_FPR8 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 9, THREAD_FPR9 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 10, THREAD_FPR10 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 11, THREAD_FPR11 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 12, THREAD_FPR12 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 13, THREAD_FPR13 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 14, THREAD_FPR14 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 15, THREAD_FPR15 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 16, THREAD_FPR16 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 17, THREAD_FPR17 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 18, THREAD_FPR18 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 19, THREAD_FPR19 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 20, THREAD_FPR20 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 21, THREAD_FPR21 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 22, THREAD_FPR22 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 23, THREAD_FPR23 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 24, THREAD_FPR24 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 25, THREAD_FPR25 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 26, THREAD_FPR26 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 27, THREAD_FPR27 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 28, THREAD_FPR28 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 29, THREAD_FPR29 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 30, THREAD_FPR30 - FPR_BASE_OFFS, FPR_BASE |
|
ld_d 31, THREAD_FPR31 - FPR_BASE_OFFS, FPR_BASE |
|
.set pop |
|
.endm |
|
|
|
#undef FPR_BASE_OFFS |
|
#undef FPR_BASE |
|
|
|
.macro msa_init_upper wd |
|
#ifdef CONFIG_64BIT |
|
insert_d \wd, 1 |
|
#else |
|
insert_w \wd, 2 |
|
insert_w \wd, 3 |
|
#endif |
|
.endm |
|
|
|
.macro msa_init_all_upper |
|
.set push |
|
.set noat |
|
SET_HARDFLOAT |
|
not $1, zero |
|
msa_init_upper 0 |
|
msa_init_upper 1 |
|
msa_init_upper 2 |
|
msa_init_upper 3 |
|
msa_init_upper 4 |
|
msa_init_upper 5 |
|
msa_init_upper 6 |
|
msa_init_upper 7 |
|
msa_init_upper 8 |
|
msa_init_upper 9 |
|
msa_init_upper 10 |
|
msa_init_upper 11 |
|
msa_init_upper 12 |
|
msa_init_upper 13 |
|
msa_init_upper 14 |
|
msa_init_upper 15 |
|
msa_init_upper 16 |
|
msa_init_upper 17 |
|
msa_init_upper 18 |
|
msa_init_upper 19 |
|
msa_init_upper 20 |
|
msa_init_upper 21 |
|
msa_init_upper 22 |
|
msa_init_upper 23 |
|
msa_init_upper 24 |
|
msa_init_upper 25 |
|
msa_init_upper 26 |
|
msa_init_upper 27 |
|
msa_init_upper 28 |
|
msa_init_upper 29 |
|
msa_init_upper 30 |
|
msa_init_upper 31 |
|
.set pop |
|
.endm |
|
|
|
#endif /* _ASM_ASMMACRO_H */
|
|
|