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61 lines
1.6 KiB
61 lines
1.6 KiB
/* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 1996 David S. Miller ([email protected]) |
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* Compatibility with board caches, Ulf Carlsson |
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*/ |
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#include <linux/kernel.h> |
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#include <asm/sgialib.h> |
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#include <asm/bcache.h> |
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#include <asm/setup.h> |
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#if defined(CONFIG_64BIT) && defined(CONFIG_FW_ARC32) |
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/* |
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* For 64bit kernels working with a 32bit ARC PROM pointer arguments |
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* for ARC calls need to reside in CKEG0/1. But as soon as the kernel |
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* switches to it's first kernel thread stack is set to an address in |
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* XKPHYS, so anything on stack can't be used anymore. This is solved |
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* by using a * static declartion variables are put into BSS, which is |
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* linked to a CKSEG0 address. Since this is only used on UP platforms |
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* there is not spinlock needed |
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*/ |
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#define O32_STATIC static |
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#else |
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#define O32_STATIC |
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#endif |
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/* |
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* IP22 boardcache is not compatible with board caches. Thus we disable it |
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* during romvec action. Since r4xx0.c is always compiled and linked with your |
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* kernel, this shouldn't cause any harm regardless what MIPS processor you |
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* have. |
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* |
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* The ARC write and read functions seem to interfere with the serial lines |
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* in some way. You should be careful with them. |
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*/ |
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void prom_putchar(char c) |
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{ |
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O32_STATIC ULONG cnt; |
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O32_STATIC CHAR it; |
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it = c; |
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bc_disable(); |
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ArcWrite(1, &it, 1, &cnt); |
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bc_enable(); |
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} |
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char prom_getchar(void) |
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{ |
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O32_STATIC ULONG cnt; |
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O32_STATIC CHAR c; |
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bc_disable(); |
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ArcRead(0, &c, 1, &cnt); |
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bc_enable(); |
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return c; |
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}
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