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75 lines
1.6 KiB
75 lines
1.6 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* DECstation 5000/200 (KN02) Control and Status Register |
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* interrupts. |
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* |
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* Copyright (c) 2002, 2003, 2005 Maciej W. Rozycki |
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*/ |
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#include <linux/init.h> |
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#include <linux/irq.h> |
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#include <linux/types.h> |
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#include <asm/dec/kn02.h> |
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/* |
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* Bits 7:0 of the Control Register are write-only -- the |
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* corresponding bits of the Status Register have a different |
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* meaning. Hence we use a cache. It speeds up things a bit |
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* as well. |
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* |
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* There is no default value -- it has to be initialized. |
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*/ |
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u32 cached_kn02_csr; |
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static int kn02_irq_base; |
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static void unmask_kn02_irq(struct irq_data *d) |
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{ |
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volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + |
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KN02_CSR); |
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cached_kn02_csr |= (1 << (d->irq - kn02_irq_base + 16)); |
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*csr = cached_kn02_csr; |
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} |
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static void mask_kn02_irq(struct irq_data *d) |
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{ |
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volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + |
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KN02_CSR); |
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cached_kn02_csr &= ~(1 << (d->irq - kn02_irq_base + 16)); |
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*csr = cached_kn02_csr; |
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} |
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static void ack_kn02_irq(struct irq_data *d) |
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{ |
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mask_kn02_irq(d); |
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iob(); |
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} |
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static struct irq_chip kn02_irq_type = { |
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.name = "KN02-CSR", |
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.irq_ack = ack_kn02_irq, |
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.irq_mask = mask_kn02_irq, |
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.irq_mask_ack = ack_kn02_irq, |
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.irq_unmask = unmask_kn02_irq, |
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}; |
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void __init init_kn02_irqs(int base) |
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{ |
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volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + |
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KN02_CSR); |
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int i; |
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/* Mask interrupts. */ |
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cached_kn02_csr &= ~KN02_CSR_IOINTEN; |
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*csr = cached_kn02_csr; |
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iob(); |
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for (i = base; i < base + KN02_IRQ_LINES; i++) |
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irq_set_chip_and_handler(i, &kn02_irq_type, handle_level_irq); |
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kn02_irq_base = base; |
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}
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