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668 lines
22 KiB
668 lines
22 KiB
/***********************license start*************** |
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* Author: Cavium Networks |
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* |
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* Contact: [email protected] |
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* This file is part of the OCTEON SDK |
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* |
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* Copyright (c) 2003-2008 Cavium Networks |
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* |
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* This file is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License, Version 2, as |
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* published by the Free Software Foundation. |
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* |
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* This file is distributed in the hope that it will be useful, but |
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty |
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or |
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* NONINFRINGEMENT. See the GNU General Public License for more |
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* details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this file; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
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* or visit http://www.gnu.org/licenses/. |
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* |
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* This file may also be available under a different license from Cavium. |
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* Contact Cavium Networks for more information |
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***********************license end**************************************/ |
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|
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/* |
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* |
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* Support library for the SPI |
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*/ |
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#include <asm/octeon/octeon.h> |
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#include <asm/octeon/cvmx-config.h> |
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#include <asm/octeon/cvmx-pko.h> |
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#include <asm/octeon/cvmx-spi.h> |
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#include <asm/octeon/cvmx-spxx-defs.h> |
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#include <asm/octeon/cvmx-stxx-defs.h> |
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#include <asm/octeon/cvmx-srxx-defs.h> |
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#define INVOKE_CB(function_p, args...) \ |
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do { \ |
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if (function_p) { \ |
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res = function_p(args); \ |
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if (res) \ |
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return res; \ |
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} \ |
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} while (0) |
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#if CVMX_ENABLE_DEBUG_PRINTS |
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static const char *modes[] = |
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{ "UNKNOWN", "TX Halfplex", "Rx Halfplex", "Duplex" }; |
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#endif |
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/* Default callbacks, can be overridden |
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* using cvmx_spi_get_callbacks/cvmx_spi_set_callbacks |
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*/ |
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static cvmx_spi_callbacks_t cvmx_spi_callbacks = { |
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.reset_cb = cvmx_spi_reset_cb, |
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.calendar_setup_cb = cvmx_spi_calendar_setup_cb, |
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.clock_detect_cb = cvmx_spi_clock_detect_cb, |
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.training_cb = cvmx_spi_training_cb, |
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.calendar_sync_cb = cvmx_spi_calendar_sync_cb, |
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.interface_up_cb = cvmx_spi_interface_up_cb |
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}; |
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/** |
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* Get current SPI4 initialization callbacks |
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* |
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* @callbacks: Pointer to the callbacks structure.to fill |
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* |
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* Returns Pointer to cvmx_spi_callbacks_t structure. |
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*/ |
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void cvmx_spi_get_callbacks(cvmx_spi_callbacks_t *callbacks) |
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{ |
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memcpy(callbacks, &cvmx_spi_callbacks, sizeof(cvmx_spi_callbacks)); |
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} |
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/** |
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* Set new SPI4 initialization callbacks |
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* |
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* @new_callbacks: Pointer to an updated callbacks structure. |
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*/ |
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void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks) |
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{ |
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memcpy(&cvmx_spi_callbacks, new_callbacks, sizeof(cvmx_spi_callbacks)); |
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} |
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/** |
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* Initialize and start the SPI interface. |
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* |
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* @interface: The identifier of the packet interface to configure and |
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* use as a SPI interface. |
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* @mode: The operating mode for the SPI interface. The interface |
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* can operate as a full duplex (both Tx and Rx data paths |
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* active) or as a halfplex (either the Tx data path is |
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* active or the Rx data path is active, but not both). |
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* @timeout: Timeout to wait for clock synchronization in seconds |
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* @num_ports: Number of SPI ports to configure |
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* |
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* Returns Zero on success, negative of failure. |
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*/ |
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int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode, int timeout, |
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int num_ports) |
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{ |
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int res = -1; |
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if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) |
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return res; |
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/* Callback to perform SPI4 reset */ |
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INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface, mode); |
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/* Callback to perform calendar setup */ |
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INVOKE_CB(cvmx_spi_callbacks.calendar_setup_cb, interface, mode, |
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num_ports); |
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/* Callback to perform clock detection */ |
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INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout); |
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/* Callback to perform SPI4 link training */ |
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INVOKE_CB(cvmx_spi_callbacks.training_cb, interface, mode, timeout); |
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/* Callback to perform calendar sync */ |
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INVOKE_CB(cvmx_spi_callbacks.calendar_sync_cb, interface, mode, |
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timeout); |
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/* Callback to handle interface coming up */ |
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INVOKE_CB(cvmx_spi_callbacks.interface_up_cb, interface, mode); |
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return res; |
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} |
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/** |
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* This routine restarts the SPI interface after it has lost synchronization |
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* with its correspondent system. |
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* |
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* @interface: The identifier of the packet interface to configure and |
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* use as a SPI interface. |
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* @mode: The operating mode for the SPI interface. The interface |
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* can operate as a full duplex (both Tx and Rx data paths |
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* active) or as a halfplex (either the Tx data path is |
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* active or the Rx data path is active, but not both). |
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* @timeout: Timeout to wait for clock synchronization in seconds |
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* |
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* Returns Zero on success, negative of failure. |
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*/ |
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int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout) |
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{ |
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int res = -1; |
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if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) |
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return res; |
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cvmx_dprintf("SPI%d: Restart %s\n", interface, modes[mode]); |
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/* Callback to perform SPI4 reset */ |
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INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface, mode); |
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/* NOTE: Calendar setup is not performed during restart */ |
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/* Refer to cvmx_spi_start_interface() for the full sequence */ |
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/* Callback to perform clock detection */ |
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INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout); |
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/* Callback to perform SPI4 link training */ |
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INVOKE_CB(cvmx_spi_callbacks.training_cb, interface, mode, timeout); |
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/* Callback to perform calendar sync */ |
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INVOKE_CB(cvmx_spi_callbacks.calendar_sync_cb, interface, mode, |
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timeout); |
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/* Callback to handle interface coming up */ |
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INVOKE_CB(cvmx_spi_callbacks.interface_up_cb, interface, mode); |
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return res; |
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} |
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EXPORT_SYMBOL_GPL(cvmx_spi_restart_interface); |
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/** |
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* Callback to perform SPI4 reset |
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* |
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* @interface: The identifier of the packet interface to configure and |
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* use as a SPI interface. |
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* @mode: The operating mode for the SPI interface. The interface |
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* can operate as a full duplex (both Tx and Rx data paths |
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* active) or as a halfplex (either the Tx data path is |
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* active or the Rx data path is active, but not both). |
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* |
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* Returns Zero on success, non-zero error code on failure (will cause |
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* SPI initialization to abort) |
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*/ |
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int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode) |
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{ |
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union cvmx_spxx_dbg_deskew_ctl spxx_dbg_deskew_ctl; |
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union cvmx_spxx_clk_ctl spxx_clk_ctl; |
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union cvmx_spxx_bist_stat spxx_bist_stat; |
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union cvmx_spxx_int_msk spxx_int_msk; |
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union cvmx_stxx_int_msk stxx_int_msk; |
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union cvmx_spxx_trn4_ctl spxx_trn4_ctl; |
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int index; |
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uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; |
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/* Disable SPI error events while we run BIST */ |
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spxx_int_msk.u64 = cvmx_read_csr(CVMX_SPXX_INT_MSK(interface)); |
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cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0); |
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stxx_int_msk.u64 = cvmx_read_csr(CVMX_STXX_INT_MSK(interface)); |
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cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0); |
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/* Run BIST in the SPI interface */ |
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cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), 0); |
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cvmx_write_csr(CVMX_STXX_COM_CTL(interface), 0); |
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spxx_clk_ctl.u64 = 0; |
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spxx_clk_ctl.s.runbist = 1; |
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cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); |
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__delay(10 * MS); |
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spxx_bist_stat.u64 = cvmx_read_csr(CVMX_SPXX_BIST_STAT(interface)); |
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if (spxx_bist_stat.s.stat0) |
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cvmx_dprintf |
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("ERROR SPI%d: BIST failed on receive datapath FIFO\n", |
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interface); |
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if (spxx_bist_stat.s.stat1) |
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cvmx_dprintf("ERROR SPI%d: BIST failed on RX calendar table\n", |
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interface); |
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if (spxx_bist_stat.s.stat2) |
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cvmx_dprintf("ERROR SPI%d: BIST failed on TX calendar table\n", |
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interface); |
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/* Clear the calendar table after BIST to fix parity errors */ |
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for (index = 0; index < 32; index++) { |
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union cvmx_srxx_spi4_calx srxx_spi4_calx; |
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union cvmx_stxx_spi4_calx stxx_spi4_calx; |
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srxx_spi4_calx.u64 = 0; |
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srxx_spi4_calx.s.oddpar = 1; |
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cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface), |
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srxx_spi4_calx.u64); |
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stxx_spi4_calx.u64 = 0; |
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stxx_spi4_calx.s.oddpar = 1; |
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cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface), |
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stxx_spi4_calx.u64); |
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} |
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/* Re enable reporting of error interrupts */ |
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cvmx_write_csr(CVMX_SPXX_INT_REG(interface), |
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cvmx_read_csr(CVMX_SPXX_INT_REG(interface))); |
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cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), spxx_int_msk.u64); |
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cvmx_write_csr(CVMX_STXX_INT_REG(interface), |
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cvmx_read_csr(CVMX_STXX_INT_REG(interface))); |
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cvmx_write_csr(CVMX_STXX_INT_MSK(interface), stxx_int_msk.u64); |
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/* Setup the CLKDLY right in the middle */ |
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spxx_clk_ctl.u64 = 0; |
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spxx_clk_ctl.s.seetrn = 0; |
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spxx_clk_ctl.s.clkdly = 0x10; |
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spxx_clk_ctl.s.runbist = 0; |
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spxx_clk_ctl.s.statdrv = 0; |
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/* This should always be on the opposite edge as statdrv */ |
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spxx_clk_ctl.s.statrcv = 1; |
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spxx_clk_ctl.s.sndtrn = 0; |
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spxx_clk_ctl.s.drptrn = 0; |
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spxx_clk_ctl.s.rcvtrn = 0; |
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spxx_clk_ctl.s.srxdlck = 0; |
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cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); |
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__delay(100 * MS); |
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/* Reset SRX0 DLL */ |
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spxx_clk_ctl.s.srxdlck = 1; |
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cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); |
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/* Waiting for Inf0 Spi4 RX DLL to lock */ |
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__delay(100 * MS); |
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/* Enable dynamic alignment */ |
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spxx_trn4_ctl.s.trntest = 0; |
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spxx_trn4_ctl.s.jitter = 1; |
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spxx_trn4_ctl.s.clr_boot = 1; |
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spxx_trn4_ctl.s.set_boot = 0; |
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if (OCTEON_IS_MODEL(OCTEON_CN58XX)) |
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spxx_trn4_ctl.s.maxdist = 3; |
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else |
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spxx_trn4_ctl.s.maxdist = 8; |
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spxx_trn4_ctl.s.macro_en = 1; |
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spxx_trn4_ctl.s.mux_en = 1; |
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cvmx_write_csr(CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64); |
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spxx_dbg_deskew_ctl.u64 = 0; |
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cvmx_write_csr(CVMX_SPXX_DBG_DESKEW_CTL(interface), |
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spxx_dbg_deskew_ctl.u64); |
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return 0; |
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} |
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/** |
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* Callback to setup calendar and miscellaneous settings before clock detection |
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* |
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* @interface: The identifier of the packet interface to configure and |
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* use as a SPI interface. |
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* @mode: The operating mode for the SPI interface. The interface |
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* can operate as a full duplex (both Tx and Rx data paths |
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* active) or as a halfplex (either the Tx data path is |
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* active or the Rx data path is active, but not both). |
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* @num_ports: Number of ports to configure on SPI |
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* |
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* Returns Zero on success, non-zero error code on failure (will cause |
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* SPI initialization to abort) |
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*/ |
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int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode, |
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int num_ports) |
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{ |
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int port; |
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int index; |
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if (mode & CVMX_SPI_MODE_RX_HALFPLEX) { |
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union cvmx_srxx_com_ctl srxx_com_ctl; |
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union cvmx_srxx_spi4_stat srxx_spi4_stat; |
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/* SRX0 number of Ports */ |
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srxx_com_ctl.u64 = 0; |
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srxx_com_ctl.s.prts = num_ports - 1; |
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srxx_com_ctl.s.st_en = 0; |
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srxx_com_ctl.s.inf_en = 0; |
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cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64); |
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/* SRX0 Calendar Table. This round robbins through all ports */ |
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port = 0; |
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index = 0; |
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while (port < num_ports) { |
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union cvmx_srxx_spi4_calx srxx_spi4_calx; |
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srxx_spi4_calx.u64 = 0; |
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srxx_spi4_calx.s.prt0 = port++; |
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srxx_spi4_calx.s.prt1 = port++; |
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srxx_spi4_calx.s.prt2 = port++; |
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srxx_spi4_calx.s.prt3 = port++; |
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srxx_spi4_calx.s.oddpar = |
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~(cvmx_dpop(srxx_spi4_calx.u64) & 1); |
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cvmx_write_csr(CVMX_SRXX_SPI4_CALX(index, interface), |
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srxx_spi4_calx.u64); |
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index++; |
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} |
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srxx_spi4_stat.u64 = 0; |
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srxx_spi4_stat.s.len = num_ports; |
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srxx_spi4_stat.s.m = 1; |
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cvmx_write_csr(CVMX_SRXX_SPI4_STAT(interface), |
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srxx_spi4_stat.u64); |
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} |
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if (mode & CVMX_SPI_MODE_TX_HALFPLEX) { |
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union cvmx_stxx_arb_ctl stxx_arb_ctl; |
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union cvmx_gmxx_tx_spi_max gmxx_tx_spi_max; |
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union cvmx_gmxx_tx_spi_thresh gmxx_tx_spi_thresh; |
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union cvmx_gmxx_tx_spi_ctl gmxx_tx_spi_ctl; |
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union cvmx_stxx_spi4_stat stxx_spi4_stat; |
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union cvmx_stxx_spi4_dat stxx_spi4_dat; |
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/* STX0 Config */ |
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stxx_arb_ctl.u64 = 0; |
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stxx_arb_ctl.s.igntpa = 0; |
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stxx_arb_ctl.s.mintrn = 0; |
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cvmx_write_csr(CVMX_STXX_ARB_CTL(interface), stxx_arb_ctl.u64); |
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gmxx_tx_spi_max.u64 = 0; |
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gmxx_tx_spi_max.s.max1 = 8; |
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gmxx_tx_spi_max.s.max2 = 4; |
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gmxx_tx_spi_max.s.slice = 0; |
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cvmx_write_csr(CVMX_GMXX_TX_SPI_MAX(interface), |
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gmxx_tx_spi_max.u64); |
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gmxx_tx_spi_thresh.u64 = 0; |
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gmxx_tx_spi_thresh.s.thresh = 4; |
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cvmx_write_csr(CVMX_GMXX_TX_SPI_THRESH(interface), |
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gmxx_tx_spi_thresh.u64); |
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|
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gmxx_tx_spi_ctl.u64 = 0; |
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gmxx_tx_spi_ctl.s.tpa_clr = 0; |
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gmxx_tx_spi_ctl.s.cont_pkt = 0; |
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cvmx_write_csr(CVMX_GMXX_TX_SPI_CTL(interface), |
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gmxx_tx_spi_ctl.u64); |
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|
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/* STX0 Training Control */ |
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stxx_spi4_dat.u64 = 0; |
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/*Minimum needed by dynamic alignment */ |
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stxx_spi4_dat.s.alpha = 32; |
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stxx_spi4_dat.s.max_t = 0xFFFF; /*Minimum interval is 0x20 */ |
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cvmx_write_csr(CVMX_STXX_SPI4_DAT(interface), |
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stxx_spi4_dat.u64); |
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|
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/* STX0 Calendar Table. This round robbins through all ports */ |
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port = 0; |
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index = 0; |
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while (port < num_ports) { |
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union cvmx_stxx_spi4_calx stxx_spi4_calx; |
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stxx_spi4_calx.u64 = 0; |
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stxx_spi4_calx.s.prt0 = port++; |
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stxx_spi4_calx.s.prt1 = port++; |
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stxx_spi4_calx.s.prt2 = port++; |
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stxx_spi4_calx.s.prt3 = port++; |
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stxx_spi4_calx.s.oddpar = |
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~(cvmx_dpop(stxx_spi4_calx.u64) & 1); |
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cvmx_write_csr(CVMX_STXX_SPI4_CALX(index, interface), |
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stxx_spi4_calx.u64); |
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index++; |
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} |
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stxx_spi4_stat.u64 = 0; |
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stxx_spi4_stat.s.len = num_ports; |
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stxx_spi4_stat.s.m = 1; |
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cvmx_write_csr(CVMX_STXX_SPI4_STAT(interface), |
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stxx_spi4_stat.u64); |
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} |
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|
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return 0; |
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} |
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|
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/** |
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* Callback to perform clock detection |
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* |
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* @interface: The identifier of the packet interface to configure and |
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* use as a SPI interface. |
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* @mode: The operating mode for the SPI interface. The interface |
|
* can operate as a full duplex (both Tx and Rx data paths |
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* active) or as a halfplex (either the Tx data path is |
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* active or the Rx data path is active, but not both). |
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* @timeout: Timeout to wait for clock synchronization in seconds |
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* |
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* Returns Zero on success, non-zero error code on failure (will cause |
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* SPI initialization to abort) |
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*/ |
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int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode, int timeout) |
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{ |
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int clock_transitions; |
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union cvmx_spxx_clk_stat stat; |
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uint64_t timeout_time; |
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uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; |
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|
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/* |
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* Regardless of operating mode, both Tx and Rx clocks must be |
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* present for the SPI interface to operate. |
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*/ |
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cvmx_dprintf("SPI%d: Waiting to see TsClk...\n", interface); |
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timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout; |
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/* |
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* Require 100 clock transitions in order to avoid any noise |
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* in the beginning. |
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*/ |
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clock_transitions = 100; |
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do { |
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stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); |
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if (stat.s.s4clk0 && stat.s.s4clk1 && clock_transitions) { |
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/* |
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* We've seen a clock transition, so decrement |
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* the number we still need. |
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*/ |
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clock_transitions--; |
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cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64); |
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stat.s.s4clk0 = 0; |
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stat.s.s4clk1 = 0; |
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} |
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if (cvmx_get_cycle() > timeout_time) { |
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cvmx_dprintf("SPI%d: Timeout\n", interface); |
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return -1; |
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} |
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} while (stat.s.s4clk0 == 0 || stat.s.s4clk1 == 0); |
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|
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cvmx_dprintf("SPI%d: Waiting to see RsClk...\n", interface); |
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timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout; |
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/* |
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* Require 100 clock transitions in order to avoid any noise in the |
|
* beginning. |
|
*/ |
|
clock_transitions = 100; |
|
do { |
|
stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); |
|
if (stat.s.d4clk0 && stat.s.d4clk1 && clock_transitions) { |
|
/* |
|
* We've seen a clock transition, so decrement |
|
* the number we still need |
|
*/ |
|
clock_transitions--; |
|
cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64); |
|
stat.s.d4clk0 = 0; |
|
stat.s.d4clk1 = 0; |
|
} |
|
if (cvmx_get_cycle() > timeout_time) { |
|
cvmx_dprintf("SPI%d: Timeout\n", interface); |
|
return -1; |
|
} |
|
} while (stat.s.d4clk0 == 0 || stat.s.d4clk1 == 0); |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* Callback to perform link training |
|
* |
|
* @interface: The identifier of the packet interface to configure and |
|
* use as a SPI interface. |
|
* @mode: The operating mode for the SPI interface. The interface |
|
* can operate as a full duplex (both Tx and Rx data paths |
|
* active) or as a halfplex (either the Tx data path is |
|
* active or the Rx data path is active, but not both). |
|
* @timeout: Timeout to wait for link to be trained (in seconds) |
|
* |
|
* Returns Zero on success, non-zero error code on failure (will cause |
|
* SPI initialization to abort) |
|
*/ |
|
int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout) |
|
{ |
|
union cvmx_spxx_trn4_ctl spxx_trn4_ctl; |
|
union cvmx_spxx_clk_stat stat; |
|
uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; |
|
uint64_t timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout; |
|
int rx_training_needed; |
|
|
|
/* SRX0 & STX0 Inf0 Links are configured - begin training */ |
|
union cvmx_spxx_clk_ctl spxx_clk_ctl; |
|
spxx_clk_ctl.u64 = 0; |
|
spxx_clk_ctl.s.seetrn = 0; |
|
spxx_clk_ctl.s.clkdly = 0x10; |
|
spxx_clk_ctl.s.runbist = 0; |
|
spxx_clk_ctl.s.statdrv = 0; |
|
/* This should always be on the opposite edge as statdrv */ |
|
spxx_clk_ctl.s.statrcv = 1; |
|
spxx_clk_ctl.s.sndtrn = 1; |
|
spxx_clk_ctl.s.drptrn = 1; |
|
spxx_clk_ctl.s.rcvtrn = 1; |
|
spxx_clk_ctl.s.srxdlck = 1; |
|
cvmx_write_csr(CVMX_SPXX_CLK_CTL(interface), spxx_clk_ctl.u64); |
|
__delay(1000 * MS); |
|
|
|
/* SRX0 clear the boot bit */ |
|
spxx_trn4_ctl.u64 = cvmx_read_csr(CVMX_SPXX_TRN4_CTL(interface)); |
|
spxx_trn4_ctl.s.clr_boot = 1; |
|
cvmx_write_csr(CVMX_SPXX_TRN4_CTL(interface), spxx_trn4_ctl.u64); |
|
|
|
/* Wait for the training sequence to complete */ |
|
cvmx_dprintf("SPI%d: Waiting for training\n", interface); |
|
__delay(1000 * MS); |
|
/* Wait a really long time here */ |
|
timeout_time = cvmx_get_cycle() + 1000ull * MS * 600; |
|
/* |
|
* The HRM says we must wait for 34 + 16 * MAXDIST training sequences. |
|
* We'll be pessimistic and wait for a lot more. |
|
*/ |
|
rx_training_needed = 500; |
|
do { |
|
stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); |
|
if (stat.s.srxtrn && rx_training_needed) { |
|
rx_training_needed--; |
|
cvmx_write_csr(CVMX_SPXX_CLK_STAT(interface), stat.u64); |
|
stat.s.srxtrn = 0; |
|
} |
|
if (cvmx_get_cycle() > timeout_time) { |
|
cvmx_dprintf("SPI%d: Timeout\n", interface); |
|
return -1; |
|
} |
|
} while (stat.s.srxtrn == 0); |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* Callback to perform calendar data synchronization |
|
* |
|
* @interface: The identifier of the packet interface to configure and |
|
* use as a SPI interface. |
|
* @mode: The operating mode for the SPI interface. The interface |
|
* can operate as a full duplex (both Tx and Rx data paths |
|
* active) or as a halfplex (either the Tx data path is |
|
* active or the Rx data path is active, but not both). |
|
* @timeout: Timeout to wait for calendar data in seconds |
|
* |
|
* Returns Zero on success, non-zero error code on failure (will cause |
|
* SPI initialization to abort) |
|
*/ |
|
int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, int timeout) |
|
{ |
|
uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; |
|
if (mode & CVMX_SPI_MODE_RX_HALFPLEX) { |
|
/* SRX0 interface should be good, send calendar data */ |
|
union cvmx_srxx_com_ctl srxx_com_ctl; |
|
cvmx_dprintf |
|
("SPI%d: Rx is synchronized, start sending calendar data\n", |
|
interface); |
|
srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface)); |
|
srxx_com_ctl.s.inf_en = 1; |
|
srxx_com_ctl.s.st_en = 1; |
|
cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64); |
|
} |
|
|
|
if (mode & CVMX_SPI_MODE_TX_HALFPLEX) { |
|
/* STX0 has achieved sync */ |
|
/* The corespondant board should be sending calendar data */ |
|
/* Enable the STX0 STAT receiver. */ |
|
union cvmx_spxx_clk_stat stat; |
|
uint64_t timeout_time; |
|
union cvmx_stxx_com_ctl stxx_com_ctl; |
|
stxx_com_ctl.u64 = 0; |
|
stxx_com_ctl.s.st_en = 1; |
|
cvmx_write_csr(CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64); |
|
|
|
/* Waiting for calendar sync on STX0 STAT */ |
|
cvmx_dprintf("SPI%d: Waiting to sync on STX[%d] STAT\n", |
|
interface, interface); |
|
timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout; |
|
/* SPX0_CLK_STAT - SPX0_CLK_STAT[STXCAL] should be 1 (bit10) */ |
|
do { |
|
stat.u64 = cvmx_read_csr(CVMX_SPXX_CLK_STAT(interface)); |
|
if (cvmx_get_cycle() > timeout_time) { |
|
cvmx_dprintf("SPI%d: Timeout\n", interface); |
|
return -1; |
|
} |
|
} while (stat.s.stxcal == 0); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
/** |
|
* Callback to handle interface up |
|
* |
|
* @interface: The identifier of the packet interface to configure and |
|
* use as a SPI interface. |
|
* @mode: The operating mode for the SPI interface. The interface |
|
* can operate as a full duplex (both Tx and Rx data paths |
|
* active) or as a halfplex (either the Tx data path is |
|
* active or the Rx data path is active, but not both). |
|
* |
|
* Returns Zero on success, non-zero error code on failure (will cause |
|
* SPI initialization to abort) |
|
*/ |
|
int cvmx_spi_interface_up_cb(int interface, cvmx_spi_mode_t mode) |
|
{ |
|
union cvmx_gmxx_rxx_frm_min gmxx_rxx_frm_min; |
|
union cvmx_gmxx_rxx_frm_max gmxx_rxx_frm_max; |
|
union cvmx_gmxx_rxx_jabber gmxx_rxx_jabber; |
|
|
|
if (mode & CVMX_SPI_MODE_RX_HALFPLEX) { |
|
union cvmx_srxx_com_ctl srxx_com_ctl; |
|
srxx_com_ctl.u64 = cvmx_read_csr(CVMX_SRXX_COM_CTL(interface)); |
|
srxx_com_ctl.s.inf_en = 1; |
|
cvmx_write_csr(CVMX_SRXX_COM_CTL(interface), srxx_com_ctl.u64); |
|
cvmx_dprintf("SPI%d: Rx is now up\n", interface); |
|
} |
|
|
|
if (mode & CVMX_SPI_MODE_TX_HALFPLEX) { |
|
union cvmx_stxx_com_ctl stxx_com_ctl; |
|
stxx_com_ctl.u64 = cvmx_read_csr(CVMX_STXX_COM_CTL(interface)); |
|
stxx_com_ctl.s.inf_en = 1; |
|
cvmx_write_csr(CVMX_STXX_COM_CTL(interface), stxx_com_ctl.u64); |
|
cvmx_dprintf("SPI%d: Tx is now up\n", interface); |
|
} |
|
|
|
gmxx_rxx_frm_min.u64 = 0; |
|
gmxx_rxx_frm_min.s.len = 64; |
|
cvmx_write_csr(CVMX_GMXX_RXX_FRM_MIN(0, interface), |
|
gmxx_rxx_frm_min.u64); |
|
gmxx_rxx_frm_max.u64 = 0; |
|
gmxx_rxx_frm_max.s.len = 64 * 1024 - 4; |
|
cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX(0, interface), |
|
gmxx_rxx_frm_max.u64); |
|
gmxx_rxx_jabber.u64 = 0; |
|
gmxx_rxx_jabber.s.cnt = 64 * 1024 - 4; |
|
cvmx_write_csr(CVMX_GMXX_RXX_JABBER(0, interface), gmxx_rxx_jabber.u64); |
|
|
|
return 0; |
|
}
|
|
|