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1117 lines
31 KiB
1117 lines
31 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Contains common pci routines for ALL ppc platform |
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* (based on pci_32.c and pci_64.c) |
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* |
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* Port for PPC64 David Engebretsen, IBM Corp. |
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* Contains common pci routines for ppc64 platform, pSeries and iSeries brands. |
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* |
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* Copyright (C) 2003 Anton Blanchard <[email protected]>, IBM |
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* Rework, based on alpha PCI code. |
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* |
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* Common pmac/prep/chrp pci routines. -- Cort |
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*/ |
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|
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#include <linux/kernel.h> |
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#include <linux/pci.h> |
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#include <linux/string.h> |
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#include <linux/init.h> |
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#include <linux/memblock.h> |
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#include <linux/mm.h> |
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#include <linux/shmem_fs.h> |
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#include <linux/list.h> |
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#include <linux/syscalls.h> |
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#include <linux/irq.h> |
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#include <linux/vmalloc.h> |
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#include <linux/slab.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_pci.h> |
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#include <linux/export.h> |
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|
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#include <asm/processor.h> |
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#include <linux/io.h> |
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#include <asm/pci-bridge.h> |
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#include <asm/byteorder.h> |
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|
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static DEFINE_SPINLOCK(hose_spinlock); |
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LIST_HEAD(hose_list); |
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|
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/* XXX kill that some day ... */ |
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static int global_phb_number; /* Global phb counter */ |
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|
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/* ISA Memory physical address */ |
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resource_size_t isa_mem_base; |
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|
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unsigned long isa_io_base; |
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EXPORT_SYMBOL(isa_io_base); |
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|
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static int pci_bus_count; |
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|
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struct pci_controller *pcibios_alloc_controller(struct device_node *dev) |
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{ |
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struct pci_controller *phb; |
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|
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phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL); |
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if (!phb) |
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return NULL; |
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spin_lock(&hose_spinlock); |
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phb->global_number = global_phb_number++; |
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list_add_tail(&phb->list_node, &hose_list); |
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spin_unlock(&hose_spinlock); |
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phb->dn = dev; |
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phb->is_dynamic = mem_init_done; |
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return phb; |
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} |
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|
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void pcibios_free_controller(struct pci_controller *phb) |
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{ |
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spin_lock(&hose_spinlock); |
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list_del(&phb->list_node); |
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spin_unlock(&hose_spinlock); |
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|
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if (phb->is_dynamic) |
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kfree(phb); |
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} |
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|
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static resource_size_t pcibios_io_size(const struct pci_controller *hose) |
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{ |
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return resource_size(&hose->io_resource); |
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} |
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|
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int pcibios_vaddr_is_ioport(void __iomem *address) |
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{ |
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int ret = 0; |
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struct pci_controller *hose; |
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resource_size_t size; |
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|
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spin_lock(&hose_spinlock); |
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list_for_each_entry(hose, &hose_list, list_node) { |
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size = pcibios_io_size(hose); |
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if (address >= hose->io_base_virt && |
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address < (hose->io_base_virt + size)) { |
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ret = 1; |
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break; |
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} |
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} |
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spin_unlock(&hose_spinlock); |
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return ret; |
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} |
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|
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unsigned long pci_address_to_pio(phys_addr_t address) |
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{ |
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struct pci_controller *hose; |
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resource_size_t size; |
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unsigned long ret = ~0; |
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spin_lock(&hose_spinlock); |
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list_for_each_entry(hose, &hose_list, list_node) { |
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size = pcibios_io_size(hose); |
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if (address >= hose->io_base_phys && |
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address < (hose->io_base_phys + size)) { |
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unsigned long base = |
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(unsigned long)hose->io_base_virt - _IO_BASE; |
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ret = base + (address - hose->io_base_phys); |
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break; |
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} |
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} |
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spin_unlock(&hose_spinlock); |
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|
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return ret; |
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} |
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EXPORT_SYMBOL_GPL(pci_address_to_pio); |
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|
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/* This routine is meant to be used early during boot, when the |
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* PCI bus numbers have not yet been assigned, and you need to |
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* issue PCI config cycles to an OF device. |
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* It could also be used to "fix" RTAS config cycles if you want |
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* to set pci_assign_all_buses to 1 and still use RTAS for PCI |
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* config cycles. |
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*/ |
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struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node) |
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{ |
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while (node) { |
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struct pci_controller *hose, *tmp; |
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list_for_each_entry_safe(hose, tmp, &hose_list, list_node) |
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if (hose->dn == node) |
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return hose; |
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node = node->parent; |
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} |
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return NULL; |
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} |
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void pcibios_set_master(struct pci_dev *dev) |
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{ |
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/* No special bus mastering setup handling */ |
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} |
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|
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/* |
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* Platform support for /proc/bus/pci/X/Y mmap()s. |
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*/ |
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int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma) |
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{ |
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struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
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resource_size_t ioaddr = pci_resource_start(pdev, bar); |
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|
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if (!hose) |
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return -EINVAL; /* should never happen */ |
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|
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/* Convert to an offset within this PCI controller */ |
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ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE; |
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vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT; |
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return 0; |
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} |
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|
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/* |
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* This one is used by /dev/mem and fbdev who have no clue about the |
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* PCI device, it tries to find the PCI device first and calls the |
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* above routine |
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*/ |
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pgprot_t pci_phys_mem_access_prot(struct file *file, |
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unsigned long pfn, |
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unsigned long size, |
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pgprot_t prot) |
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{ |
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struct pci_dev *pdev = NULL; |
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struct resource *found = NULL; |
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resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT; |
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int i; |
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|
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if (page_is_ram(pfn)) |
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return prot; |
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prot = pgprot_noncached(prot); |
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for_each_pci_dev(pdev) { |
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for (i = 0; i <= PCI_ROM_RESOURCE; i++) { |
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struct resource *rp = &pdev->resource[i]; |
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int flags = rp->flags; |
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|
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/* Active and same type? */ |
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if ((flags & IORESOURCE_MEM) == 0) |
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continue; |
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/* In the range of this resource? */ |
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if (offset < (rp->start & PAGE_MASK) || |
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offset > rp->end) |
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continue; |
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found = rp; |
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break; |
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} |
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if (found) |
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break; |
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} |
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if (found) { |
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if (found->flags & IORESOURCE_PREFETCH) |
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prot = pgprot_noncached_wc(prot); |
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pci_dev_put(pdev); |
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} |
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|
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pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n", |
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(unsigned long long)offset, pgprot_val(prot)); |
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|
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return prot; |
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} |
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|
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/* This provides legacy IO read access on a bus */ |
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int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size) |
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{ |
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unsigned long offset; |
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struct pci_controller *hose = pci_bus_to_host(bus); |
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struct resource *rp = &hose->io_resource; |
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void __iomem *addr; |
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|
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/* Check if port can be supported by that bus. We only check |
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* the ranges of the PHB though, not the bus itself as the rules |
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* for forwarding legacy cycles down bridges are not our problem |
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* here. So if the host bridge supports it, we do it. |
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*/ |
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offset = (unsigned long)hose->io_base_virt - _IO_BASE; |
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offset += port; |
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if (!(rp->flags & IORESOURCE_IO)) |
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return -ENXIO; |
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if (offset < rp->start || (offset + size) > rp->end) |
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return -ENXIO; |
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addr = hose->io_base_virt + port; |
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|
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switch (size) { |
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case 1: |
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*((u8 *)val) = in_8(addr); |
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return 1; |
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case 2: |
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if (port & 1) |
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return -EINVAL; |
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*((u16 *)val) = in_le16(addr); |
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return 2; |
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case 4: |
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if (port & 3) |
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return -EINVAL; |
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*((u32 *)val) = in_le32(addr); |
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return 4; |
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} |
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return -EINVAL; |
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} |
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|
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/* This provides legacy IO write access on a bus */ |
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int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size) |
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{ |
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unsigned long offset; |
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struct pci_controller *hose = pci_bus_to_host(bus); |
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struct resource *rp = &hose->io_resource; |
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void __iomem *addr; |
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|
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/* Check if port can be supported by that bus. We only check |
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* the ranges of the PHB though, not the bus itself as the rules |
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* for forwarding legacy cycles down bridges are not our problem |
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* here. So if the host bridge supports it, we do it. |
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*/ |
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offset = (unsigned long)hose->io_base_virt - _IO_BASE; |
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offset += port; |
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if (!(rp->flags & IORESOURCE_IO)) |
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return -ENXIO; |
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if (offset < rp->start || (offset + size) > rp->end) |
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return -ENXIO; |
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addr = hose->io_base_virt + port; |
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|
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/* WARNING: The generic code is idiotic. It gets passed a pointer |
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* to what can be a 1, 2 or 4 byte quantity and always reads that |
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* as a u32, which means that we have to correct the location of |
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* the data read within those 32 bits for size 1 and 2 |
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*/ |
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switch (size) { |
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case 1: |
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out_8(addr, val >> 24); |
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return 1; |
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case 2: |
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if (port & 1) |
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return -EINVAL; |
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out_le16(addr, val >> 16); |
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return 2; |
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case 4: |
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if (port & 3) |
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return -EINVAL; |
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out_le32(addr, val); |
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return 4; |
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} |
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return -EINVAL; |
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} |
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|
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/* This provides legacy IO or memory mmap access on a bus */ |
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int pci_mmap_legacy_page_range(struct pci_bus *bus, |
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struct vm_area_struct *vma, |
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enum pci_mmap_state mmap_state) |
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{ |
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struct pci_controller *hose = pci_bus_to_host(bus); |
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resource_size_t offset = |
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((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT; |
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resource_size_t size = vma->vm_end - vma->vm_start; |
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struct resource *rp; |
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|
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pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n", |
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pci_domain_nr(bus), bus->number, |
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mmap_state == pci_mmap_mem ? "MEM" : "IO", |
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(unsigned long long)offset, |
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(unsigned long long)(offset + size - 1)); |
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|
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if (mmap_state == pci_mmap_mem) { |
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/* Hack alert ! |
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* |
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* Because X is lame and can fail starting if it gets an error |
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* trying to mmap legacy_mem (instead of just moving on without |
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* legacy memory access) we fake it here by giving it anonymous |
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* memory, effectively behaving just like /dev/zero |
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*/ |
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if ((offset + size) > hose->isa_mem_size) { |
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pr_debug("Process %s (pid:%d) mapped non-existing PCI", |
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current->comm, current->pid); |
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pr_debug("legacy memory for 0%04x:%02x\n", |
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pci_domain_nr(bus), bus->number); |
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if (vma->vm_flags & VM_SHARED) |
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return shmem_zero_setup(vma); |
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return 0; |
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} |
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offset += hose->isa_mem_phys; |
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} else { |
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unsigned long io_offset = (unsigned long)hose->io_base_virt - |
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_IO_BASE; |
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unsigned long roffset = offset + io_offset; |
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rp = &hose->io_resource; |
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if (!(rp->flags & IORESOURCE_IO)) |
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return -ENXIO; |
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if (roffset < rp->start || (roffset + size) > rp->end) |
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return -ENXIO; |
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offset += hose->io_base_phys; |
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} |
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pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset); |
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|
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vma->vm_pgoff = offset >> PAGE_SHIFT; |
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vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
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return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, |
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vma->vm_end - vma->vm_start, |
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vma->vm_page_prot); |
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} |
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|
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void pci_resource_to_user(const struct pci_dev *dev, int bar, |
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const struct resource *rsrc, |
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resource_size_t *start, resource_size_t *end) |
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{ |
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struct pci_bus_region region; |
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|
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if (rsrc->flags & IORESOURCE_IO) { |
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pcibios_resource_to_bus(dev->bus, ®ion, |
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(struct resource *) rsrc); |
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*start = region.start; |
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*end = region.end; |
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return; |
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} |
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|
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/* We pass a CPU physical address to userland for MMIO instead of a |
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* BAR value because X is lame and expects to be able to use that |
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* to pass to /dev/mem! |
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* |
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* That means we may have 64-bit values where some apps only expect |
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* 32 (like X itself since it thinks only Sparc has 64-bit MMIO). |
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*/ |
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*start = rsrc->start; |
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*end = rsrc->end; |
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} |
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|
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/** |
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* pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree |
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* @hose: newly allocated pci_controller to be setup |
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* @dev: device node of the host bridge |
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* @primary: set if primary bus (32 bits only, soon to be deprecated) |
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* |
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* This function will parse the "ranges" property of a PCI host bridge device |
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* node and setup the resource mapping of a pci controller based on its |
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* content. |
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* |
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* Life would be boring if it wasn't for a few issues that we have to deal |
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* with here: |
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* |
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* - We can only cope with one IO space range and up to 3 Memory space |
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* ranges. However, some machines (thanks Apple !) tend to split their |
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* space into lots of small contiguous ranges. So we have to coalesce. |
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* |
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* - We can only cope with all memory ranges having the same offset |
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* between CPU addresses and PCI addresses. Unfortunately, some bridges |
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* are setup for a large 1:1 mapping along with a small "window" which |
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* maps PCI address 0 to some arbitrary high address of the CPU space in |
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* order to give access to the ISA memory hole. |
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* The way out of here that I've chosen for now is to always set the |
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* offset based on the first resource found, then override it if we |
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* have a different offset and the previous was set by an ISA hole. |
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* |
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* - Some busses have IO space not starting at 0, which causes trouble with |
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* the way we do our IO resource renumbering. The code somewhat deals with |
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* it for 64 bits but I would expect problems on 32 bits. |
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* |
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* - Some 32 bits platforms such as 4xx can have physical space larger than |
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* 32 bits so we need to use 64 bits values for the parsing |
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*/ |
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void pci_process_bridge_OF_ranges(struct pci_controller *hose, |
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struct device_node *dev, int primary) |
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{ |
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int memno = 0, isa_hole = -1; |
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unsigned long long isa_mb = 0; |
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struct resource *res; |
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struct of_pci_range range; |
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struct of_pci_range_parser parser; |
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|
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pr_info("PCI host bridge %pOF %s ranges:\n", |
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dev, primary ? "(primary)" : ""); |
|
|
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/* Check for ranges property */ |
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if (of_pci_range_parser_init(&parser, dev)) |
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return; |
|
|
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pr_debug("Parsing ranges property...\n"); |
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for_each_of_pci_range(&parser, &range) { |
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/* Read next ranges element */ |
|
|
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/* If we failed translation or got a zero-sized region |
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* (some FW try to feed us with non sensical zero sized regions |
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* such as power3 which look like some kind of attempt |
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* at exposing the VGA memory hole) |
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*/ |
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if (range.cpu_addr == OF_BAD_ADDR || range.size == 0) |
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continue; |
|
|
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/* Act based on address space type */ |
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res = NULL; |
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switch (range.flags & IORESOURCE_TYPE_BITS) { |
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case IORESOURCE_IO: |
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pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n", |
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range.cpu_addr, range.cpu_addr + range.size - 1, |
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range.pci_addr); |
|
|
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/* We support only one IO range */ |
|
if (hose->pci_io_size) { |
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pr_info(" \\--> Skipped (too many) !\n"); |
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continue; |
|
} |
|
/* On 32 bits, limit I/O space to 16MB */ |
|
if (range.size > 0x01000000) |
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range.size = 0x01000000; |
|
|
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/* 32 bits needs to map IOs here */ |
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hose->io_base_virt = ioremap(range.cpu_addr, |
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range.size); |
|
|
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/* Expect trouble if pci_addr is not 0 */ |
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if (primary) |
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isa_io_base = |
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(unsigned long)hose->io_base_virt; |
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/* pci_io_size and io_base_phys always represent IO |
|
* space starting at 0 so we factor in pci_addr |
|
*/ |
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hose->pci_io_size = range.pci_addr + range.size; |
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hose->io_base_phys = range.cpu_addr - range.pci_addr; |
|
|
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/* Build resource */ |
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res = &hose->io_resource; |
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range.cpu_addr = range.pci_addr; |
|
|
|
break; |
|
case IORESOURCE_MEM: |
|
pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n", |
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range.cpu_addr, range.cpu_addr + range.size - 1, |
|
range.pci_addr, |
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(range.flags & IORESOURCE_PREFETCH) ? |
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"Prefetch" : ""); |
|
|
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/* We support only 3 memory ranges */ |
|
if (memno >= 3) { |
|
pr_info(" \\--> Skipped (too many) !\n"); |
|
continue; |
|
} |
|
/* Handles ISA memory hole space here */ |
|
if (range.pci_addr == 0) { |
|
isa_mb = range.cpu_addr; |
|
isa_hole = memno; |
|
if (primary || isa_mem_base == 0) |
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isa_mem_base = range.cpu_addr; |
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hose->isa_mem_phys = range.cpu_addr; |
|
hose->isa_mem_size = range.size; |
|
} |
|
|
|
/* We get the PCI/Mem offset from the first range or |
|
* the, current one if the offset came from an ISA |
|
* hole. If they don't match, bugger. |
|
*/ |
|
if (memno == 0 || |
|
(isa_hole >= 0 && range.pci_addr != 0 && |
|
hose->pci_mem_offset == isa_mb)) |
|
hose->pci_mem_offset = range.cpu_addr - |
|
range.pci_addr; |
|
else if (range.pci_addr != 0 && |
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hose->pci_mem_offset != range.cpu_addr - |
|
range.pci_addr) { |
|
pr_info(" \\--> Skipped (offset mismatch) !\n"); |
|
continue; |
|
} |
|
|
|
/* Build resource */ |
|
res = &hose->mem_resources[memno++]; |
|
break; |
|
} |
|
if (res != NULL) { |
|
res->name = dev->full_name; |
|
res->flags = range.flags; |
|
res->start = range.cpu_addr; |
|
res->end = range.cpu_addr + range.size - 1; |
|
res->parent = res->child = res->sibling = NULL; |
|
} |
|
} |
|
|
|
/* If there's an ISA hole and the pci_mem_offset is -not- matching |
|
* the ISA hole offset, then we need to remove the ISA hole from |
|
* the resource list for that brige |
|
*/ |
|
if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) { |
|
unsigned int next = isa_hole + 1; |
|
pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb); |
|
if (next < memno) |
|
memmove(&hose->mem_resources[isa_hole], |
|
&hose->mem_resources[next], |
|
sizeof(struct resource) * (memno - next)); |
|
hose->mem_resources[--memno].flags = 0; |
|
} |
|
} |
|
|
|
/* Display the domain number in /proc */ |
|
int pci_proc_domain(struct pci_bus *bus) |
|
{ |
|
return pci_domain_nr(bus); |
|
} |
|
|
|
/* This header fixup will do the resource fixup for all devices as they are |
|
* probed, but not for bridge ranges |
|
*/ |
|
static void pcibios_fixup_resources(struct pci_dev *dev) |
|
{ |
|
struct pci_controller *hose = pci_bus_to_host(dev->bus); |
|
int i; |
|
|
|
if (!hose) { |
|
pr_err("No host bridge for PCI dev %s !\n", |
|
pci_name(dev)); |
|
return; |
|
} |
|
for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
|
struct resource *res = dev->resource + i; |
|
if (!res->flags) |
|
continue; |
|
if (res->start == 0) { |
|
pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]", |
|
pci_name(dev), i, |
|
(unsigned long long)res->start, |
|
(unsigned long long)res->end, |
|
(unsigned int)res->flags); |
|
pr_debug("is unassigned\n"); |
|
res->end -= res->start; |
|
res->start = 0; |
|
res->flags |= IORESOURCE_UNSET; |
|
continue; |
|
} |
|
|
|
pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]\n", |
|
pci_name(dev), i, |
|
(unsigned long long)res->start, |
|
(unsigned long long)res->end, |
|
(unsigned int)res->flags); |
|
} |
|
} |
|
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources); |
|
|
|
int pcibios_add_device(struct pci_dev *dev) |
|
{ |
|
dev->irq = of_irq_parse_and_map_pci(dev, 0, 0); |
|
|
|
return 0; |
|
} |
|
EXPORT_SYMBOL(pcibios_add_device); |
|
|
|
/* |
|
* Reparent resource children of pr that conflict with res |
|
* under res, and make res replace those children. |
|
*/ |
|
static int __init reparent_resources(struct resource *parent, |
|
struct resource *res) |
|
{ |
|
struct resource *p, **pp; |
|
struct resource **firstpp = NULL; |
|
|
|
for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) { |
|
if (p->end < res->start) |
|
continue; |
|
if (res->end < p->start) |
|
break; |
|
if (p->start < res->start || p->end > res->end) |
|
return -1; /* not completely contained */ |
|
if (firstpp == NULL) |
|
firstpp = pp; |
|
} |
|
if (firstpp == NULL) |
|
return -1; /* didn't find any conflicting entries? */ |
|
res->parent = parent; |
|
res->child = *firstpp; |
|
res->sibling = *pp; |
|
*firstpp = res; |
|
*pp = NULL; |
|
for (p = res->child; p != NULL; p = p->sibling) { |
|
p->parent = res; |
|
pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n", |
|
p->name, |
|
(unsigned long long)p->start, |
|
(unsigned long long)p->end, res->name); |
|
} |
|
return 0; |
|
} |
|
|
|
/* |
|
* Handle resources of PCI devices. If the world were perfect, we could |
|
* just allocate all the resource regions and do nothing more. It isn't. |
|
* On the other hand, we cannot just re-allocate all devices, as it would |
|
* require us to know lots of host bridge internals. So we attempt to |
|
* keep as much of the original configuration as possible, but tweak it |
|
* when it's found to be wrong. |
|
* |
|
* Known BIOS problems we have to work around: |
|
* - I/O or memory regions not configured |
|
* - regions configured, but not enabled in the command register |
|
* - bogus I/O addresses above 64K used |
|
* - expansion ROMs left enabled (this may sound harmless, but given |
|
* the fact the PCI specs explicitly allow address decoders to be |
|
* shared between expansion ROMs and other resource regions, it's |
|
* at least dangerous) |
|
* |
|
* Our solution: |
|
* (1) Allocate resources for all buses behind PCI-to-PCI bridges. |
|
* This gives us fixed barriers on where we can allocate. |
|
* (2) Allocate resources for all enabled devices. If there is |
|
* a collision, just mark the resource as unallocated. Also |
|
* disable expansion ROMs during this step. |
|
* (3) Try to allocate resources for disabled devices. If the |
|
* resources were assigned correctly, everything goes well, |
|
* if they weren't, they won't disturb allocation of other |
|
* resources. |
|
* (4) Assign new addresses to resources which were either |
|
* not configured at all or misconfigured. If explicitly |
|
* requested by the user, configure expansion ROM address |
|
* as well. |
|
*/ |
|
|
|
static void pcibios_allocate_bus_resources(struct pci_bus *bus) |
|
{ |
|
struct pci_bus *b; |
|
int i; |
|
struct resource *res, *pr; |
|
|
|
pr_debug("PCI: Allocating bus resources for %04x:%02x...\n", |
|
pci_domain_nr(bus), bus->number); |
|
|
|
pci_bus_for_each_resource(bus, res, i) { |
|
if (!res || !res->flags |
|
|| res->start > res->end || res->parent) |
|
continue; |
|
if (bus->parent == NULL) |
|
pr = (res->flags & IORESOURCE_IO) ? |
|
&ioport_resource : &iomem_resource; |
|
else { |
|
/* Don't bother with non-root busses when |
|
* re-assigning all resources. We clear the |
|
* resource flags as if they were colliding |
|
* and as such ensure proper re-allocation |
|
* later. |
|
*/ |
|
pr = pci_find_parent_resource(bus->self, res); |
|
if (pr == res) { |
|
/* this happens when the generic PCI |
|
* code (wrongly) decides that this |
|
* bridge is transparent -- paulus |
|
*/ |
|
continue; |
|
} |
|
} |
|
|
|
pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ", |
|
bus->self ? pci_name(bus->self) : "PHB", |
|
bus->number, i, |
|
(unsigned long long)res->start, |
|
(unsigned long long)res->end); |
|
pr_debug("[0x%x], parent %p (%s)\n", |
|
(unsigned int)res->flags, |
|
pr, (pr && pr->name) ? pr->name : "nil"); |
|
|
|
if (pr && !(pr->flags & IORESOURCE_UNSET)) { |
|
struct pci_dev *dev = bus->self; |
|
|
|
if (request_resource(pr, res) == 0) |
|
continue; |
|
/* |
|
* Must be a conflict with an existing entry. |
|
* Move that entry (or entries) under the |
|
* bridge resource and try again. |
|
*/ |
|
if (reparent_resources(pr, res) == 0) |
|
continue; |
|
|
|
if (dev && i < PCI_BRIDGE_RESOURCE_NUM && |
|
pci_claim_bridge_resource(dev, |
|
i + PCI_BRIDGE_RESOURCES) == 0) |
|
continue; |
|
|
|
} |
|
pr_warn("PCI: Cannot allocate resource region "); |
|
pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number); |
|
res->start = res->end = 0; |
|
res->flags = 0; |
|
} |
|
|
|
list_for_each_entry(b, &bus->children, node) |
|
pcibios_allocate_bus_resources(b); |
|
} |
|
|
|
static inline void alloc_resource(struct pci_dev *dev, int idx) |
|
{ |
|
struct resource *pr, *r = &dev->resource[idx]; |
|
|
|
pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n", |
|
pci_name(dev), idx, |
|
(unsigned long long)r->start, |
|
(unsigned long long)r->end, |
|
(unsigned int)r->flags); |
|
|
|
pr = pci_find_parent_resource(dev, r); |
|
if (!pr || (pr->flags & IORESOURCE_UNSET) || |
|
request_resource(pr, r) < 0) { |
|
pr_warn("PCI: Cannot allocate resource region %d ", idx); |
|
pr_cont("of device %s, will remap\n", pci_name(dev)); |
|
if (pr) |
|
pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n", |
|
pr, |
|
(unsigned long long)pr->start, |
|
(unsigned long long)pr->end, |
|
(unsigned int)pr->flags); |
|
/* We'll assign a new address later */ |
|
r->flags |= IORESOURCE_UNSET; |
|
r->end -= r->start; |
|
r->start = 0; |
|
} |
|
} |
|
|
|
static void __init pcibios_allocate_resources(int pass) |
|
{ |
|
struct pci_dev *dev = NULL; |
|
int idx, disabled; |
|
u16 command; |
|
struct resource *r; |
|
|
|
for_each_pci_dev(dev) { |
|
pci_read_config_word(dev, PCI_COMMAND, &command); |
|
for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) { |
|
r = &dev->resource[idx]; |
|
if (r->parent) /* Already allocated */ |
|
continue; |
|
if (!r->flags || (r->flags & IORESOURCE_UNSET)) |
|
continue; /* Not assigned at all */ |
|
/* We only allocate ROMs on pass 1 just in case they |
|
* have been screwed up by firmware |
|
*/ |
|
if (idx == PCI_ROM_RESOURCE) |
|
disabled = 1; |
|
if (r->flags & IORESOURCE_IO) |
|
disabled = !(command & PCI_COMMAND_IO); |
|
else |
|
disabled = !(command & PCI_COMMAND_MEMORY); |
|
if (pass == disabled) |
|
alloc_resource(dev, idx); |
|
} |
|
if (pass) |
|
continue; |
|
r = &dev->resource[PCI_ROM_RESOURCE]; |
|
if (r->flags) { |
|
/* Turn the ROM off, leave the resource region, |
|
* but keep it unregistered. |
|
*/ |
|
u32 reg; |
|
pci_read_config_dword(dev, dev->rom_base_reg, ®); |
|
if (reg & PCI_ROM_ADDRESS_ENABLE) { |
|
pr_debug("PCI: Switching off ROM of %s\n", |
|
pci_name(dev)); |
|
r->flags &= ~IORESOURCE_ROM_ENABLE; |
|
pci_write_config_dword(dev, dev->rom_base_reg, |
|
reg & ~PCI_ROM_ADDRESS_ENABLE); |
|
} |
|
} |
|
} |
|
} |
|
|
|
static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus) |
|
{ |
|
struct pci_controller *hose = pci_bus_to_host(bus); |
|
resource_size_t offset; |
|
struct resource *res, *pres; |
|
int i; |
|
|
|
pr_debug("Reserving legacy ranges for domain %04x\n", |
|
pci_domain_nr(bus)); |
|
|
|
/* Check for IO */ |
|
if (!(hose->io_resource.flags & IORESOURCE_IO)) |
|
goto no_io; |
|
offset = (unsigned long)hose->io_base_virt - _IO_BASE; |
|
res = kzalloc(sizeof(struct resource), GFP_KERNEL); |
|
BUG_ON(res == NULL); |
|
res->name = "Legacy IO"; |
|
res->flags = IORESOURCE_IO; |
|
res->start = offset; |
|
res->end = (offset + 0xfff) & 0xfffffffful; |
|
pr_debug("Candidate legacy IO: %pR\n", res); |
|
if (request_resource(&hose->io_resource, res)) { |
|
pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n", |
|
pci_domain_nr(bus), bus->number, res); |
|
kfree(res); |
|
} |
|
|
|
no_io: |
|
/* Check for memory */ |
|
offset = hose->pci_mem_offset; |
|
pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset); |
|
for (i = 0; i < 3; i++) { |
|
pres = &hose->mem_resources[i]; |
|
if (!(pres->flags & IORESOURCE_MEM)) |
|
continue; |
|
pr_debug("hose mem res: %pR\n", pres); |
|
if ((pres->start - offset) <= 0xa0000 && |
|
(pres->end - offset) >= 0xbffff) |
|
break; |
|
} |
|
if (i >= 3) |
|
return; |
|
res = kzalloc(sizeof(struct resource), GFP_KERNEL); |
|
BUG_ON(res == NULL); |
|
res->name = "Legacy VGA memory"; |
|
res->flags = IORESOURCE_MEM; |
|
res->start = 0xa0000 + offset; |
|
res->end = 0xbffff + offset; |
|
pr_debug("Candidate VGA memory: %pR\n", res); |
|
if (request_resource(pres, res)) { |
|
pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n", |
|
pci_domain_nr(bus), bus->number, res); |
|
kfree(res); |
|
} |
|
} |
|
|
|
void __init pcibios_resource_survey(void) |
|
{ |
|
struct pci_bus *b; |
|
|
|
/* Allocate and assign resources. If we re-assign everything, then |
|
* we skip the allocate phase |
|
*/ |
|
list_for_each_entry(b, &pci_root_buses, node) |
|
pcibios_allocate_bus_resources(b); |
|
|
|
pcibios_allocate_resources(0); |
|
pcibios_allocate_resources(1); |
|
|
|
/* Before we start assigning unassigned resource, we try to reserve |
|
* the low IO area and the VGA memory area if they intersect the |
|
* bus available resources to avoid allocating things on top of them |
|
*/ |
|
list_for_each_entry(b, &pci_root_buses, node) |
|
pcibios_reserve_legacy_regions(b); |
|
|
|
/* Now proceed to assigning things that were left unassigned */ |
|
pr_debug("PCI: Assigning unassigned resources...\n"); |
|
pci_assign_unassigned_resources(); |
|
} |
|
|
|
static void pcibios_setup_phb_resources(struct pci_controller *hose, |
|
struct list_head *resources) |
|
{ |
|
unsigned long io_offset; |
|
struct resource *res; |
|
int i; |
|
|
|
/* Hookup PHB IO resource */ |
|
res = &hose->io_resource; |
|
|
|
/* Fixup IO space offset */ |
|
io_offset = (unsigned long)hose->io_base_virt - isa_io_base; |
|
res->start = (res->start + io_offset) & 0xffffffffu; |
|
res->end = (res->end + io_offset) & 0xffffffffu; |
|
|
|
if (!res->flags) { |
|
pr_warn("PCI: I/O resource not set for host "); |
|
pr_cont("bridge %pOF (domain %d)\n", |
|
hose->dn, hose->global_number); |
|
/* Workaround for lack of IO resource only on 32-bit */ |
|
res->start = (unsigned long)hose->io_base_virt - isa_io_base; |
|
res->end = res->start + IO_SPACE_LIMIT; |
|
res->flags = IORESOURCE_IO; |
|
} |
|
pci_add_resource_offset(resources, res, |
|
(__force resource_size_t)(hose->io_base_virt - _IO_BASE)); |
|
|
|
pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n", |
|
(unsigned long long)res->start, |
|
(unsigned long long)res->end, |
|
(unsigned long)res->flags); |
|
|
|
/* Hookup PHB Memory resources */ |
|
for (i = 0; i < 3; ++i) { |
|
res = &hose->mem_resources[i]; |
|
if (!res->flags) { |
|
if (i > 0) |
|
continue; |
|
pr_err("PCI: Memory resource 0 not set for "); |
|
pr_cont("host bridge %pOF (domain %d)\n", |
|
hose->dn, hose->global_number); |
|
|
|
/* Workaround for lack of MEM resource only on 32-bit */ |
|
res->start = hose->pci_mem_offset; |
|
res->end = (resource_size_t)-1LL; |
|
res->flags = IORESOURCE_MEM; |
|
|
|
} |
|
pci_add_resource_offset(resources, res, hose->pci_mem_offset); |
|
|
|
pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n", |
|
i, (unsigned long long)res->start, |
|
(unsigned long long)res->end, |
|
(unsigned long)res->flags); |
|
} |
|
|
|
pr_debug("PCI: PHB MEM offset = %016llx\n", |
|
(unsigned long long)hose->pci_mem_offset); |
|
pr_debug("PCI: PHB IO offset = %08lx\n", |
|
(unsigned long)hose->io_base_virt - _IO_BASE); |
|
} |
|
|
|
static void pcibios_scan_phb(struct pci_controller *hose) |
|
{ |
|
LIST_HEAD(resources); |
|
struct pci_bus *bus; |
|
struct device_node *node = hose->dn; |
|
|
|
pr_debug("PCI: Scanning PHB %pOF\n", node); |
|
|
|
pcibios_setup_phb_resources(hose, &resources); |
|
|
|
bus = pci_scan_root_bus(hose->parent, hose->first_busno, |
|
hose->ops, hose, &resources); |
|
if (bus == NULL) { |
|
pr_err("Failed to create bus for PCI domain %04x\n", |
|
hose->global_number); |
|
pci_free_resource_list(&resources); |
|
return; |
|
} |
|
bus->busn_res.start = hose->first_busno; |
|
hose->bus = bus; |
|
|
|
hose->last_busno = bus->busn_res.end; |
|
} |
|
|
|
static int __init pcibios_init(void) |
|
{ |
|
struct pci_controller *hose, *tmp; |
|
int next_busno = 0; |
|
|
|
pr_info("PCI: Probing PCI hardware\n"); |
|
|
|
/* Scan all of the recorded PCI controllers. */ |
|
list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { |
|
hose->last_busno = 0xff; |
|
pcibios_scan_phb(hose); |
|
if (next_busno <= hose->last_busno) |
|
next_busno = hose->last_busno + 1; |
|
} |
|
pci_bus_count = next_busno; |
|
|
|
/* Call common code to handle resource allocation */ |
|
pcibios_resource_survey(); |
|
list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { |
|
if (hose->bus) |
|
pci_bus_add_devices(hose->bus); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
subsys_initcall(pcibios_init); |
|
|
|
static struct pci_controller *pci_bus_to_hose(int bus) |
|
{ |
|
struct pci_controller *hose, *tmp; |
|
|
|
list_for_each_entry_safe(hose, tmp, &hose_list, list_node) |
|
if (bus >= hose->first_busno && bus <= hose->last_busno) |
|
return hose; |
|
return NULL; |
|
} |
|
|
|
/* Provide information on locations of various I/O regions in physical |
|
* memory. Do this on a per-card basis so that we choose the right |
|
* root bridge. |
|
* Note that the returned IO or memory base is a physical address |
|
*/ |
|
|
|
long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn) |
|
{ |
|
struct pci_controller *hose; |
|
long result = -EOPNOTSUPP; |
|
|
|
hose = pci_bus_to_hose(bus); |
|
if (!hose) |
|
return -ENODEV; |
|
|
|
switch (which) { |
|
case IOBASE_BRIDGE_NUMBER: |
|
return (long)hose->first_busno; |
|
case IOBASE_MEMORY: |
|
return (long)hose->pci_mem_offset; |
|
case IOBASE_IO: |
|
return (long)hose->io_base_phys; |
|
case IOBASE_ISA_IO: |
|
return (long)isa_io_base; |
|
case IOBASE_ISA_MEM: |
|
return (long)isa_mem_base; |
|
} |
|
|
|
return result; |
|
} |
|
|
|
/* |
|
* Null PCI config access functions, for the case when we can't |
|
* find a hose. |
|
*/ |
|
#define NULL_PCI_OP(rw, size, type) \ |
|
static int \ |
|
null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \ |
|
{ \ |
|
return PCIBIOS_DEVICE_NOT_FOUND; \ |
|
} |
|
|
|
static int |
|
null_read_config(struct pci_bus *bus, unsigned int devfn, int offset, |
|
int len, u32 *val) |
|
{ |
|
return PCIBIOS_DEVICE_NOT_FOUND; |
|
} |
|
|
|
static int |
|
null_write_config(struct pci_bus *bus, unsigned int devfn, int offset, |
|
int len, u32 val) |
|
{ |
|
return PCIBIOS_DEVICE_NOT_FOUND; |
|
} |
|
|
|
static struct pci_ops null_pci_ops = { |
|
.read = null_read_config, |
|
.write = null_write_config, |
|
}; |
|
|
|
/* |
|
* These functions are used early on before PCI scanning is done |
|
* and all of the pci_dev and pci_bus structures have been created. |
|
*/ |
|
static struct pci_bus * |
|
fake_pci_bus(struct pci_controller *hose, int busnr) |
|
{ |
|
static struct pci_bus bus; |
|
|
|
if (!hose) |
|
pr_err("Can't find hose for PCI bus %d!\n", busnr); |
|
|
|
bus.number = busnr; |
|
bus.sysdata = hose; |
|
bus.ops = hose ? hose->ops : &null_pci_ops; |
|
return &bus; |
|
} |
|
|
|
#define EARLY_PCI_OP(rw, size, type) \ |
|
int early_##rw##_config_##size(struct pci_controller *hose, int bus, \ |
|
int devfn, int offset, type value) \ |
|
{ \ |
|
return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \ |
|
devfn, offset, value); \ |
|
} |
|
|
|
EARLY_PCI_OP(read, byte, u8 *) |
|
EARLY_PCI_OP(read, word, u16 *) |
|
EARLY_PCI_OP(read, dword, u32 *) |
|
EARLY_PCI_OP(write, byte, u8) |
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EARLY_PCI_OP(write, word, u16) |
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EARLY_PCI_OP(write, dword, u32) |
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int early_find_capability(struct pci_controller *hose, int bus, int devfn, |
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int cap) |
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{ |
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return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap); |
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}
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