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124 lines
3.1 KiB
124 lines
3.1 KiB
/* |
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** macints.h -- Macintosh Linux interrupt handling structs and prototypes |
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** |
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** Copyright 1997 by Michael Schmitz |
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** |
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** This file is subject to the terms and conditions of the GNU General Public |
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** License. See the file COPYING in the main directory of this archive |
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** for more details. |
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** |
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*/ |
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#ifndef _ASM_MACINTS_H_ |
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#define _ASM_MACINTS_H_ |
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#include <asm/irq.h> |
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/* |
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* Base IRQ number for all Mac68K interrupt sources. Each source |
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* has eight indexes (base -> base+7). |
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*/ |
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#define VIA1_SOURCE_BASE 8 |
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#define VIA2_SOURCE_BASE 16 |
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#define PSC3_SOURCE_BASE 24 |
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#define PSC4_SOURCE_BASE 32 |
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#define PSC5_SOURCE_BASE 40 |
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#define PSC6_SOURCE_BASE 48 |
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#define NUBUS_SOURCE_BASE 56 |
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#define BABOON_SOURCE_BASE 64 |
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/* |
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* Maximum IRQ number is BABOON_SOURCE_BASE + 7, |
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* giving us IRQs up through 71 |
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*/ |
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#define NUM_MAC_SOURCES 72 |
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/* |
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* clean way to separate IRQ into its source and index |
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*/ |
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#define IRQ_SRC(irq) (irq >> 3) |
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#define IRQ_IDX(irq) (irq & 7) |
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/* VIA1 interrupts */ |
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#define IRQ_VIA1_0 (8) /* one second int. */ |
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#define IRQ_VIA1_1 (9) /* VBlank int. */ |
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#define IRQ_MAC_VBL IRQ_VIA1_1 |
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#define IRQ_VIA1_2 (10) /* ADB SR shifts complete */ |
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#define IRQ_MAC_ADB IRQ_VIA1_2 |
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#define IRQ_MAC_ADB_SR IRQ_VIA1_2 |
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#define IRQ_VIA1_3 (11) /* ADB SR CB2 ?? */ |
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#define IRQ_MAC_ADB_SD IRQ_VIA1_3 |
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#define IRQ_VIA1_4 (12) /* ADB SR ext. clock pulse */ |
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#define IRQ_MAC_ADB_CL IRQ_VIA1_4 |
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#define IRQ_VIA1_5 (13) |
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#define IRQ_MAC_TIMER_2 IRQ_VIA1_5 |
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#define IRQ_VIA1_6 (14) |
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#define IRQ_MAC_TIMER_1 IRQ_VIA1_6 |
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#define IRQ_VIA1_7 (15) |
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/* VIA2/RBV interrupts */ |
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#define IRQ_VIA2_0 (16) |
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#define IRQ_MAC_SCSIDRQ IRQ_VIA2_0 |
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#define IRQ_VIA2_1 (17) |
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#define IRQ_MAC_NUBUS IRQ_VIA2_1 |
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#define IRQ_VIA2_2 (18) |
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#define IRQ_VIA2_3 (19) |
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#define IRQ_MAC_SCSI IRQ_VIA2_3 |
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#define IRQ_VIA2_4 (20) |
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#define IRQ_VIA2_5 (21) |
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#define IRQ_VIA2_6 (22) |
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#define IRQ_VIA2_7 (23) |
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/* Level 3 (PSC, AV Macs only) interrupts */ |
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#define IRQ_PSC3_0 (24) |
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#define IRQ_MAC_MACE IRQ_PSC3_0 |
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#define IRQ_PSC3_1 (25) |
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#define IRQ_PSC3_2 (26) |
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#define IRQ_PSC3_3 (27) |
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/* Level 4 (PSC, AV Macs only) interrupts */ |
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#define IRQ_PSC4_0 (32) |
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#define IRQ_PSC4_1 (33) |
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#define IRQ_MAC_SCC_A IRQ_PSC4_1 |
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#define IRQ_PSC4_2 (34) |
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#define IRQ_MAC_SCC_B IRQ_PSC4_2 |
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#define IRQ_PSC4_3 (35) |
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#define IRQ_MAC_MACE_DMA IRQ_PSC4_3 |
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/* OSS Level 4 interrupts */ |
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#define IRQ_MAC_SCC (33) |
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/* Level 5 (PSC, AV Macs only) interrupts */ |
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#define IRQ_PSC5_0 (40) |
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#define IRQ_PSC5_1 (41) |
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#define IRQ_PSC5_2 (42) |
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#define IRQ_PSC5_3 (43) |
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/* Level 6 (PSC, AV Macs only) interrupts */ |
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#define IRQ_PSC6_0 (48) |
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#define IRQ_PSC6_1 (49) |
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#define IRQ_PSC6_2 (50) |
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#define IRQ_PSC6_3 (51) |
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/* Nubus interrupts (cascaded to VIA2) */ |
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#define IRQ_NUBUS_9 (56) |
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#define IRQ_NUBUS_A (57) |
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#define IRQ_NUBUS_B (58) |
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#define IRQ_NUBUS_C (59) |
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#define IRQ_NUBUS_D (60) |
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#define IRQ_NUBUS_E (61) |
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#define IRQ_NUBUS_F (62) |
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/* Baboon interrupts (cascaded to nubus slot $C) */ |
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#define IRQ_BABOON_0 (64) |
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#define IRQ_BABOON_1 (65) |
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#define IRQ_BABOON_2 (66) |
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#define IRQ_BABOON_3 (67) |
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#define SLOT2IRQ(x) (x + 47) |
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#define IRQ2SLOT(x) (x - 47) |
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#endif /* asm/macints.h */
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