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166 lines
5.4 KiB
166 lines
5.4 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* I/O Processor (IOP) defines and structures, mostly snagged from A/UX |
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* header files. |
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* |
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* The original header from which this was taken is copyrighted. I've done some |
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* rewriting (in fact my changes make this a bit more readable, IMHO) but some |
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* more should be done. |
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*/ |
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/* |
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* This is the base address of the IOPs. Use this as the address of |
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* a "struct iop" (see below) to see where the actual registers fall. |
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*/ |
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#define SCC_IOP_BASE_IIFX (0x50F04000) |
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#define ISM_IOP_BASE_IIFX (0x50F12000) |
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#define SCC_IOP_BASE_QUADRA (0x50F0C000) |
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#define ISM_IOP_BASE_QUADRA (0x50F1E000) |
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/* IOP status/control register bits: */ |
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#define IOP_BYPASS 0x01 /* bypass-mode hardware access */ |
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#define IOP_AUTOINC 0x02 /* allow autoincrement of ramhi/lo */ |
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#define IOP_RUN 0x04 /* set to 0 to reset IOP chip */ |
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#define IOP_IRQ 0x08 /* generate IRQ to IOP if 1 */ |
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#define IOP_INT0 0x10 /* intr priority from IOP to host */ |
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#define IOP_INT1 0x20 /* intr priority from IOP to host */ |
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#define IOP_HWINT 0x40 /* IRQ from hardware; bypass mode only */ |
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#define IOP_DMAINACTIVE 0x80 /* no DMA request active; bypass mode only */ |
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#define NUM_IOPS 2 |
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#define NUM_IOP_CHAN 7 |
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#define NUM_IOP_MSGS NUM_IOP_CHAN*8 |
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#define IOP_MSG_LEN 32 |
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/* IOP reference numbers, used by the globally-visible iop_xxx functions */ |
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#define IOP_NUM_SCC 0 |
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#define IOP_NUM_ISM 1 |
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/* IOP channel states */ |
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#define IOP_MSG_IDLE 0 /* idle */ |
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#define IOP_MSG_NEW 1 /* new message sent */ |
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#define IOP_MSG_RCVD 2 /* message received; processing */ |
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#define IOP_MSG_COMPLETE 3 /* message processing complete */ |
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/* IOP message status codes */ |
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#define IOP_MSGSTATUS_UNUSED 0 /* Unused message structure */ |
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#define IOP_MSGSTATUS_WAITING 1 /* waiting for channel */ |
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#define IOP_MSGSTATUS_SENT 2 /* message sent, awaiting reply */ |
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#define IOP_MSGSTATUS_COMPLETE 3 /* message complete and reply rcvd */ |
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#define IOP_MSGSTATUS_UNSOL 6 /* message is unsolicited */ |
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/* IOP memory addresses of the members of the mac_iop_kernel structure. */ |
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#define IOP_ADDR_MAX_SEND_CHAN 0x0200 |
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#define IOP_ADDR_SEND_STATE 0x0201 |
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#define IOP_ADDR_PATCH_CTRL 0x021F |
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#define IOP_ADDR_SEND_MSG 0x0220 |
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#define IOP_ADDR_MAX_RECV_CHAN 0x0300 |
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#define IOP_ADDR_RECV_STATE 0x0301 |
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#define IOP_ADDR_ALIVE 0x031F |
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#define IOP_ADDR_RECV_MSG 0x0320 |
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#ifndef __ASSEMBLY__ |
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/* |
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* IOP Control registers, staggered because in usual Apple style they were |
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* too lazy to decode the A0 bit. This structure is assumed to begin at |
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* one of the xxx_IOP_BASE addresses given above. |
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*/ |
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struct mac_iop { |
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__u8 ram_addr_hi; /* shared RAM address hi byte */ |
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__u8 pad0; |
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__u8 ram_addr_lo; /* shared RAM address lo byte */ |
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__u8 pad1; |
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__u8 status_ctrl; /* status/control register */ |
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__u8 pad2[3]; |
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__u8 ram_data; /* RAM data byte at ramhi/lo */ |
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__u8 pad3[23]; |
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/* Bypass-mode hardware access registers */ |
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union { |
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struct { /* SCC registers */ |
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__u8 sccb_cmd; /* SCC B command reg */ |
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__u8 pad4; |
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__u8 scca_cmd; /* SCC A command reg */ |
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__u8 pad5; |
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__u8 sccb_data; /* SCC B data */ |
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__u8 pad6; |
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__u8 scca_data; /* SCC A data */ |
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} scc_regs; |
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struct { /* ISM registers */ |
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__u8 wdata; /* write a data byte */ |
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__u8 pad7; |
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__u8 wmark; /* write a mark byte */ |
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__u8 pad8; |
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__u8 wcrc; /* write 2-byte crc to disk */ |
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__u8 pad9; |
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__u8 wparams; /* write the param regs */ |
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__u8 pad10; |
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__u8 wphase; /* write the phase states & dirs */ |
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__u8 pad11; |
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__u8 wsetup; /* write the setup register */ |
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__u8 pad12; |
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__u8 wzeroes; /* mode reg: 1's clr bits, 0's are x */ |
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__u8 pad13; |
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__u8 wones; /* mode reg: 1's set bits, 0's are x */ |
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__u8 pad14; |
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__u8 rdata; /* read a data byte */ |
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__u8 pad15; |
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__u8 rmark; /* read a mark byte */ |
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__u8 pad16; |
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__u8 rerror; /* read the error register */ |
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__u8 pad17; |
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__u8 rparams; /* read the param regs */ |
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__u8 pad18; |
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__u8 rphase; /* read the phase states & dirs */ |
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__u8 pad19; |
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__u8 rsetup; /* read the setup register */ |
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__u8 pad20; |
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__u8 rmode; /* read the mode register */ |
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__u8 pad21; |
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__u8 rhandshake; /* read the handshake register */ |
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} ism_regs; |
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} b; |
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}; |
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/* This structure is used to track IOP messages in the Linux kernel */ |
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struct iop_msg { |
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struct iop_msg *next; /* next message in queue or NULL */ |
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uint iop_num; /* IOP number */ |
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uint channel; /* channel number */ |
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void *caller_priv; /* caller private data */ |
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int status; /* status of this message */ |
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__u8 message[IOP_MSG_LEN]; /* the message being sent/received */ |
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__u8 reply[IOP_MSG_LEN]; /* the reply to the message */ |
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void (*handler)(struct iop_msg *); |
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/* function to call when reply recvd */ |
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}; |
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extern int iop_scc_present,iop_ism_present; |
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extern int iop_listen(uint, uint, |
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void (*handler)(struct iop_msg *), |
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const char *); |
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extern int iop_send_message(uint, uint, void *, uint, __u8 *, |
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void (*)(struct iop_msg *)); |
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extern void iop_complete_message(struct iop_msg *); |
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extern void iop_upload_code(uint, __u8 *, uint, __u16); |
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extern void iop_download_code(uint, __u8 *, uint, __u16); |
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extern __u8 *iop_compare_code(uint, __u8 *, uint, __u16); |
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extern void iop_ism_irq_poll(uint); |
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extern void iop_register_interrupts(void); |
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#endif /* __ASSEMBLY__ */
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