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279 lines
7.0 KiB
279 lines
7.0 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _M68K_CACHEFLUSH_H |
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#define _M68K_CACHEFLUSH_H |
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#include <linux/mm.h> |
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#ifdef CONFIG_COLDFIRE |
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#include <asm/mcfsim.h> |
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#endif |
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/* cache code */ |
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#define FLUSH_I_AND_D (0x00000808) |
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#define FLUSH_I (0x00000008) |
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#ifndef ICACHE_MAX_ADDR |
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#define ICACHE_MAX_ADDR 0 |
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#define ICACHE_SET_MASK 0 |
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#define DCACHE_MAX_ADDR 0 |
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#define DCACHE_SETMASK 0 |
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#endif |
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#ifndef CACHE_MODE |
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#define CACHE_MODE 0 |
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#define CACR_ICINVA 0 |
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#define CACR_DCINVA 0 |
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#define CACR_BCINVA 0 |
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#endif |
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/* |
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* ColdFire architecture has no way to clear individual cache lines, so we |
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* are stuck invalidating all the cache entries when we want a clear operation. |
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*/ |
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static inline void clear_cf_icache(unsigned long start, unsigned long end) |
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{ |
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__asm__ __volatile__ ( |
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"movec %0,%%cacr\n\t" |
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"nop" |
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: |
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: "r" (CACHE_MODE | CACR_ICINVA | CACR_BCINVA)); |
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} |
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static inline void clear_cf_dcache(unsigned long start, unsigned long end) |
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{ |
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__asm__ __volatile__ ( |
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"movec %0,%%cacr\n\t" |
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"nop" |
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: |
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: "r" (CACHE_MODE | CACR_DCINVA)); |
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} |
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static inline void clear_cf_bcache(unsigned long start, unsigned long end) |
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{ |
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__asm__ __volatile__ ( |
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"movec %0,%%cacr\n\t" |
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"nop" |
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: |
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: "r" (CACHE_MODE | CACR_ICINVA | CACR_BCINVA | CACR_DCINVA)); |
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} |
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/* |
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* Use the ColdFire cpushl instruction to push (and invalidate) cache lines. |
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* The start and end addresses are cache line numbers not memory addresses. |
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*/ |
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static inline void flush_cf_icache(unsigned long start, unsigned long end) |
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{ |
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unsigned long set; |
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for (set = start; set <= end; set += (0x10 - 3)) { |
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__asm__ __volatile__ ( |
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"cpushl %%ic,(%0)\n\t" |
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"addq%.l #1,%0\n\t" |
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"cpushl %%ic,(%0)\n\t" |
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"addq%.l #1,%0\n\t" |
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"cpushl %%ic,(%0)\n\t" |
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"addq%.l #1,%0\n\t" |
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"cpushl %%ic,(%0)" |
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: "=a" (set) |
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: "a" (set)); |
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} |
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} |
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static inline void flush_cf_dcache(unsigned long start, unsigned long end) |
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{ |
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unsigned long set; |
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for (set = start; set <= end; set += (0x10 - 3)) { |
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__asm__ __volatile__ ( |
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"cpushl %%dc,(%0)\n\t" |
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"addq%.l #1,%0\n\t" |
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"cpushl %%dc,(%0)\n\t" |
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"addq%.l #1,%0\n\t" |
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"cpushl %%dc,(%0)\n\t" |
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"addq%.l #1,%0\n\t" |
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"cpushl %%dc,(%0)" |
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: "=a" (set) |
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: "a" (set)); |
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} |
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} |
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static inline void flush_cf_bcache(unsigned long start, unsigned long end) |
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{ |
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unsigned long set; |
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for (set = start; set <= end; set += (0x10 - 3)) { |
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__asm__ __volatile__ ( |
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"cpushl %%bc,(%0)\n\t" |
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"addq%.l #1,%0\n\t" |
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"cpushl %%bc,(%0)\n\t" |
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"addq%.l #1,%0\n\t" |
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"cpushl %%bc,(%0)\n\t" |
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"addq%.l #1,%0\n\t" |
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"cpushl %%bc,(%0)" |
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: "=a" (set) |
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: "a" (set)); |
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} |
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} |
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/* |
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* Cache handling functions |
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*/ |
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static inline void flush_icache(void) |
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{ |
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if (CPU_IS_COLDFIRE) { |
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flush_cf_icache(0, ICACHE_MAX_ADDR); |
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} else if (CPU_IS_040_OR_060) { |
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asm volatile ( "nop\n" |
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" .chip 68040\n" |
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" cpusha %bc\n" |
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" .chip 68k"); |
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} else { |
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unsigned long tmp; |
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asm volatile ( "movec %%cacr,%0\n" |
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" or.w %1,%0\n" |
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" movec %0,%%cacr" |
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: "=&d" (tmp) |
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: "id" (FLUSH_I)); |
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} |
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} |
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/* |
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* invalidate the cache for the specified memory range. |
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* It starts at the physical address specified for |
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* the given number of bytes. |
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*/ |
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extern void cache_clear(unsigned long paddr, int len); |
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/* |
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* push any dirty cache in the specified memory range. |
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* It starts at the physical address specified for |
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* the given number of bytes. |
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*/ |
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extern void cache_push(unsigned long paddr, int len); |
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/* |
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* push and invalidate pages in the specified user virtual |
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* memory range. |
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*/ |
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extern void cache_push_v(unsigned long vaddr, int len); |
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/* This is needed whenever the virtual mapping of the current |
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process changes. */ |
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#define __flush_cache_all() \ |
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({ \ |
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if (CPU_IS_COLDFIRE) { \ |
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flush_cf_dcache(0, DCACHE_MAX_ADDR); \ |
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} else if (CPU_IS_040_OR_060) { \ |
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__asm__ __volatile__("nop\n\t" \ |
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".chip 68040\n\t" \ |
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"cpusha %dc\n\t" \ |
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".chip 68k"); \ |
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} else { \ |
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unsigned long _tmp; \ |
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__asm__ __volatile__("movec %%cacr,%0\n\t" \ |
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"orw %1,%0\n\t" \ |
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"movec %0,%%cacr" \ |
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: "=&d" (_tmp) \ |
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: "di" (FLUSH_I_AND_D)); \ |
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} \ |
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}) |
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#define __flush_cache_030() \ |
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({ \ |
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if (CPU_IS_020_OR_030) { \ |
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unsigned long _tmp; \ |
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__asm__ __volatile__("movec %%cacr,%0\n\t" \ |
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"orw %1,%0\n\t" \ |
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"movec %0,%%cacr" \ |
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: "=&d" (_tmp) \ |
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: "di" (FLUSH_I_AND_D)); \ |
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} \ |
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}) |
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#define flush_cache_all() __flush_cache_all() |
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#define flush_cache_vmap(start, end) flush_cache_all() |
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#define flush_cache_vunmap(start, end) flush_cache_all() |
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static inline void flush_cache_mm(struct mm_struct *mm) |
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{ |
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if (mm == current->mm) |
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__flush_cache_030(); |
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} |
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#define flush_cache_dup_mm(mm) flush_cache_mm(mm) |
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/* flush_cache_range/flush_cache_page must be macros to avoid |
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a dependency on linux/mm.h, which includes this file... */ |
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static inline void flush_cache_range(struct vm_area_struct *vma, |
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unsigned long start, |
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unsigned long end) |
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{ |
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if (vma->vm_mm == current->mm) |
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__flush_cache_030(); |
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} |
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static inline void flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn) |
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{ |
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if (vma->vm_mm == current->mm) |
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__flush_cache_030(); |
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} |
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/* Push the page at kernel virtual address and clear the icache */ |
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/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */ |
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static inline void __flush_page_to_ram(void *vaddr) |
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{ |
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if (CPU_IS_COLDFIRE) { |
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unsigned long addr, start, end; |
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addr = ((unsigned long) vaddr) & ~(PAGE_SIZE - 1); |
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start = addr & ICACHE_SET_MASK; |
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end = (addr + PAGE_SIZE - 1) & ICACHE_SET_MASK; |
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if (start > end) { |
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flush_cf_bcache(0, end); |
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end = ICACHE_MAX_ADDR; |
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} |
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flush_cf_bcache(start, end); |
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} else if (CPU_IS_040_OR_060) { |
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__asm__ __volatile__("nop\n\t" |
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".chip 68040\n\t" |
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"cpushp %%bc,(%0)\n\t" |
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".chip 68k" |
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: : "a" (__pa(vaddr))); |
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} else { |
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unsigned long _tmp; |
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__asm__ __volatile__("movec %%cacr,%0\n\t" |
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"orw %1,%0\n\t" |
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"movec %0,%%cacr" |
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: "=&d" (_tmp) |
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: "di" (FLUSH_I)); |
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} |
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} |
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 |
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#define flush_dcache_page(page) __flush_page_to_ram(page_address(page)) |
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#define flush_dcache_mmap_lock(mapping) do { } while (0) |
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#define flush_dcache_mmap_unlock(mapping) do { } while (0) |
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#define flush_icache_page(vma, page) __flush_page_to_ram(page_address(page)) |
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extern void flush_icache_user_page(struct vm_area_struct *vma, struct page *page, |
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unsigned long addr, int len); |
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extern void flush_icache_range(unsigned long address, unsigned long endaddr); |
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extern void flush_icache_user_range(unsigned long address, |
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unsigned long endaddr); |
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static inline void copy_to_user_page(struct vm_area_struct *vma, |
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struct page *page, unsigned long vaddr, |
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void *dst, void *src, int len) |
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{ |
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flush_cache_page(vma, vaddr, page_to_pfn(page)); |
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memcpy(dst, src, len); |
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flush_icache_user_page(vma, page, vaddr, len); |
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} |
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static inline void copy_from_user_page(struct vm_area_struct *vma, |
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struct page *page, unsigned long vaddr, |
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void *dst, void *src, int len) |
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{ |
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flush_cache_page(vma, vaddr, page_to_pfn(page)); |
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memcpy(dst, src, len); |
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} |
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#endif /* _M68K_CACHEFLUSH_H */
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