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493 lines
13 KiB
493 lines
13 KiB
| |
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| kernel_ex.sa 3.3 12/19/90 |
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| |
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| This file contains routines to force exception status in the |
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| fpu for exceptional cases detected or reported within the |
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| transcendental functions. Typically, the t_xx routine will |
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| set the appropriate bits in the USER_FPSR word on the stack. |
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| The bits are tested in gen_except.sa to determine if an exceptional |
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| situation needs to be created on return from the FPSP. |
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| |
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| Copyright (C) Motorola, Inc. 1990 |
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| All Rights Reserved |
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| |
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| For details on the license for this file, please see the |
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| file, README, in this same directory. |
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KERNEL_EX: |idnt 2,1 | Motorola 040 Floating Point Software Package |
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|section 8 |
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#include "fpsp.h" |
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mns_inf: .long 0xffff0000,0x00000000,0x00000000 |
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pls_inf: .long 0x7fff0000,0x00000000,0x00000000 |
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nan: .long 0x7fff0000,0xffffffff,0xffffffff |
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huge: .long 0x7ffe0000,0xffffffff,0xffffffff |
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|xref ovf_r_k |
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|xref unf_sub |
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|xref nrm_set |
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.global t_dz |
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.global t_dz2 |
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.global t_operr |
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.global t_unfl |
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.global t_ovfl |
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.global t_ovfl2 |
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.global t_inx2 |
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.global t_frcinx |
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.global t_extdnrm |
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.global t_resdnrm |
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.global dst_nan |
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.global src_nan |
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| |
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| DZ exception |
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| |
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| |
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| if dz trap disabled |
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| store properly signed inf (use sign of etemp) into fp0 |
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| set FPSR exception status dz bit, condition code |
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| inf bit, and accrued dz bit |
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| return |
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| frestore the frame into the machine (done by unimp_hd) |
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| |
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| else dz trap enabled |
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| set exception status bit & accrued bits in FPSR |
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| set flag to disable sto_res from corrupting fp register |
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| return |
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| frestore the frame into the machine (done by unimp_hd) |
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| |
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| t_dz2 is used by monadic functions such as flogn (from do_func). |
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| t_dz is used by monadic functions such as satanh (from the |
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| transcendental function). |
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| |
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t_dz2: |
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bsetb #neg_bit,FPSR_CC(%a6) |set neg bit in FPSR |
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fmovel #0,%FPSR |clr status bits (Z set) |
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btstb #dz_bit,FPCR_ENABLE(%a6) |test FPCR for dz exc enabled |
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bnes dz_ena_end |
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bras m_inf |flogx always returns -inf |
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t_dz: |
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fmovel #0,%FPSR |clr status bits (Z set) |
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btstb #dz_bit,FPCR_ENABLE(%a6) |test FPCR for dz exc enabled |
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bnes dz_ena |
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| |
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| dz disabled |
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| |
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btstb #sign_bit,ETEMP_EX(%a6) |check sign for neg or pos |
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beqs p_inf |branch if pos sign |
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m_inf: |
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fmovemx mns_inf,%fp0-%fp0 |load -inf |
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bsetb #neg_bit,FPSR_CC(%a6) |set neg bit in FPSR |
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bras set_fpsr |
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p_inf: |
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fmovemx pls_inf,%fp0-%fp0 |load +inf |
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set_fpsr: |
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orl #dzinf_mask,USER_FPSR(%a6) |set I,DZ,ADZ |
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rts |
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| dz enabled |
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| |
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dz_ena: |
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btstb #sign_bit,ETEMP_EX(%a6) |check sign for neg or pos |
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beqs dz_ena_end |
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bsetb #neg_bit,FPSR_CC(%a6) |set neg bit in FPSR |
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dz_ena_end: |
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orl #dzinf_mask,USER_FPSR(%a6) |set I,DZ,ADZ |
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st STORE_FLG(%a6) |
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rts |
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| |
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| OPERR exception |
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| |
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| if (operr trap disabled) |
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| set FPSR exception status operr bit, condition code |
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| nan bit; Store default NAN into fp0 |
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| frestore the frame into the machine (done by unimp_hd) |
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| |
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| else (operr trap enabled) |
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| set FPSR exception status operr bit, accrued operr bit |
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| set flag to disable sto_res from corrupting fp register |
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| frestore the frame into the machine (done by unimp_hd) |
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| |
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t_operr: |
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orl #opnan_mask,USER_FPSR(%a6) |set NaN, OPERR, AIOP |
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btstb #operr_bit,FPCR_ENABLE(%a6) |test FPCR for operr enabled |
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bnes op_ena |
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fmovemx nan,%fp0-%fp0 |load default nan |
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rts |
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op_ena: |
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st STORE_FLG(%a6) |do not corrupt destination |
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rts |
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| |
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| t_unfl --- UNFL exception |
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| |
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| This entry point is used by all routines requiring unfl, inex2, |
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| aunfl, and ainex to be set on exit. |
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| |
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| On entry, a0 points to the exceptional operand. The final exceptional |
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| operand is built in FP_SCR1 and only the sign from the original operand |
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| is used. |
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| |
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t_unfl: |
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clrl FP_SCR1(%a6) |set exceptional operand to zero |
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clrl FP_SCR1+4(%a6) |
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clrl FP_SCR1+8(%a6) |
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tstb (%a0) |extract sign from caller's exop |
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bpls unfl_signok |
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bset #sign_bit,FP_SCR1(%a6) |
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unfl_signok: |
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leal FP_SCR1(%a6),%a0 |
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orl #unfinx_mask,USER_FPSR(%a6) |
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| ;set UNFL, INEX2, AUNFL, AINEX |
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unfl_con: |
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btstb #unfl_bit,FPCR_ENABLE(%a6) |
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beqs unfl_dis |
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unfl_ena: |
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bfclr STAG(%a6){#5:#3} |clear wbtm66,wbtm1,wbtm0 |
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bsetb #wbtemp15_bit,WB_BYTE(%a6) |set wbtemp15 |
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bsetb #sticky_bit,STICKY(%a6) |set sticky bit |
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bclrb #E1,E_BYTE(%a6) |
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unfl_dis: |
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bfextu FPCR_MODE(%a6){#0:#2},%d0 |get round precision |
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bclrb #sign_bit,LOCAL_EX(%a0) |
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sne LOCAL_SGN(%a0) |convert to internal ext format |
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bsr unf_sub |returns IEEE result at a0 |
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| ;and sets FPSR_CC accordingly |
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bfclr LOCAL_SGN(%a0){#0:#8} |convert back to IEEE ext format |
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beqs unfl_fin |
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bsetb #sign_bit,LOCAL_EX(%a0) |
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bsetb #sign_bit,FP_SCR1(%a6) |set sign bit of exc operand |
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unfl_fin: |
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fmovemx (%a0),%fp0-%fp0 |store result in fp0 |
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rts |
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| |
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| t_ovfl2 --- OVFL exception (without inex2 returned) |
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| |
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| This entry is used by scale to force catastrophic overflow. The |
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| ovfl, aovfl, and ainex bits are set, but not the inex2 bit. |
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| |
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t_ovfl2: |
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orl #ovfl_inx_mask,USER_FPSR(%a6) |
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movel ETEMP(%a6),FP_SCR1(%a6) |
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movel ETEMP_HI(%a6),FP_SCR1+4(%a6) |
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movel ETEMP_LO(%a6),FP_SCR1+8(%a6) |
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| |
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| Check for single or double round precision. If single, check if |
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| the lower 40 bits of ETEMP are zero; if not, set inex2. If double, |
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| check if the lower 21 bits are zero; if not, set inex2. |
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| |
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moveb FPCR_MODE(%a6),%d0 |
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andib #0xc0,%d0 |
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beq t_work |if extended, finish ovfl processing |
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cmpib #0x40,%d0 |test for single |
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bnes t_dbl |
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t_sgl: |
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tstb ETEMP_LO(%a6) |
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bnes t_setinx2 |
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movel ETEMP_HI(%a6),%d0 |
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andil #0xff,%d0 |look at only lower 8 bits |
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bnes t_setinx2 |
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bra t_work |
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t_dbl: |
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movel ETEMP_LO(%a6),%d0 |
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andil #0x7ff,%d0 |look at only lower 11 bits |
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beq t_work |
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t_setinx2: |
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orl #inex2_mask,USER_FPSR(%a6) |
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bras t_work |
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| |
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| t_ovfl --- OVFL exception |
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| |
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|** Note: the exc operand is returned in ETEMP. |
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t_ovfl: |
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orl #ovfinx_mask,USER_FPSR(%a6) |
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t_work: |
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btstb #ovfl_bit,FPCR_ENABLE(%a6) |test FPCR for ovfl enabled |
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beqs ovf_dis |
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ovf_ena: |
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clrl FP_SCR1(%a6) |set exceptional operand |
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clrl FP_SCR1+4(%a6) |
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clrl FP_SCR1+8(%a6) |
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bfclr STAG(%a6){#5:#3} |clear wbtm66,wbtm1,wbtm0 |
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bclrb #wbtemp15_bit,WB_BYTE(%a6) |clear wbtemp15 |
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bsetb #sticky_bit,STICKY(%a6) |set sticky bit |
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bclrb #E1,E_BYTE(%a6) |
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| ;fall through to disabled case |
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| For disabled overflow call 'ovf_r_k'. This routine loads the |
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| correct result based on the rounding precision, destination |
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| format, rounding mode and sign. |
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| |
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ovf_dis: |
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bsr ovf_r_k |returns unsigned ETEMP_EX |
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| ;and sets FPSR_CC accordingly. |
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bfclr ETEMP_SGN(%a6){#0:#8} |fix sign |
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beqs ovf_pos |
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bsetb #sign_bit,ETEMP_EX(%a6) |
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bsetb #sign_bit,FP_SCR1(%a6) |set exceptional operand sign |
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ovf_pos: |
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fmovemx ETEMP(%a6),%fp0-%fp0 |move the result to fp0 |
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rts |
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| INEX2 exception |
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| The inex2 and ainex bits are set. |
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t_inx2: |
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orl #inx2a_mask,USER_FPSR(%a6) |set INEX2, AINEX |
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rts |
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| Force Inex2 |
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| |
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| This routine is called by the transcendental routines to force |
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| the inex2 exception bits set in the FPSR. If the underflow bit |
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| is set, but the underflow trap was not taken, the aunfl bit in |
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| the FPSR must be set. |
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| |
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t_frcinx: |
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orl #inx2a_mask,USER_FPSR(%a6) |set INEX2, AINEX |
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btstb #unfl_bit,FPSR_EXCEPT(%a6) |test for unfl bit set |
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beqs no_uacc1 |if clear, do not set aunfl |
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bsetb #aunfl_bit,FPSR_AEXCEPT(%a6) |
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no_uacc1: |
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rts |
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| |
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| DST_NAN |
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| |
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| Determine if the destination nan is signalling or non-signalling, |
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| and set the FPSR bits accordingly. See the MC68040 User's Manual |
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| section 3.2.2.5 NOT-A-NUMBERS. |
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| |
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dst_nan: |
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btstb #sign_bit,FPTEMP_EX(%a6) |test sign of nan |
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beqs dst_pos |if clr, it was positive |
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bsetb #neg_bit,FPSR_CC(%a6) |set N bit |
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dst_pos: |
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btstb #signan_bit,FPTEMP_HI(%a6) |check if signalling |
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beqs dst_snan |branch if signalling |
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fmovel %d1,%fpcr |restore user's rmode/prec |
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fmovex FPTEMP(%a6),%fp0 |return the non-signalling nan |
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| Check the source nan. If it is signalling, snan will be reported. |
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moveb STAG(%a6),%d0 |
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andib #0xe0,%d0 |
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cmpib #0x60,%d0 |
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bnes no_snan |
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btstb #signan_bit,ETEMP_HI(%a6) |check if signalling |
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bnes no_snan |
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orl #snaniop_mask,USER_FPSR(%a6) |set NAN, SNAN, AIOP |
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no_snan: |
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rts |
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dst_snan: |
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btstb #snan_bit,FPCR_ENABLE(%a6) |check if trap enabled |
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beqs dst_dis |branch if disabled |
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orb #nan_tag,DTAG(%a6) |set up dtag for nan |
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st STORE_FLG(%a6) |do not store a result |
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orl #snaniop_mask,USER_FPSR(%a6) |set NAN, SNAN, AIOP |
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rts |
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dst_dis: |
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bsetb #signan_bit,FPTEMP_HI(%a6) |set SNAN bit in sop |
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fmovel %d1,%fpcr |restore user's rmode/prec |
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fmovex FPTEMP(%a6),%fp0 |load non-sign. nan |
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orl #snaniop_mask,USER_FPSR(%a6) |set NAN, SNAN, AIOP |
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rts |
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| SRC_NAN |
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| |
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| Determine if the source nan is signalling or non-signalling, |
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| and set the FPSR bits accordingly. See the MC68040 User's Manual |
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| section 3.2.2.5 NOT-A-NUMBERS. |
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| |
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src_nan: |
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btstb #sign_bit,ETEMP_EX(%a6) |test sign of nan |
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beqs src_pos |if clr, it was positive |
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bsetb #neg_bit,FPSR_CC(%a6) |set N bit |
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src_pos: |
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btstb #signan_bit,ETEMP_HI(%a6) |check if signalling |
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beqs src_snan |branch if signalling |
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fmovel %d1,%fpcr |restore user's rmode/prec |
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fmovex ETEMP(%a6),%fp0 |return the non-signalling nan |
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rts |
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src_snan: |
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btstb #snan_bit,FPCR_ENABLE(%a6) |check if trap enabled |
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beqs src_dis |branch if disabled |
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bsetb #signan_bit,ETEMP_HI(%a6) |set SNAN bit in sop |
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orb #norm_tag,DTAG(%a6) |set up dtag for norm |
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orb #nan_tag,STAG(%a6) |set up stag for nan |
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st STORE_FLG(%a6) |do not store a result |
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orl #snaniop_mask,USER_FPSR(%a6) |set NAN, SNAN, AIOP |
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rts |
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src_dis: |
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bsetb #signan_bit,ETEMP_HI(%a6) |set SNAN bit in sop |
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fmovel %d1,%fpcr |restore user's rmode/prec |
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fmovex ETEMP(%a6),%fp0 |load non-sign. nan |
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orl #snaniop_mask,USER_FPSR(%a6) |set NAN, SNAN, AIOP |
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rts |
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| |
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| For all functions that have a denormalized input and that f(x)=x, |
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| this is the entry point |
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t_extdnrm: |
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orl #unfinx_mask,USER_FPSR(%a6) |
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| ;set UNFL, INEX2, AUNFL, AINEX |
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bras xdnrm_con |
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| |
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| Entry point for scale with extended denorm. The function does |
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| not set inex2, aunfl, or ainex. |
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t_resdnrm: |
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orl #unfl_mask,USER_FPSR(%a6) |
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xdnrm_con: |
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btstb #unfl_bit,FPCR_ENABLE(%a6) |
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beqs xdnrm_dis |
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| |
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| If exceptions are enabled, the additional task of setting up WBTEMP |
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| is needed so that when the underflow exception handler is entered, |
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| the user perceives no difference between what the 040 provides vs. |
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| what the FPSP provides. |
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| |
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xdnrm_ena: |
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movel %a0,-(%a7) |
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movel LOCAL_EX(%a0),FP_SCR1(%a6) |
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movel LOCAL_HI(%a0),FP_SCR1+4(%a6) |
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movel LOCAL_LO(%a0),FP_SCR1+8(%a6) |
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lea FP_SCR1(%a6),%a0 |
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bclrb #sign_bit,LOCAL_EX(%a0) |
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sne LOCAL_SGN(%a0) |convert to internal ext format |
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tstw LOCAL_EX(%a0) |check if input is denorm |
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beqs xdnrm_dn |if so, skip nrm_set |
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bsr nrm_set |normalize the result (exponent |
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| ;will be negative |
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xdnrm_dn: |
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bclrb #sign_bit,LOCAL_EX(%a0) |take off false sign |
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bfclr LOCAL_SGN(%a0){#0:#8} |change back to IEEE ext format |
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beqs xdep |
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bsetb #sign_bit,LOCAL_EX(%a0) |
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xdep: |
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bfclr STAG(%a6){#5:#3} |clear wbtm66,wbtm1,wbtm0 |
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bsetb #wbtemp15_bit,WB_BYTE(%a6) |set wbtemp15 |
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bclrb #sticky_bit,STICKY(%a6) |clear sticky bit |
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bclrb #E1,E_BYTE(%a6) |
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movel (%a7)+,%a0 |
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xdnrm_dis: |
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bfextu FPCR_MODE(%a6){#0:#2},%d0 |get round precision |
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bnes not_ext |if not round extended, store |
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| ;IEEE defaults |
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is_ext: |
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btstb #sign_bit,LOCAL_EX(%a0) |
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beqs xdnrm_store |
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bsetb #neg_bit,FPSR_CC(%a6) |set N bit in FPSR_CC |
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bras xdnrm_store |
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not_ext: |
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bclrb #sign_bit,LOCAL_EX(%a0) |
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sne LOCAL_SGN(%a0) |convert to internal ext format |
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bsr unf_sub |returns IEEE result pointed by |
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| ;a0; sets FPSR_CC accordingly |
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bfclr LOCAL_SGN(%a0){#0:#8} |convert back to IEEE ext format |
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beqs xdnrm_store |
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bsetb #sign_bit,LOCAL_EX(%a0) |
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xdnrm_store: |
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fmovemx (%a0),%fp0-%fp0 |store result in fp0 |
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rts |
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| |
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| This subroutine is used for dyadic operations that use an extended |
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| denorm within the kernel. The approach used is to capture the frame, |
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| fix/restore. |
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| |
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.global t_avoid_unsupp |
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t_avoid_unsupp: |
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link %a2,#-LOCAL_SIZE |so that a2 fpsp.h negative |
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| ;offsets may be used |
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fsave -(%a7) |
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tstb 1(%a7) |check if idle, exit if so |
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beq idle_end |
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btstb #E1,E_BYTE(%a2) |check for an E1 exception if |
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| ;enabled, there is an unsupp |
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beq end_avun |else, exit |
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btstb #7,DTAG(%a2) |check for denorm destination |
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beqs src_den |else, must be a source denorm |
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| |
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| handle destination denorm |
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| |
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lea FPTEMP(%a2),%a0 |
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btstb #sign_bit,LOCAL_EX(%a0) |
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sne LOCAL_SGN(%a0) |convert to internal ext format |
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bclrb #7,DTAG(%a2) |set DTAG to norm |
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bsr nrm_set |normalize result, exponent |
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| ;will become negative |
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bclrb #sign_bit,LOCAL_EX(%a0) |get rid of fake sign |
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bfclr LOCAL_SGN(%a0){#0:#8} |convert back to IEEE ext format |
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beqs ck_src_den |check if source is also denorm |
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bsetb #sign_bit,LOCAL_EX(%a0) |
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ck_src_den: |
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btstb #7,STAG(%a2) |
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beqs end_avun |
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src_den: |
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lea ETEMP(%a2),%a0 |
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btstb #sign_bit,LOCAL_EX(%a0) |
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sne LOCAL_SGN(%a0) |convert to internal ext format |
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bclrb #7,STAG(%a2) |set STAG to norm |
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bsr nrm_set |normalize result, exponent |
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| ;will become negative |
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bclrb #sign_bit,LOCAL_EX(%a0) |get rid of fake sign |
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bfclr LOCAL_SGN(%a0){#0:#8} |convert back to IEEE ext format |
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beqs den_com |
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bsetb #sign_bit,LOCAL_EX(%a0) |
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den_com: |
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moveb #0xfe,CU_SAVEPC(%a2) |set continue frame |
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clrw NMNEXC(%a2) |clear NMNEXC |
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bclrb #E1,E_BYTE(%a2) |
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| fmove.l %FPSR,FPSR_SHADOW(%a2) |
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| bset.b #SFLAG,E_BYTE(%a2) |
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| bset.b #XFLAG,T_BYTE(%a2) |
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end_avun: |
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frestore (%a7)+ |
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unlk %a2 |
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rts |
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idle_end: |
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addl #4,%a7 |
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unlk %a2 |
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rts |
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|end
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