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162 lines
4.2 KiB
162 lines
4.2 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/***************************************************************************/ |
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/* |
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* pit.c -- Freescale ColdFire PIT timer. Currently this type of |
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* hardware timer only exists in the Freescale ColdFire |
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* 5270/5271, 5282 and 5208 CPUs. No doubt newer ColdFire |
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* family members will probably use it too. |
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* |
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* Copyright (C) 1999-2008, Greg Ungerer ([email protected]) |
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* Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com) |
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*/ |
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/***************************************************************************/ |
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#include <linux/kernel.h> |
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#include <linux/sched.h> |
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#include <linux/param.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/clockchips.h> |
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#include <asm/machdep.h> |
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#include <asm/io.h> |
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#include <asm/coldfire.h> |
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#include <asm/mcfpit.h> |
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#include <asm/mcfsim.h> |
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/***************************************************************************/ |
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/* |
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* By default use timer1 as the system clock timer. |
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*/ |
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#define FREQ ((MCF_CLK / 2) / 64) |
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#define TA(a) (MCFPIT_BASE1 + (a)) |
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#define PIT_CYCLES_PER_JIFFY (FREQ / HZ) |
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static u32 pit_cnt; |
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/* |
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* Initialize the PIT timer. |
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* |
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* This is also called after resume to bring the PIT into operation again. |
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*/ |
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static int cf_pit_set_periodic(struct clock_event_device *evt) |
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{ |
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__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR)); |
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__raw_writew(PIT_CYCLES_PER_JIFFY, TA(MCFPIT_PMR)); |
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__raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | |
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MCFPIT_PCSR_OVW | MCFPIT_PCSR_RLD | |
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MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR)); |
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return 0; |
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} |
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static int cf_pit_set_oneshot(struct clock_event_device *evt) |
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{ |
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__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR)); |
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__raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | |
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MCFPIT_PCSR_OVW | MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR)); |
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return 0; |
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} |
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static int cf_pit_shutdown(struct clock_event_device *evt) |
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{ |
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__raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR)); |
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return 0; |
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} |
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/* |
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* Program the next event in oneshot mode |
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* |
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* Delta is given in PIT ticks |
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*/ |
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static int cf_pit_next_event(unsigned long delta, |
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struct clock_event_device *evt) |
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{ |
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__raw_writew(delta, TA(MCFPIT_PMR)); |
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return 0; |
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} |
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struct clock_event_device cf_pit_clockevent = { |
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.name = "pit", |
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.features = CLOCK_EVT_FEAT_PERIODIC | |
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CLOCK_EVT_FEAT_ONESHOT, |
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.set_state_shutdown = cf_pit_shutdown, |
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.set_state_periodic = cf_pit_set_periodic, |
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.set_state_oneshot = cf_pit_set_oneshot, |
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.set_next_event = cf_pit_next_event, |
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.shift = 32, |
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.irq = MCF_IRQ_PIT1, |
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}; |
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/***************************************************************************/ |
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static irqreturn_t pit_tick(int irq, void *dummy) |
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{ |
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struct clock_event_device *evt = &cf_pit_clockevent; |
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u16 pcsr; |
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/* Reset the ColdFire timer */ |
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pcsr = __raw_readw(TA(MCFPIT_PCSR)); |
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__raw_writew(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR)); |
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pit_cnt += PIT_CYCLES_PER_JIFFY; |
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evt->event_handler(evt); |
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return IRQ_HANDLED; |
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} |
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/***************************************************************************/ |
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static u64 pit_read_clk(struct clocksource *cs) |
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{ |
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unsigned long flags; |
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u32 cycles; |
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u16 pcntr; |
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local_irq_save(flags); |
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pcntr = __raw_readw(TA(MCFPIT_PCNTR)); |
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cycles = pit_cnt; |
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local_irq_restore(flags); |
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return cycles + PIT_CYCLES_PER_JIFFY - pcntr; |
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} |
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/***************************************************************************/ |
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static struct clocksource pit_clk = { |
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.name = "pit", |
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.rating = 100, |
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.read = pit_read_clk, |
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.mask = CLOCKSOURCE_MASK(32), |
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}; |
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/***************************************************************************/ |
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void hw_timer_init(void) |
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{ |
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int ret; |
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cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id()); |
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cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32); |
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cf_pit_clockevent.max_delta_ns = |
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clockevent_delta2ns(0xFFFF, &cf_pit_clockevent); |
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cf_pit_clockevent.max_delta_ticks = 0xFFFF; |
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cf_pit_clockevent.min_delta_ns = |
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clockevent_delta2ns(0x3f, &cf_pit_clockevent); |
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cf_pit_clockevent.min_delta_ticks = 0x3f; |
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clockevents_register_device(&cf_pit_clockevent); |
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ret = request_irq(MCF_IRQ_PIT1, pit_tick, IRQF_TIMER, "timer", NULL); |
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if (ret) { |
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pr_err("Failed to request irq %d (timer): %pe\n", MCF_IRQ_PIT1, |
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ERR_PTR(ret)); |
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} |
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clocksource_register_hz(&pit_clk, FREQ); |
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} |
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/***************************************************************************/
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