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120 lines
2.7 KiB
120 lines
2.7 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Cache flushing routines. |
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* |
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* Copyright (C) 1999-2001, 2005 Hewlett-Packard Co |
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* David Mosberger-Tang <davidm@hpl.hp.com> |
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* |
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* 05/28/05 Zoltan Menyhart Dynamic stride size |
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*/ |
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#include <asm/asmmacro.h> |
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#include <asm/export.h> |
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/* |
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* flush_icache_range(start,end) |
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* |
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* Make i-cache(s) coherent with d-caches. |
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* |
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* Must deal with range from start to end-1 but nothing else (need to |
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* be careful not to touch addresses that may be unmapped). |
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* |
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* Note: "in0" and "in1" are preserved for debugging purposes. |
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*/ |
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.section .kprobes.text,"ax" |
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GLOBAL_ENTRY(flush_icache_range) |
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.prologue |
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alloc r2=ar.pfs,2,0,0,0 |
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movl r3=ia64_i_cache_stride_shift |
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mov r21=1 |
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;; |
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ld8 r20=[r3] // r20: stride shift |
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sub r22=in1,r0,1 // last byte address |
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;; |
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shr.u r23=in0,r20 // start / (stride size) |
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shr.u r22=r22,r20 // (last byte address) / (stride size) |
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shl r21=r21,r20 // r21: stride size of the i-cache(s) |
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;; |
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sub r8=r22,r23 // number of strides - 1 |
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shl r24=r23,r20 // r24: addresses for "fc.i" = |
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// "start" rounded down to stride boundary |
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.save ar.lc,r3 |
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mov r3=ar.lc // save ar.lc |
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;; |
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.body |
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mov ar.lc=r8 |
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;; |
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/* |
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* 32 byte aligned loop, even number of (actually 2) bundles |
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*/ |
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.Loop: fc.i r24 // issuable on M0 only |
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add r24=r21,r24 // we flush "stride size" bytes per iteration |
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nop.i 0 |
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br.cloop.sptk.few .Loop |
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;; |
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sync.i |
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;; |
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srlz.i |
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;; |
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mov ar.lc=r3 // restore ar.lc |
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br.ret.sptk.many rp |
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END(flush_icache_range) |
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EXPORT_SYMBOL_GPL(flush_icache_range) |
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/* |
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* clflush_cache_range(start,size) |
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* |
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* Flush cache lines from start to start+size-1. |
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* |
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* Must deal with range from start to start+size-1 but nothing else |
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* (need to be careful not to touch addresses that may be |
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* unmapped). |
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* |
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* Note: "in0" and "in1" are preserved for debugging purposes. |
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*/ |
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.section .kprobes.text,"ax" |
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GLOBAL_ENTRY(clflush_cache_range) |
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.prologue |
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alloc r2=ar.pfs,2,0,0,0 |
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movl r3=ia64_cache_stride_shift |
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mov r21=1 |
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add r22=in1,in0 |
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;; |
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ld8 r20=[r3] // r20: stride shift |
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sub r22=r22,r0,1 // last byte address |
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;; |
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shr.u r23=in0,r20 // start / (stride size) |
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shr.u r22=r22,r20 // (last byte address) / (stride size) |
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shl r21=r21,r20 // r21: stride size of the i-cache(s) |
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;; |
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sub r8=r22,r23 // number of strides - 1 |
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shl r24=r23,r20 // r24: addresses for "fc" = |
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// "start" rounded down to stride |
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// boundary |
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.save ar.lc,r3 |
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mov r3=ar.lc // save ar.lc |
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;; |
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.body |
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mov ar.lc=r8 |
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;; |
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/* |
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* 32 byte aligned loop, even number of (actually 2) bundles |
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*/ |
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.Loop_fc: |
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fc r24 // issuable on M0 only |
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add r24=r21,r24 // we flush "stride size" bytes per iteration |
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nop.i 0 |
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br.cloop.sptk.few .Loop_fc |
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;; |
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sync.i |
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;; |
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srlz.i |
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;; |
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mov ar.lc=r3 // restore ar.lc |
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br.ret.sptk.many rp |
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END(clflush_cache_range)
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