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237 lines
6.4 KiB
237 lines
6.4 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Instruction-patching support. |
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* |
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* Copyright (C) 2003 Hewlett-Packard Co |
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* David Mosberger-Tang <[email protected]> |
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*/ |
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#include <linux/init.h> |
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#include <linux/string.h> |
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#include <asm/patch.h> |
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#include <asm/processor.h> |
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#include <asm/sections.h> |
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#include <asm/unistd.h> |
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/* |
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* This was adapted from code written by Tony Luck: |
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* |
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* The 64-bit value in a "movl reg=value" is scattered between the two words of the bundle |
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* like this: |
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* |
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* 6 6 5 4 3 2 1 |
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* 3210987654321098765432109876543210987654321098765432109876543210 |
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* ABBBBBBBBBBBBBBBBBBBBBBBCCCCCCCCCCCCCCCCCCDEEEEEFFFFFFFFFGGGGGGG |
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* |
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* CCCCCCCCCCCCCCCCCCxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx |
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* xxxxAFFFFFFFFFEEEEEDxGGGGGGGxxxxxxxxxxxxxBBBBBBBBBBBBBBBBBBBBBBB |
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*/ |
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static u64 |
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get_imm64 (u64 insn_addr) |
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{ |
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u64 *p = (u64 *) (insn_addr & -16); /* mask out slot number */ |
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return ( (p[1] & 0x0800000000000000UL) << 4) | /*A*/ |
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((p[1] & 0x00000000007fffffUL) << 40) | /*B*/ |
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((p[0] & 0xffffc00000000000UL) >> 24) | /*C*/ |
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((p[1] & 0x0000100000000000UL) >> 23) | /*D*/ |
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((p[1] & 0x0003e00000000000UL) >> 29) | /*E*/ |
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((p[1] & 0x07fc000000000000UL) >> 43) | /*F*/ |
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((p[1] & 0x000007f000000000UL) >> 36); /*G*/ |
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} |
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/* Patch instruction with "val" where "mask" has 1 bits. */ |
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void |
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ia64_patch (u64 insn_addr, u64 mask, u64 val) |
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{ |
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u64 m0, m1, v0, v1, b0, b1, *b = (u64 *) (insn_addr & -16); |
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# define insn_mask ((1UL << 41) - 1) |
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unsigned long shift; |
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b0 = b[0]; b1 = b[1]; |
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shift = 5 + 41 * (insn_addr % 16); /* 5 bits of template, then 3 x 41-bit instructions */ |
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if (shift >= 64) { |
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m1 = mask << (shift - 64); |
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v1 = val << (shift - 64); |
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} else { |
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m0 = mask << shift; m1 = mask >> (64 - shift); |
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v0 = val << shift; v1 = val >> (64 - shift); |
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b[0] = (b0 & ~m0) | (v0 & m0); |
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} |
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b[1] = (b1 & ~m1) | (v1 & m1); |
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} |
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void |
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ia64_patch_imm64 (u64 insn_addr, u64 val) |
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{ |
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/* The assembler may generate offset pointing to either slot 1 |
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or slot 2 for a long (2-slot) instruction, occupying slots 1 |
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and 2. */ |
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insn_addr &= -16UL; |
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ia64_patch(insn_addr + 2, |
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0x01fffefe000UL, ( ((val & 0x8000000000000000UL) >> 27) /* bit 63 -> 36 */ |
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| ((val & 0x0000000000200000UL) << 0) /* bit 21 -> 21 */ |
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| ((val & 0x00000000001f0000UL) << 6) /* bit 16 -> 22 */ |
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| ((val & 0x000000000000ff80UL) << 20) /* bit 7 -> 27 */ |
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| ((val & 0x000000000000007fUL) << 13) /* bit 0 -> 13 */)); |
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ia64_patch(insn_addr + 1, 0x1ffffffffffUL, val >> 22); |
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} |
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void |
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ia64_patch_imm60 (u64 insn_addr, u64 val) |
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{ |
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/* The assembler may generate offset pointing to either slot 1 |
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or slot 2 for a long (2-slot) instruction, occupying slots 1 |
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and 2. */ |
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insn_addr &= -16UL; |
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ia64_patch(insn_addr + 2, |
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0x011ffffe000UL, ( ((val & 0x0800000000000000UL) >> 23) /* bit 59 -> 36 */ |
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| ((val & 0x00000000000fffffUL) << 13) /* bit 0 -> 13 */)); |
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ia64_patch(insn_addr + 1, 0x1fffffffffcUL, val >> 18); |
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} |
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/* |
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* We need sometimes to load the physical address of a kernel |
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* object. Often we can convert the virtual address to physical |
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* at execution time, but sometimes (either for performance reasons |
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* or during error recovery) we cannot to this. Patch the marked |
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* bundles to load the physical address. |
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*/ |
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void __init |
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ia64_patch_vtop (unsigned long start, unsigned long end) |
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{ |
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s32 *offp = (s32 *) start; |
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u64 ip; |
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while (offp < (s32 *) end) { |
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ip = (u64) offp + *offp; |
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/* replace virtual address with corresponding physical address: */ |
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ia64_patch_imm64(ip, ia64_tpa(get_imm64(ip))); |
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ia64_fc((void *) ip); |
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++offp; |
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} |
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ia64_sync_i(); |
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ia64_srlz_i(); |
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} |
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/* |
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* Disable the RSE workaround by turning the conditional branch |
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* that we tagged in each place the workaround was used into an |
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* unconditional branch. |
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*/ |
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void __init |
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ia64_patch_rse (unsigned long start, unsigned long end) |
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{ |
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s32 *offp = (s32 *) start; |
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u64 ip, *b; |
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while (offp < (s32 *) end) { |
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ip = (u64) offp + *offp; |
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b = (u64 *)(ip & -16); |
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b[1] &= ~0xf800000L; |
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ia64_fc((void *) ip); |
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++offp; |
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} |
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ia64_sync_i(); |
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ia64_srlz_i(); |
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} |
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void __init |
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ia64_patch_mckinley_e9 (unsigned long start, unsigned long end) |
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{ |
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static int first_time = 1; |
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int need_workaround; |
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s32 *offp = (s32 *) start; |
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u64 *wp; |
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need_workaround = (local_cpu_data->family == 0x1f && local_cpu_data->model == 0); |
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if (first_time) { |
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first_time = 0; |
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if (need_workaround) |
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printk(KERN_INFO "Leaving McKinley Errata 9 workaround enabled\n"); |
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} |
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if (need_workaround) |
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return; |
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while (offp < (s32 *) end) { |
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wp = (u64 *) ia64_imva((char *) offp + *offp); |
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wp[0] = 0x0000000100000011UL; /* nop.m 0; nop.i 0; br.ret.sptk.many b6 */ |
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wp[1] = 0x0084006880000200UL; |
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wp[2] = 0x0000000100000000UL; /* nop.m 0; nop.i 0; nop.i 0 */ |
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wp[3] = 0x0004000000000200UL; |
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ia64_fc(wp); ia64_fc(wp + 2); |
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++offp; |
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} |
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ia64_sync_i(); |
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ia64_srlz_i(); |
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} |
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static void __init |
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patch_fsyscall_table (unsigned long start, unsigned long end) |
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{ |
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extern unsigned long fsyscall_table[NR_syscalls]; |
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s32 *offp = (s32 *) start; |
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u64 ip; |
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while (offp < (s32 *) end) { |
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ip = (u64) ia64_imva((char *) offp + *offp); |
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ia64_patch_imm64(ip, (u64) fsyscall_table); |
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ia64_fc((void *) ip); |
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++offp; |
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} |
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ia64_sync_i(); |
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ia64_srlz_i(); |
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} |
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static void __init |
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patch_brl_fsys_bubble_down (unsigned long start, unsigned long end) |
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{ |
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extern char fsys_bubble_down[]; |
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s32 *offp = (s32 *) start; |
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u64 ip; |
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while (offp < (s32 *) end) { |
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ip = (u64) offp + *offp; |
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ia64_patch_imm60((u64) ia64_imva((void *) ip), |
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(u64) (fsys_bubble_down - (ip & -16)) / 16); |
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ia64_fc((void *) ip); |
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++offp; |
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} |
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ia64_sync_i(); |
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ia64_srlz_i(); |
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} |
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void __init |
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ia64_patch_gate (void) |
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{ |
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# define START(name) ((unsigned long) __start_gate_##name##_patchlist) |
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# define END(name) ((unsigned long)__end_gate_##name##_patchlist) |
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patch_fsyscall_table(START(fsyscall), END(fsyscall)); |
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patch_brl_fsys_bubble_down(START(brl_fsys_bubble_down), END(brl_fsys_bubble_down)); |
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ia64_patch_vtop(START(vtop), END(vtop)); |
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ia64_patch_mckinley_e9(START(mckinley_e9), END(mckinley_e9)); |
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} |
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void ia64_patch_phys_stack_reg(unsigned long val) |
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{ |
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s32 * offp = (s32 *) __start___phys_stack_reg_patchlist; |
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s32 * end = (s32 *) __end___phys_stack_reg_patchlist; |
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u64 ip, mask, imm; |
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/* see instruction format A4: adds r1 = imm13, r3 */ |
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mask = (0x3fUL << 27) | (0x7f << 13); |
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imm = (((val >> 7) & 0x3f) << 27) | (val & 0x7f) << 13; |
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while (offp < end) { |
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ip = (u64) offp + *offp; |
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ia64_patch(ip, mask, imm); |
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ia64_fc((void *)ip); |
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++offp; |
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} |
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ia64_sync_i(); |
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ia64_srlz_i(); |
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}
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