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1123 lines
27 KiB
1123 lines
27 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* File: mca_asm.S |
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* Purpose: assembly portion of the IA64 MCA handling |
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* |
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* Mods by cfleck to integrate into kernel build |
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* |
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* 2000-03-15 David Mosberger-Tang <davidm@hpl.hp.com> |
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* Added various stop bits to get a clean compile |
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* |
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* 2000-03-29 Chuck Fleckenstein <cfleck@co.intel.com> |
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* Added code to save INIT handoff state in pt_regs format, |
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* switch to temp kstack, switch modes, jump to C INIT handler |
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* |
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* 2002-01-04 J.Hall <jenna.s.hall@intel.com> |
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* Before entering virtual mode code: |
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* 1. Check for TLB CPU error |
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* 2. Restore current thread pointer to kr6 |
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* 3. Move stack ptr 16 bytes to conform to C calling convention |
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* |
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* 2004-11-12 Russ Anderson <rja@sgi.com> |
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* Added per cpu MCA/INIT stack save areas. |
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* |
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* 2005-12-08 Keith Owens <kaos@sgi.com> |
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* Use per cpu MCA/INIT stacks for all data. |
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*/ |
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#include <linux/threads.h> |
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#include <linux/pgtable.h> |
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#include <asm/asmmacro.h> |
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#include <asm/processor.h> |
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#include <asm/mca_asm.h> |
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#include <asm/mca.h> |
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#include "entry.h" |
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#define GET_IA64_MCA_DATA(reg) \ |
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GET_THIS_PADDR(reg, ia64_mca_data) \ |
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;; \ |
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ld8 reg=[reg] |
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.global ia64_do_tlb_purge |
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.global ia64_os_mca_dispatch |
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.global ia64_os_init_on_kdump |
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.global ia64_os_init_dispatch_monarch |
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.global ia64_os_init_dispatch_slave |
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.text |
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.align 16 |
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//StartMain//////////////////////////////////////////////////////////////////// |
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/* |
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* Just the TLB purge part is moved to a separate function |
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* so we can re-use the code for cpu hotplug code as well |
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* Caller should now setup b1, so we can branch once the |
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* tlb flush is complete. |
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*/ |
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ia64_do_tlb_purge: |
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#define O(member) IA64_CPUINFO_##member##_OFFSET |
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GET_THIS_PADDR(r2, ia64_cpu_info) // load phys addr of cpu_info into r2 |
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;; |
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addl r17=O(PTCE_STRIDE),r2 |
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addl r2=O(PTCE_BASE),r2 |
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;; |
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ld8 r18=[r2],(O(PTCE_COUNT)-O(PTCE_BASE));; // r18=ptce_base |
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ld4 r19=[r2],4 // r19=ptce_count[0] |
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ld4 r21=[r17],4 // r21=ptce_stride[0] |
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;; |
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ld4 r20=[r2] // r20=ptce_count[1] |
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ld4 r22=[r17] // r22=ptce_stride[1] |
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mov r24=0 |
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;; |
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adds r20=-1,r20 |
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;; |
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#undef O |
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2: |
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cmp.ltu p6,p7=r24,r19 |
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(p7) br.cond.dpnt.few 4f |
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mov ar.lc=r20 |
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3: |
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ptc.e r18 |
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;; |
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add r18=r22,r18 |
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br.cloop.sptk.few 3b |
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;; |
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add r18=r21,r18 |
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add r24=1,r24 |
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;; |
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br.sptk.few 2b |
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4: |
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srlz.i // srlz.i implies srlz.d |
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;; |
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// Now purge addresses formerly mapped by TR registers |
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// 1. Purge ITR&DTR for kernel. |
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movl r16=KERNEL_START |
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mov r18=KERNEL_TR_PAGE_SHIFT<<2 |
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;; |
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ptr.i r16, r18 |
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ptr.d r16, r18 |
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;; |
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srlz.i |
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;; |
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srlz.d |
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;; |
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// 3. Purge ITR for PAL code. |
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GET_THIS_PADDR(r2, ia64_mca_pal_base) |
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;; |
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ld8 r16=[r2] |
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mov r18=IA64_GRANULE_SHIFT<<2 |
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;; |
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ptr.i r16,r18 |
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;; |
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srlz.i |
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;; |
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// 4. Purge DTR for stack. |
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mov r16=IA64_KR(CURRENT_STACK) |
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;; |
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shl r16=r16,IA64_GRANULE_SHIFT |
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movl r19=PAGE_OFFSET |
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;; |
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add r16=r19,r16 |
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mov r18=IA64_GRANULE_SHIFT<<2 |
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;; |
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ptr.d r16,r18 |
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;; |
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srlz.i |
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;; |
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// Now branch away to caller. |
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br.sptk.many b1 |
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;; |
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//EndMain////////////////////////////////////////////////////////////////////// |
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//StartMain//////////////////////////////////////////////////////////////////// |
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ia64_os_mca_dispatch: |
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mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack |
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LOAD_PHYSICAL(p0,r2,1f) // return address |
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mov r19=1 // All MCA events are treated as monarch (for now) |
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br.sptk ia64_state_save // save the state that is not in minstate |
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1: |
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GET_IA64_MCA_DATA(r2) |
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// Using MCA stack, struct ia64_sal_os_state, variable proc_state_param |
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;; |
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add r3=IA64_MCA_CPU_MCA_STACK_OFFSET+MCA_SOS_OFFSET+SOS(PROC_STATE_PARAM), r2 |
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;; |
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ld8 r18=[r3] // Get processor state parameter on existing PALE_CHECK. |
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;; |
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tbit.nz p6,p7=r18,60 |
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(p7) br.spnt done_tlb_purge_and_reload |
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|
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// The following code purges TC and TR entries. Then reload all TC entries. |
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// Purge percpu data TC entries. |
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begin_tlb_purge_and_reload: |
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movl r18=ia64_reload_tr;; |
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LOAD_PHYSICAL(p0,r18,ia64_reload_tr);; |
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mov b1=r18;; |
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br.sptk.many ia64_do_tlb_purge;; |
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ia64_reload_tr: |
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// Finally reload the TR registers. |
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// 1. Reload DTR/ITR registers for kernel. |
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mov r18=KERNEL_TR_PAGE_SHIFT<<2 |
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movl r17=KERNEL_START |
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;; |
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mov cr.itir=r18 |
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mov cr.ifa=r17 |
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mov r16=IA64_TR_KERNEL |
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mov r19=ip |
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movl r18=PAGE_KERNEL |
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;; |
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dep r17=0,r19,0, KERNEL_TR_PAGE_SHIFT |
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;; |
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or r18=r17,r18 |
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;; |
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itr.i itr[r16]=r18 |
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;; |
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itr.d dtr[r16]=r18 |
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;; |
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srlz.i |
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srlz.d |
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;; |
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// 3. Reload ITR for PAL code. |
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GET_THIS_PADDR(r2, ia64_mca_pal_pte) |
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;; |
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ld8 r18=[r2] // load PAL PTE |
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;; |
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GET_THIS_PADDR(r2, ia64_mca_pal_base) |
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;; |
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ld8 r16=[r2] // load PAL vaddr |
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mov r19=IA64_GRANULE_SHIFT<<2 |
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;; |
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mov cr.itir=r19 |
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mov cr.ifa=r16 |
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mov r20=IA64_TR_PALCODE |
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;; |
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itr.i itr[r20]=r18 |
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;; |
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srlz.i |
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;; |
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// 4. Reload DTR for stack. |
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mov r16=IA64_KR(CURRENT_STACK) |
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;; |
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shl r16=r16,IA64_GRANULE_SHIFT |
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movl r19=PAGE_OFFSET |
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;; |
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add r18=r19,r16 |
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movl r20=PAGE_KERNEL |
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;; |
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add r16=r20,r16 |
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mov r19=IA64_GRANULE_SHIFT<<2 |
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;; |
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mov cr.itir=r19 |
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mov cr.ifa=r18 |
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mov r20=IA64_TR_CURRENT_STACK |
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;; |
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itr.d dtr[r20]=r16 |
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GET_THIS_PADDR(r2, ia64_mca_tr_reload) |
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mov r18 = 1 |
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;; |
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srlz.d |
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;; |
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st8 [r2] =r18 |
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;; |
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done_tlb_purge_and_reload: |
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// switch to per cpu MCA stack |
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mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack |
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LOAD_PHYSICAL(p0,r2,1f) // return address |
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br.sptk ia64_new_stack |
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1: |
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// everything saved, now we can set the kernel registers |
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mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack |
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LOAD_PHYSICAL(p0,r2,1f) // return address |
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br.sptk ia64_set_kernel_registers |
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1: |
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// This must be done in physical mode |
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GET_IA64_MCA_DATA(r2) |
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;; |
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mov r7=r2 |
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// Enter virtual mode from physical mode |
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VIRTUAL_MODE_ENTER(r2, r3, ia64_os_mca_virtual_begin, r4) |
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// This code returns to SAL via SOS r2, in general SAL has no unwind |
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// data. To get a clean termination when backtracing the C MCA/INIT |
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// handler, set a dummy return address of 0 in this routine. That |
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// requires that ia64_os_mca_virtual_begin be a global function. |
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ENTRY(ia64_os_mca_virtual_begin) |
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.prologue |
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.save rp,r0 |
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.body |
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mov ar.rsc=3 // set eager mode for C handler |
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mov r2=r7 // see GET_IA64_MCA_DATA above |
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;; |
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// Call virtual mode handler |
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alloc r14=ar.pfs,0,0,3,0 |
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;; |
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DATA_PA_TO_VA(r2,r7) |
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;; |
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add out0=IA64_MCA_CPU_MCA_STACK_OFFSET+MCA_PT_REGS_OFFSET, r2 |
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add out1=IA64_MCA_CPU_MCA_STACK_OFFSET+MCA_SWITCH_STACK_OFFSET, r2 |
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add out2=IA64_MCA_CPU_MCA_STACK_OFFSET+MCA_SOS_OFFSET, r2 |
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br.call.sptk.many b0=ia64_mca_handler |
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// Revert back to physical mode before going back to SAL |
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PHYSICAL_MODE_ENTER(r2, r3, ia64_os_mca_virtual_end, r4) |
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ia64_os_mca_virtual_end: |
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END(ia64_os_mca_virtual_begin) |
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// switch back to previous stack |
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alloc r14=ar.pfs,0,0,0,0 // remove the MCA handler frame |
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mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack |
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LOAD_PHYSICAL(p0,r2,1f) // return address |
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br.sptk ia64_old_stack |
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1: |
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mov r3=IA64_MCA_CPU_MCA_STACK_OFFSET // use the MCA stack |
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LOAD_PHYSICAL(p0,r2,1f) // return address |
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br.sptk ia64_state_restore // restore the SAL state |
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1: |
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mov b0=r12 // SAL_CHECK return address |
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br b0 |
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//EndMain////////////////////////////////////////////////////////////////////// |
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//StartMain//////////////////////////////////////////////////////////////////// |
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// |
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// NOP init handler for kdump. In panic situation, we may receive INIT |
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// while kernel transition. Since we initialize registers on leave from |
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// current kernel, no longer monarch/slave handlers of current kernel in |
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// virtual mode are called safely. |
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// We can unregister these init handlers from SAL, however then the INIT |
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// will result in warmboot by SAL and we cannot retrieve the crashdump. |
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// Therefore register this NOP function to SAL, to prevent entering virtual |
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// mode and resulting warmboot by SAL. |
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// |
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ia64_os_init_on_kdump: |
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mov r8=r0 // IA64_INIT_RESUME |
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mov r9=r10 // SAL_GP |
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mov r22=r17 // *minstate |
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;; |
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mov r10=r0 // return to same context |
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mov b0=r12 // SAL_CHECK return address |
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br b0 |
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// |
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// SAL to OS entry point for INIT on all processors. This has been defined for |
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// registration purposes with SAL as a part of ia64_mca_init. Monarch and |
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// slave INIT have identical processing, except for the value of the |
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// sos->monarch flag in r19. |
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// |
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ia64_os_init_dispatch_monarch: |
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mov r19=1 // Bow, bow, ye lower middle classes! |
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br.sptk ia64_os_init_dispatch |
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ia64_os_init_dispatch_slave: |
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mov r19=0 // <igor>yeth, mathter</igor> |
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ia64_os_init_dispatch: |
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mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack |
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LOAD_PHYSICAL(p0,r2,1f) // return address |
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br.sptk ia64_state_save // save the state that is not in minstate |
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1: |
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// switch to per cpu INIT stack |
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mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack |
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LOAD_PHYSICAL(p0,r2,1f) // return address |
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br.sptk ia64_new_stack |
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1: |
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// everything saved, now we can set the kernel registers |
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mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack |
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LOAD_PHYSICAL(p0,r2,1f) // return address |
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br.sptk ia64_set_kernel_registers |
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1: |
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// This must be done in physical mode |
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GET_IA64_MCA_DATA(r2) |
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;; |
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mov r7=r2 |
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// Enter virtual mode from physical mode |
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VIRTUAL_MODE_ENTER(r2, r3, ia64_os_init_virtual_begin, r4) |
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// This code returns to SAL via SOS r2, in general SAL has no unwind |
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// data. To get a clean termination when backtracing the C MCA/INIT |
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// handler, set a dummy return address of 0 in this routine. That |
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// requires that ia64_os_init_virtual_begin be a global function. |
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ENTRY(ia64_os_init_virtual_begin) |
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.prologue |
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.save rp,r0 |
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.body |
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mov ar.rsc=3 // set eager mode for C handler |
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mov r2=r7 // see GET_IA64_MCA_DATA above |
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;; |
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// Call virtual mode handler |
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alloc r14=ar.pfs,0,0,3,0 |
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;; |
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DATA_PA_TO_VA(r2,r7) |
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;; |
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add out0=IA64_MCA_CPU_INIT_STACK_OFFSET+MCA_PT_REGS_OFFSET, r2 |
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add out1=IA64_MCA_CPU_INIT_STACK_OFFSET+MCA_SWITCH_STACK_OFFSET, r2 |
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add out2=IA64_MCA_CPU_INIT_STACK_OFFSET+MCA_SOS_OFFSET, r2 |
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br.call.sptk.many b0=ia64_init_handler |
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// Revert back to physical mode before going back to SAL |
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PHYSICAL_MODE_ENTER(r2, r3, ia64_os_init_virtual_end, r4) |
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ia64_os_init_virtual_end: |
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END(ia64_os_init_virtual_begin) |
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mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack |
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LOAD_PHYSICAL(p0,r2,1f) // return address |
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br.sptk ia64_state_restore // restore the SAL state |
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1: |
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// switch back to previous stack |
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alloc r14=ar.pfs,0,0,0,0 // remove the INIT handler frame |
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mov r3=IA64_MCA_CPU_INIT_STACK_OFFSET // use the INIT stack |
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LOAD_PHYSICAL(p0,r2,1f) // return address |
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br.sptk ia64_old_stack |
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1: |
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mov b0=r12 // SAL_CHECK return address |
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br b0 |
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//EndMain////////////////////////////////////////////////////////////////////// |
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// common defines for the stubs |
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#define ms r4 |
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#define regs r5 |
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#define temp1 r2 /* careful, it overlaps with input registers */ |
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#define temp2 r3 /* careful, it overlaps with input registers */ |
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#define temp3 r7 |
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#define temp4 r14 |
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//++ |
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// Name: |
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// ia64_state_save() |
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// |
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// Stub Description: |
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// |
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// Save the state that is not in minstate. This is sensitive to the layout of |
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// struct ia64_sal_os_state in mca.h. |
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// |
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// r2 contains the return address, r3 contains either |
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// IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET. |
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// |
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// The OS to SAL section of struct ia64_sal_os_state is set to a default |
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// value of cold boot (MCA) or warm boot (INIT) and return to the same |
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// context. ia64_sal_os_state is also used to hold some registers that |
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// need to be saved and restored across the stack switches. |
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// |
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// Most input registers to this stub come from PAL/SAL |
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// r1 os gp, physical |
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// r8 pal_proc entry point |
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// r9 sal_proc entry point |
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// r10 sal gp |
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// r11 MCA - rendevzous state, INIT - reason code |
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// r12 sal return address |
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// r17 pal min_state |
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// r18 processor state parameter |
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// r19 monarch flag, set by the caller of this routine |
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// |
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// In addition to the SAL to OS state, this routine saves all the |
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// registers that appear in struct pt_regs and struct switch_stack, |
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// excluding those that are already in the PAL minstate area. This |
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// results in a partial pt_regs and switch_stack, the C code copies the |
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// remaining registers from PAL minstate to pt_regs and switch_stack. The |
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// resulting structures contain all the state of the original process when |
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// MCA/INIT occurred. |
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// |
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//-- |
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ia64_state_save: |
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add regs=MCA_SOS_OFFSET, r3 |
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add ms=MCA_SOS_OFFSET+8, r3 |
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mov b0=r2 // save return address |
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cmp.eq p1,p2=IA64_MCA_CPU_MCA_STACK_OFFSET, r3 |
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;; |
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GET_IA64_MCA_DATA(temp2) |
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;; |
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add temp1=temp2, regs // struct ia64_sal_os_state on MCA or INIT stack |
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add temp2=temp2, ms // struct ia64_sal_os_state+8 on MCA or INIT stack |
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;; |
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mov regs=temp1 // save the start of sos |
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st8 [temp1]=r1,16 // os_gp |
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st8 [temp2]=r8,16 // pal_proc |
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;; |
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st8 [temp1]=r9,16 // sal_proc |
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st8 [temp2]=r11,16 // rv_rc |
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mov r11=cr.iipa |
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;; |
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st8 [temp1]=r18 // proc_state_param |
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st8 [temp2]=r19 // monarch |
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mov r6=IA64_KR(CURRENT) |
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add temp1=SOS(SAL_RA), regs |
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add temp2=SOS(SAL_GP), regs |
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;; |
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st8 [temp1]=r12,16 // sal_ra |
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st8 [temp2]=r10,16 // sal_gp |
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mov r12=cr.isr |
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;; |
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st8 [temp1]=r17,16 // pal_min_state |
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st8 [temp2]=r6,16 // prev_IA64_KR_CURRENT |
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mov r6=IA64_KR(CURRENT_STACK) |
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;; |
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st8 [temp1]=r6,16 // prev_IA64_KR_CURRENT_STACK |
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st8 [temp2]=r0,16 // prev_task, starts off as NULL |
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mov r6=cr.ifa |
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;; |
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st8 [temp1]=r12,16 // cr.isr |
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st8 [temp2]=r6,16 // cr.ifa |
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mov r12=cr.itir |
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;; |
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st8 [temp1]=r12,16 // cr.itir |
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st8 [temp2]=r11,16 // cr.iipa |
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mov r12=cr.iim |
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;; |
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st8 [temp1]=r12 // cr.iim |
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(p1) mov r12=IA64_MCA_COLD_BOOT |
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(p2) mov r12=IA64_INIT_WARM_BOOT |
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mov r6=cr.iha |
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add temp1=SOS(OS_STATUS), regs |
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;; |
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st8 [temp2]=r6 // cr.iha |
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add temp2=SOS(CONTEXT), regs |
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st8 [temp1]=r12 // os_status, default is cold boot |
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mov r6=IA64_MCA_SAME_CONTEXT |
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;; |
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st8 [temp2]=r6 // context, default is same context |
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|
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// Save the pt_regs data that is not in minstate. The previous code |
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// left regs at sos. |
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add regs=MCA_PT_REGS_OFFSET-MCA_SOS_OFFSET, regs |
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;; |
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add temp1=PT(B6), regs |
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mov temp3=b6 |
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mov temp4=b7 |
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add temp2=PT(B7), regs |
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;; |
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st8 [temp1]=temp3,PT(AR_CSD)-PT(B6) // save b6 |
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st8 [temp2]=temp4,PT(AR_SSD)-PT(B7) // save b7 |
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mov temp3=ar.csd |
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mov temp4=ar.ssd |
|
cover // must be last in group |
|
;; |
|
st8 [temp1]=temp3,PT(AR_UNAT)-PT(AR_CSD) // save ar.csd |
|
st8 [temp2]=temp4,PT(AR_PFS)-PT(AR_SSD) // save ar.ssd |
|
mov temp3=ar.unat |
|
mov temp4=ar.pfs |
|
;; |
|
st8 [temp1]=temp3,PT(AR_RNAT)-PT(AR_UNAT) // save ar.unat |
|
st8 [temp2]=temp4,PT(AR_BSPSTORE)-PT(AR_PFS) // save ar.pfs |
|
mov temp3=ar.rnat |
|
mov temp4=ar.bspstore |
|
;; |
|
st8 [temp1]=temp3,PT(LOADRS)-PT(AR_RNAT) // save ar.rnat |
|
st8 [temp2]=temp4,PT(AR_FPSR)-PT(AR_BSPSTORE) // save ar.bspstore |
|
mov temp3=ar.bsp |
|
;; |
|
sub temp3=temp3, temp4 // ar.bsp - ar.bspstore |
|
mov temp4=ar.fpsr |
|
;; |
|
shl temp3=temp3,16 // compute ar.rsc to be used for "loadrs" |
|
;; |
|
st8 [temp1]=temp3,PT(AR_CCV)-PT(LOADRS) // save loadrs |
|
st8 [temp2]=temp4,PT(F6)-PT(AR_FPSR) // save ar.fpsr |
|
mov temp3=ar.ccv |
|
;; |
|
st8 [temp1]=temp3,PT(F7)-PT(AR_CCV) // save ar.ccv |
|
stf.spill [temp2]=f6,PT(F8)-PT(F6) |
|
;; |
|
stf.spill [temp1]=f7,PT(F9)-PT(F7) |
|
stf.spill [temp2]=f8,PT(F10)-PT(F8) |
|
;; |
|
stf.spill [temp1]=f9,PT(F11)-PT(F9) |
|
stf.spill [temp2]=f10 |
|
;; |
|
stf.spill [temp1]=f11 |
|
|
|
// Save the switch_stack data that is not in minstate nor pt_regs. The |
|
// previous code left regs at pt_regs. |
|
add regs=MCA_SWITCH_STACK_OFFSET-MCA_PT_REGS_OFFSET, regs |
|
;; |
|
add temp1=SW(F2), regs |
|
add temp2=SW(F3), regs |
|
;; |
|
stf.spill [temp1]=f2,32 |
|
stf.spill [temp2]=f3,32 |
|
;; |
|
stf.spill [temp1]=f4,32 |
|
stf.spill [temp2]=f5,32 |
|
;; |
|
stf.spill [temp1]=f12,32 |
|
stf.spill [temp2]=f13,32 |
|
;; |
|
stf.spill [temp1]=f14,32 |
|
stf.spill [temp2]=f15,32 |
|
;; |
|
stf.spill [temp1]=f16,32 |
|
stf.spill [temp2]=f17,32 |
|
;; |
|
stf.spill [temp1]=f18,32 |
|
stf.spill [temp2]=f19,32 |
|
;; |
|
stf.spill [temp1]=f20,32 |
|
stf.spill [temp2]=f21,32 |
|
;; |
|
stf.spill [temp1]=f22,32 |
|
stf.spill [temp2]=f23,32 |
|
;; |
|
stf.spill [temp1]=f24,32 |
|
stf.spill [temp2]=f25,32 |
|
;; |
|
stf.spill [temp1]=f26,32 |
|
stf.spill [temp2]=f27,32 |
|
;; |
|
stf.spill [temp1]=f28,32 |
|
stf.spill [temp2]=f29,32 |
|
;; |
|
stf.spill [temp1]=f30,SW(B2)-SW(F30) |
|
stf.spill [temp2]=f31,SW(B3)-SW(F31) |
|
mov temp3=b2 |
|
mov temp4=b3 |
|
;; |
|
st8 [temp1]=temp3,16 // save b2 |
|
st8 [temp2]=temp4,16 // save b3 |
|
mov temp3=b4 |
|
mov temp4=b5 |
|
;; |
|
st8 [temp1]=temp3,SW(AR_LC)-SW(B4) // save b4 |
|
st8 [temp2]=temp4 // save b5 |
|
mov temp3=ar.lc |
|
;; |
|
st8 [temp1]=temp3 // save ar.lc |
|
|
|
// FIXME: Some proms are incorrectly accessing the minstate area as |
|
// cached data. The C code uses region 6, uncached virtual. Ensure |
|
// that there is no cache data lying around for the first 1K of the |
|
// minstate area. |
|
// Remove this code in September 2006, that gives platforms a year to |
|
// fix their proms and get their customers updated. |
|
|
|
add r1=32*1,r17 |
|
add r2=32*2,r17 |
|
add r3=32*3,r17 |
|
add r4=32*4,r17 |
|
add r5=32*5,r17 |
|
add r6=32*6,r17 |
|
add r7=32*7,r17 |
|
;; |
|
fc r17 |
|
fc r1 |
|
fc r2 |
|
fc r3 |
|
fc r4 |
|
fc r5 |
|
fc r6 |
|
fc r7 |
|
add r17=32*8,r17 |
|
add r1=32*8,r1 |
|
add r2=32*8,r2 |
|
add r3=32*8,r3 |
|
add r4=32*8,r4 |
|
add r5=32*8,r5 |
|
add r6=32*8,r6 |
|
add r7=32*8,r7 |
|
;; |
|
fc r17 |
|
fc r1 |
|
fc r2 |
|
fc r3 |
|
fc r4 |
|
fc r5 |
|
fc r6 |
|
fc r7 |
|
add r17=32*8,r17 |
|
add r1=32*8,r1 |
|
add r2=32*8,r2 |
|
add r3=32*8,r3 |
|
add r4=32*8,r4 |
|
add r5=32*8,r5 |
|
add r6=32*8,r6 |
|
add r7=32*8,r7 |
|
;; |
|
fc r17 |
|
fc r1 |
|
fc r2 |
|
fc r3 |
|
fc r4 |
|
fc r5 |
|
fc r6 |
|
fc r7 |
|
add r17=32*8,r17 |
|
add r1=32*8,r1 |
|
add r2=32*8,r2 |
|
add r3=32*8,r3 |
|
add r4=32*8,r4 |
|
add r5=32*8,r5 |
|
add r6=32*8,r6 |
|
add r7=32*8,r7 |
|
;; |
|
fc r17 |
|
fc r1 |
|
fc r2 |
|
fc r3 |
|
fc r4 |
|
fc r5 |
|
fc r6 |
|
fc r7 |
|
|
|
br.sptk b0 |
|
|
|
//EndStub////////////////////////////////////////////////////////////////////// |
|
|
|
|
|
//++ |
|
// Name: |
|
// ia64_state_restore() |
|
// |
|
// Stub Description: |
|
// |
|
// Restore the SAL/OS state. This is sensitive to the layout of struct |
|
// ia64_sal_os_state in mca.h. |
|
// |
|
// r2 contains the return address, r3 contains either |
|
// IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET. |
|
// |
|
// In addition to the SAL to OS state, this routine restores all the |
|
// registers that appear in struct pt_regs and struct switch_stack, |
|
// excluding those in the PAL minstate area. |
|
// |
|
//-- |
|
|
|
ia64_state_restore: |
|
// Restore the switch_stack data that is not in minstate nor pt_regs. |
|
add regs=MCA_SWITCH_STACK_OFFSET, r3 |
|
mov b0=r2 // save return address |
|
;; |
|
GET_IA64_MCA_DATA(temp2) |
|
;; |
|
add regs=temp2, regs |
|
;; |
|
add temp1=SW(F2), regs |
|
add temp2=SW(F3), regs |
|
;; |
|
ldf.fill f2=[temp1],32 |
|
ldf.fill f3=[temp2],32 |
|
;; |
|
ldf.fill f4=[temp1],32 |
|
ldf.fill f5=[temp2],32 |
|
;; |
|
ldf.fill f12=[temp1],32 |
|
ldf.fill f13=[temp2],32 |
|
;; |
|
ldf.fill f14=[temp1],32 |
|
ldf.fill f15=[temp2],32 |
|
;; |
|
ldf.fill f16=[temp1],32 |
|
ldf.fill f17=[temp2],32 |
|
;; |
|
ldf.fill f18=[temp1],32 |
|
ldf.fill f19=[temp2],32 |
|
;; |
|
ldf.fill f20=[temp1],32 |
|
ldf.fill f21=[temp2],32 |
|
;; |
|
ldf.fill f22=[temp1],32 |
|
ldf.fill f23=[temp2],32 |
|
;; |
|
ldf.fill f24=[temp1],32 |
|
ldf.fill f25=[temp2],32 |
|
;; |
|
ldf.fill f26=[temp1],32 |
|
ldf.fill f27=[temp2],32 |
|
;; |
|
ldf.fill f28=[temp1],32 |
|
ldf.fill f29=[temp2],32 |
|
;; |
|
ldf.fill f30=[temp1],SW(B2)-SW(F30) |
|
ldf.fill f31=[temp2],SW(B3)-SW(F31) |
|
;; |
|
ld8 temp3=[temp1],16 // restore b2 |
|
ld8 temp4=[temp2],16 // restore b3 |
|
;; |
|
mov b2=temp3 |
|
mov b3=temp4 |
|
ld8 temp3=[temp1],SW(AR_LC)-SW(B4) // restore b4 |
|
ld8 temp4=[temp2] // restore b5 |
|
;; |
|
mov b4=temp3 |
|
mov b5=temp4 |
|
ld8 temp3=[temp1] // restore ar.lc |
|
;; |
|
mov ar.lc=temp3 |
|
|
|
// Restore the pt_regs data that is not in minstate. The previous code |
|
// left regs at switch_stack. |
|
add regs=MCA_PT_REGS_OFFSET-MCA_SWITCH_STACK_OFFSET, regs |
|
;; |
|
add temp1=PT(B6), regs |
|
add temp2=PT(B7), regs |
|
;; |
|
ld8 temp3=[temp1],PT(AR_CSD)-PT(B6) // restore b6 |
|
ld8 temp4=[temp2],PT(AR_SSD)-PT(B7) // restore b7 |
|
;; |
|
mov b6=temp3 |
|
mov b7=temp4 |
|
ld8 temp3=[temp1],PT(AR_UNAT)-PT(AR_CSD) // restore ar.csd |
|
ld8 temp4=[temp2],PT(AR_PFS)-PT(AR_SSD) // restore ar.ssd |
|
;; |
|
mov ar.csd=temp3 |
|
mov ar.ssd=temp4 |
|
ld8 temp3=[temp1] // restore ar.unat |
|
add temp1=PT(AR_CCV)-PT(AR_UNAT), temp1 |
|
ld8 temp4=[temp2],PT(AR_FPSR)-PT(AR_PFS) // restore ar.pfs |
|
;; |
|
mov ar.unat=temp3 |
|
mov ar.pfs=temp4 |
|
// ar.rnat, ar.bspstore, loadrs are restore in ia64_old_stack. |
|
ld8 temp3=[temp1],PT(F6)-PT(AR_CCV) // restore ar.ccv |
|
ld8 temp4=[temp2],PT(F7)-PT(AR_FPSR) // restore ar.fpsr |
|
;; |
|
mov ar.ccv=temp3 |
|
mov ar.fpsr=temp4 |
|
ldf.fill f6=[temp1],PT(F8)-PT(F6) |
|
ldf.fill f7=[temp2],PT(F9)-PT(F7) |
|
;; |
|
ldf.fill f8=[temp1],PT(F10)-PT(F8) |
|
ldf.fill f9=[temp2],PT(F11)-PT(F9) |
|
;; |
|
ldf.fill f10=[temp1] |
|
ldf.fill f11=[temp2] |
|
|
|
// Restore the SAL to OS state. The previous code left regs at pt_regs. |
|
add regs=MCA_SOS_OFFSET-MCA_PT_REGS_OFFSET, regs |
|
;; |
|
add temp1=SOS(SAL_RA), regs |
|
add temp2=SOS(SAL_GP), regs |
|
;; |
|
ld8 r12=[temp1],16 // sal_ra |
|
ld8 r9=[temp2],16 // sal_gp |
|
;; |
|
ld8 r22=[temp1],16 // pal_min_state, virtual |
|
ld8 r13=[temp2],16 // prev_IA64_KR_CURRENT |
|
;; |
|
ld8 r16=[temp1],16 // prev_IA64_KR_CURRENT_STACK |
|
ld8 r20=[temp2],16 // prev_task |
|
;; |
|
ld8 temp3=[temp1],16 // cr.isr |
|
ld8 temp4=[temp2],16 // cr.ifa |
|
;; |
|
mov cr.isr=temp3 |
|
mov cr.ifa=temp4 |
|
ld8 temp3=[temp1],16 // cr.itir |
|
ld8 temp4=[temp2],16 // cr.iipa |
|
;; |
|
mov cr.itir=temp3 |
|
mov cr.iipa=temp4 |
|
ld8 temp3=[temp1] // cr.iim |
|
ld8 temp4=[temp2] // cr.iha |
|
add temp1=SOS(OS_STATUS), regs |
|
add temp2=SOS(CONTEXT), regs |
|
;; |
|
mov cr.iim=temp3 |
|
mov cr.iha=temp4 |
|
dep r22=0,r22,62,1 // pal_min_state, physical, uncached |
|
mov IA64_KR(CURRENT)=r13 |
|
ld8 r8=[temp1] // os_status |
|
ld8 r10=[temp2] // context |
|
|
|
/* Wire IA64_TR_CURRENT_STACK to the stack that we are resuming to. To |
|
* avoid any dependencies on the algorithm in ia64_switch_to(), just |
|
* purge any existing CURRENT_STACK mapping and insert the new one. |
|
* |
|
* r16 contains prev_IA64_KR_CURRENT_STACK, r13 contains |
|
* prev_IA64_KR_CURRENT, these values may have been changed by the C |
|
* code. Do not use r8, r9, r10, r22, they contain values ready for |
|
* the return to SAL. |
|
*/ |
|
|
|
mov r15=IA64_KR(CURRENT_STACK) // physical granule mapped by IA64_TR_CURRENT_STACK |
|
;; |
|
shl r15=r15,IA64_GRANULE_SHIFT |
|
;; |
|
dep r15=-1,r15,61,3 // virtual granule |
|
mov r18=IA64_GRANULE_SHIFT<<2 // for cr.itir.ps |
|
;; |
|
ptr.d r15,r18 |
|
;; |
|
srlz.d |
|
|
|
extr.u r19=r13,61,3 // r13 = prev_IA64_KR_CURRENT |
|
shl r20=r16,IA64_GRANULE_SHIFT // r16 = prev_IA64_KR_CURRENT_STACK |
|
movl r21=PAGE_KERNEL // page properties |
|
;; |
|
mov IA64_KR(CURRENT_STACK)=r16 |
|
cmp.ne p6,p0=RGN_KERNEL,r19 // new stack is in the kernel region? |
|
or r21=r20,r21 // construct PA | page properties |
|
(p6) br.spnt 1f // the dreaded cpu 0 idle task in region 5:( |
|
;; |
|
mov cr.itir=r18 |
|
mov cr.ifa=r13 |
|
mov r20=IA64_TR_CURRENT_STACK |
|
;; |
|
itr.d dtr[r20]=r21 |
|
;; |
|
srlz.d |
|
1: |
|
|
|
br.sptk b0 |
|
|
|
//EndStub////////////////////////////////////////////////////////////////////// |
|
|
|
|
|
//++ |
|
// Name: |
|
// ia64_new_stack() |
|
// |
|
// Stub Description: |
|
// |
|
// Switch to the MCA/INIT stack. |
|
// |
|
// r2 contains the return address, r3 contains either |
|
// IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET. |
|
// |
|
// On entry RBS is still on the original stack, this routine switches RBS |
|
// to use the MCA/INIT stack. |
|
// |
|
// On entry, sos->pal_min_state is physical, on exit it is virtual. |
|
// |
|
//-- |
|
|
|
ia64_new_stack: |
|
add regs=MCA_PT_REGS_OFFSET, r3 |
|
add temp2=MCA_SOS_OFFSET+SOS(PAL_MIN_STATE), r3 |
|
mov b0=r2 // save return address |
|
GET_IA64_MCA_DATA(temp1) |
|
invala |
|
;; |
|
add temp2=temp2, temp1 // struct ia64_sal_os_state.pal_min_state on MCA or INIT stack |
|
add regs=regs, temp1 // struct pt_regs on MCA or INIT stack |
|
;; |
|
// Address of minstate area provided by PAL is physical, uncacheable. |
|
// Convert to Linux virtual address in region 6 for C code. |
|
ld8 ms=[temp2] // pal_min_state, physical |
|
;; |
|
dep temp1=-1,ms,62,2 // set region 6 |
|
mov temp3=IA64_RBS_OFFSET-MCA_PT_REGS_OFFSET |
|
;; |
|
st8 [temp2]=temp1 // pal_min_state, virtual |
|
|
|
add temp4=temp3, regs // start of bspstore on new stack |
|
;; |
|
mov ar.bspstore=temp4 // switch RBS to MCA/INIT stack |
|
;; |
|
flushrs // must be first in group |
|
br.sptk b0 |
|
|
|
//EndStub////////////////////////////////////////////////////////////////////// |
|
|
|
|
|
//++ |
|
// Name: |
|
// ia64_old_stack() |
|
// |
|
// Stub Description: |
|
// |
|
// Switch to the old stack. |
|
// |
|
// r2 contains the return address, r3 contains either |
|
// IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET. |
|
// |
|
// On entry, pal_min_state is virtual, on exit it is physical. |
|
// |
|
// On entry RBS is on the MCA/INIT stack, this routine switches RBS |
|
// back to the previous stack. |
|
// |
|
// The psr is set to all zeroes. SAL return requires either all zeroes or |
|
// just psr.mc set. Leaving psr.mc off allows INIT to be issued if this |
|
// code does not perform correctly. |
|
// |
|
// The dirty registers at the time of the event were flushed to the |
|
// MCA/INIT stack in ia64_pt_regs_save(). Restore the dirty registers |
|
// before reverting to the previous bspstore. |
|
//-- |
|
|
|
ia64_old_stack: |
|
add regs=MCA_PT_REGS_OFFSET, r3 |
|
mov b0=r2 // save return address |
|
GET_IA64_MCA_DATA(temp2) |
|
LOAD_PHYSICAL(p0,temp1,1f) |
|
;; |
|
mov cr.ipsr=r0 |
|
mov cr.ifs=r0 |
|
mov cr.iip=temp1 |
|
;; |
|
invala |
|
rfi |
|
1: |
|
|
|
add regs=regs, temp2 // struct pt_regs on MCA or INIT stack |
|
;; |
|
add temp1=PT(LOADRS), regs |
|
;; |
|
ld8 temp2=[temp1],PT(AR_BSPSTORE)-PT(LOADRS) // restore loadrs |
|
;; |
|
ld8 temp3=[temp1],PT(AR_RNAT)-PT(AR_BSPSTORE) // restore ar.bspstore |
|
mov ar.rsc=temp2 |
|
;; |
|
loadrs |
|
ld8 temp4=[temp1] // restore ar.rnat |
|
;; |
|
mov ar.bspstore=temp3 // back to old stack |
|
;; |
|
mov ar.rnat=temp4 |
|
;; |
|
|
|
br.sptk b0 |
|
|
|
//EndStub////////////////////////////////////////////////////////////////////// |
|
|
|
|
|
//++ |
|
// Name: |
|
// ia64_set_kernel_registers() |
|
// |
|
// Stub Description: |
|
// |
|
// Set the registers that are required by the C code in order to run on an |
|
// MCA/INIT stack. |
|
// |
|
// r2 contains the return address, r3 contains either |
|
// IA64_MCA_CPU_MCA_STACK_OFFSET or IA64_MCA_CPU_INIT_STACK_OFFSET. |
|
// |
|
//-- |
|
|
|
ia64_set_kernel_registers: |
|
add temp3=MCA_SP_OFFSET, r3 |
|
mov b0=r2 // save return address |
|
GET_IA64_MCA_DATA(temp1) |
|
;; |
|
add r12=temp1, temp3 // kernel stack pointer on MCA/INIT stack |
|
add r13=temp1, r3 // set current to start of MCA/INIT stack |
|
add r20=temp1, r3 // physical start of MCA/INIT stack |
|
;; |
|
DATA_PA_TO_VA(r12,temp2) |
|
DATA_PA_TO_VA(r13,temp3) |
|
;; |
|
mov IA64_KR(CURRENT)=r13 |
|
|
|
/* Wire IA64_TR_CURRENT_STACK to the MCA/INIT handler stack. To avoid |
|
* any dependencies on the algorithm in ia64_switch_to(), just purge |
|
* any existing CURRENT_STACK mapping and insert the new one. |
|
*/ |
|
|
|
mov r16=IA64_KR(CURRENT_STACK) // physical granule mapped by IA64_TR_CURRENT_STACK |
|
;; |
|
shl r16=r16,IA64_GRANULE_SHIFT |
|
;; |
|
dep r16=-1,r16,61,3 // virtual granule |
|
mov r18=IA64_GRANULE_SHIFT<<2 // for cr.itir.ps |
|
;; |
|
ptr.d r16,r18 |
|
;; |
|
srlz.d |
|
|
|
shr.u r16=r20,IA64_GRANULE_SHIFT // r20 = physical start of MCA/INIT stack |
|
movl r21=PAGE_KERNEL // page properties |
|
;; |
|
mov IA64_KR(CURRENT_STACK)=r16 |
|
or r21=r20,r21 // construct PA | page properties |
|
;; |
|
mov cr.itir=r18 |
|
mov cr.ifa=r13 |
|
mov r20=IA64_TR_CURRENT_STACK |
|
|
|
movl r17=FPSR_DEFAULT |
|
;; |
|
mov.m ar.fpsr=r17 // set ar.fpsr to kernel default value |
|
;; |
|
itr.d dtr[r20]=r21 |
|
;; |
|
srlz.d |
|
|
|
br.sptk b0 |
|
|
|
//EndStub////////////////////////////////////////////////////////////////////// |
|
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#undef ms |
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#undef regs |
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#undef temp1 |
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#undef temp2 |
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#undef temp3 |
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#undef temp4 |
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// Support function for mca.c, it is here to avoid using inline asm. Given the |
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// address of an rnat slot, if that address is below the current ar.bspstore |
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// then return the contents of that slot, otherwise return the contents of |
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// ar.rnat. |
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GLOBAL_ENTRY(ia64_get_rnat) |
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alloc r14=ar.pfs,1,0,0,0 |
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mov ar.rsc=0 |
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;; |
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mov r14=ar.bspstore |
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;; |
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cmp.lt p6,p7=in0,r14 |
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;; |
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(p6) ld8 r8=[in0] |
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(p7) mov r8=ar.rnat |
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mov ar.rsc=3 |
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br.ret.sptk.many rp |
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END(ia64_get_rnat) |
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// void ia64_set_psr_mc(void) |
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// |
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// Set psr.mc bit to mask MCA/INIT. |
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GLOBAL_ENTRY(ia64_set_psr_mc) |
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rsm psr.i | psr.ic // disable interrupts |
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;; |
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srlz.d |
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;; |
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mov r14 = psr // get psr{36:35,31:0} |
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movl r15 = 1f |
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;; |
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dep r14 = -1, r14, PSR_MC, 1 // set psr.mc |
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;; |
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dep r14 = -1, r14, PSR_IC, 1 // set psr.ic |
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;; |
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dep r14 = -1, r14, PSR_BN, 1 // keep bank1 in use |
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;; |
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mov cr.ipsr = r14 |
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mov cr.ifs = r0 |
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mov cr.iip = r15 |
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;; |
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rfi |
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1: |
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br.ret.sptk.many rp |
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END(ia64_set_psr_mc)
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