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315 lines
8.6 KiB
315 lines
8.6 KiB
/* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* SGI UV architectural definitions |
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* |
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* Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved. |
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*/ |
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#ifndef __ASM_IA64_UV_HUB_H__ |
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#define __ASM_IA64_UV_HUB_H__ |
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#include <linux/numa.h> |
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#include <linux/percpu.h> |
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#include <asm/types.h> |
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#include <asm/percpu.h> |
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/* |
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* Addressing Terminology |
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* |
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* M - The low M bits of a physical address represent the offset |
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* into the blade local memory. RAM memory on a blade is physically |
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* contiguous (although various IO spaces may punch holes in |
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* it).. |
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* |
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* N - Number of bits in the node portion of a socket physical |
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* address. |
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* |
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* NASID - network ID of a router, Mbrick or Cbrick. Nasid values of |
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* routers always have low bit of 1, C/MBricks have low bit |
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* equal to 0. Most addressing macros that target UV hub chips |
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* right shift the NASID by 1 to exclude the always-zero bit. |
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* NASIDs contain up to 15 bits. |
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* |
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* GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead |
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* of nasids. |
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* |
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* PNODE - the low N bits of the GNODE. The PNODE is the most useful variant |
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* of the nasid for socket usage. |
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* |
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* |
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* NumaLink Global Physical Address Format: |
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* +--------------------------------+---------------------+ |
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* |00..000| GNODE | NodeOffset | |
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* +--------------------------------+---------------------+ |
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* |<-------53 - M bits --->|<--------M bits -----> |
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* |
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* M - number of node offset bits (35 .. 40) |
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* |
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* |
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* Memory/UV-HUB Processor Socket Address Format: |
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* +----------------+---------------+---------------------+ |
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* |00..000000000000| PNODE | NodeOffset | |
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* +----------------+---------------+---------------------+ |
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* <--- N bits --->|<--------M bits -----> |
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* |
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* M - number of node offset bits (35 .. 40) |
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* N - number of PNODE bits (0 .. 10) |
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* |
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* Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). |
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* The actual values are configuration dependent and are set at |
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* boot time. M & N values are set by the hardware/BIOS at boot. |
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*/ |
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/* |
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* Maximum number of bricks in all partitions and in all coherency domains. |
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* This is the total number of bricks accessible in the numalink fabric. It |
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* includes all C & M bricks. Routers are NOT included. |
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* |
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* This value is also the value of the maximum number of non-router NASIDs |
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* in the numalink fabric. |
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* |
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* NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused. |
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*/ |
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#define UV_MAX_NUMALINK_BLADES 16384 |
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/* |
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* Maximum number of C/Mbricks within a software SSI (hardware may support |
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* more). |
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*/ |
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#define UV_MAX_SSI_BLADES 1 |
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/* |
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* The largest possible NASID of a C or M brick (+ 2) |
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*/ |
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#define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_NODES * 2) |
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/* |
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* The following defines attributes of the HUB chip. These attributes are |
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* frequently referenced and are kept in the per-cpu data areas of each cpu. |
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* They are kept together in a struct to minimize cache misses. |
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*/ |
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struct uv_hub_info_s { |
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unsigned long global_mmr_base; |
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unsigned long gpa_mask; |
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unsigned long gnode_upper; |
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unsigned long lowmem_remap_top; |
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unsigned long lowmem_remap_base; |
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unsigned short pnode; |
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unsigned short pnode_mask; |
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unsigned short coherency_domain_number; |
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unsigned short numa_blade_id; |
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unsigned char blade_processor_id; |
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unsigned char m_val; |
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unsigned char n_val; |
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}; |
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DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); |
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#define uv_hub_info this_cpu_ptr(&__uv_hub_info) |
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#define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu)) |
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/* |
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* Local & Global MMR space macros. |
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* Note: macros are intended to be used ONLY by inline functions |
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* in this file - not by other kernel code. |
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* n - NASID (full 15-bit global nasid) |
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* g - GNODE (full 15-bit global nasid, right shifted 1) |
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* p - PNODE (local part of nsids, right shifted 1) |
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*/ |
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#define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask) |
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#define UV_PNODE_TO_NASID(p) (((p) << 1) | uv_hub_info->gnode_upper) |
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#define UV_LOCAL_MMR_BASE 0xf4000000UL |
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#define UV_GLOBAL_MMR32_BASE 0xf8000000UL |
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#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) |
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#define UV_GLOBAL_MMR32_PNODE_SHIFT 15 |
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#define UV_GLOBAL_MMR64_PNODE_SHIFT 26 |
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#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) |
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#define UV_GLOBAL_MMR64_PNODE_BITS(p) \ |
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((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT) |
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/* |
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* Macros for converting between kernel virtual addresses, socket local physical |
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* addresses, and UV global physical addresses. |
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* Note: use the standard __pa() & __va() macros for converting |
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* between socket virtual and socket physical addresses. |
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*/ |
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/* socket phys RAM --> UV global physical address */ |
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static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) |
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{ |
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if (paddr < uv_hub_info->lowmem_remap_top) |
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paddr += uv_hub_info->lowmem_remap_base; |
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return paddr | uv_hub_info->gnode_upper; |
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} |
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/* socket virtual --> UV global physical address */ |
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static inline unsigned long uv_gpa(void *v) |
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{ |
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return __pa(v) | uv_hub_info->gnode_upper; |
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} |
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/* socket virtual --> UV global physical address */ |
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static inline void *uv_vgpa(void *v) |
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{ |
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return (void *)uv_gpa(v); |
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} |
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/* UV global physical address --> socket virtual */ |
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static inline void *uv_va(unsigned long gpa) |
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{ |
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return __va(gpa & uv_hub_info->gpa_mask); |
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} |
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/* pnode, offset --> socket virtual */ |
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static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) |
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{ |
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return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); |
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} |
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/* |
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* Access global MMRs using the low memory MMR32 space. This region supports |
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* faster MMR access but not all MMRs are accessible in this space. |
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*/ |
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static inline unsigned long *uv_global_mmr32_address(int pnode, |
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unsigned long offset) |
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{ |
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return __va(UV_GLOBAL_MMR32_BASE | |
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UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset); |
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} |
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static inline void uv_write_global_mmr32(int pnode, unsigned long offset, |
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unsigned long val) |
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{ |
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*uv_global_mmr32_address(pnode, offset) = val; |
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} |
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static inline unsigned long uv_read_global_mmr32(int pnode, |
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unsigned long offset) |
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{ |
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return *uv_global_mmr32_address(pnode, offset); |
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} |
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/* |
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* Access Global MMR space using the MMR space located at the top of physical |
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* memory. |
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*/ |
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static inline unsigned long *uv_global_mmr64_address(int pnode, |
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unsigned long offset) |
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{ |
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return __va(UV_GLOBAL_MMR64_BASE | |
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UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset); |
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} |
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static inline void uv_write_global_mmr64(int pnode, unsigned long offset, |
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unsigned long val) |
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{ |
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*uv_global_mmr64_address(pnode, offset) = val; |
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} |
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static inline unsigned long uv_read_global_mmr64(int pnode, |
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unsigned long offset) |
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{ |
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return *uv_global_mmr64_address(pnode, offset); |
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} |
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/* |
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* Access hub local MMRs. Faster than using global space but only local MMRs |
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* are accessible. |
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*/ |
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static inline unsigned long *uv_local_mmr_address(unsigned long offset) |
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{ |
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return __va(UV_LOCAL_MMR_BASE | offset); |
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} |
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static inline unsigned long uv_read_local_mmr(unsigned long offset) |
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{ |
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return *uv_local_mmr_address(offset); |
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} |
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static inline void uv_write_local_mmr(unsigned long offset, unsigned long val) |
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{ |
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*uv_local_mmr_address(offset) = val; |
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} |
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/* |
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* Structures and definitions for converting between cpu, node, pnode, and blade |
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* numbers. |
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*/ |
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/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ |
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static inline int uv_blade_processor_id(void) |
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{ |
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return smp_processor_id(); |
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} |
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/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ |
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static inline int uv_numa_blade_id(void) |
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{ |
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return 0; |
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} |
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/* Convert a cpu number to the the UV blade number */ |
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static inline int uv_cpu_to_blade_id(int cpu) |
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{ |
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return 0; |
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} |
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/* Convert linux node number to the UV blade number */ |
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static inline int uv_node_to_blade_id(int nid) |
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{ |
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return 0; |
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} |
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/* Convert a blade id to the PNODE of the blade */ |
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static inline int uv_blade_to_pnode(int bid) |
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{ |
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return 0; |
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} |
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/* Determine the number of possible cpus on a blade */ |
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static inline int uv_blade_nr_possible_cpus(int bid) |
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{ |
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return num_possible_cpus(); |
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} |
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/* Determine the number of online cpus on a blade */ |
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static inline int uv_blade_nr_online_cpus(int bid) |
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{ |
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return num_online_cpus(); |
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} |
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/* Convert a cpu id to the PNODE of the blade containing the cpu */ |
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static inline int uv_cpu_to_pnode(int cpu) |
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{ |
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return 0; |
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} |
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/* Convert a linux node number to the PNODE of the blade */ |
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static inline int uv_node_to_pnode(int nid) |
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{ |
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return 0; |
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} |
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/* Maximum possible number of blades */ |
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static inline int uv_num_possible_blades(void) |
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{ |
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return 1; |
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} |
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static inline void uv_hub_send_ipi(int pnode, int apicid, int vector) |
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{ |
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/* not currently needed on ia64 */ |
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} |
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#endif /* __ASM_IA64_UV_HUB__ */ |
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