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167 lines
5.6 KiB
167 lines
5.6 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _ASM_IA64_HW_IRQ_H |
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#define _ASM_IA64_HW_IRQ_H |
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/* |
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* Copyright (C) 2001-2003 Hewlett-Packard Co |
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* David Mosberger-Tang <[email protected]> |
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*/ |
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#include <linux/interrupt.h> |
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#include <linux/sched.h> |
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#include <linux/types.h> |
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#include <linux/profile.h> |
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#include <asm/ptrace.h> |
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#include <asm/smp.h> |
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typedef u8 ia64_vector; |
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/* |
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* 0 special |
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* |
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* 1,3-14 are reserved from firmware |
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* |
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* 16-255 (vectored external interrupts) are available |
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* |
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* 15 spurious interrupt (see IVR) |
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* |
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* 16 lowest priority, 255 highest priority |
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* |
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* 15 classes of 16 interrupts each. |
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*/ |
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#define IA64_MIN_VECTORED_IRQ 16 |
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#define IA64_MAX_VECTORED_IRQ 255 |
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#define IA64_NUM_VECTORS 256 |
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#define AUTO_ASSIGN -1 |
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#define IA64_SPURIOUS_INT_VECTOR 0x0f |
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/* |
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* Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI. |
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*/ |
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#define IA64_CPEP_VECTOR 0x1c /* corrected platform error polling vector */ |
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#define IA64_CMCP_VECTOR 0x1d /* corrected machine-check polling vector */ |
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#define IA64_CPE_VECTOR 0x1e /* corrected platform error interrupt vector */ |
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#define IA64_CMC_VECTOR 0x1f /* corrected machine-check interrupt vector */ |
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/* |
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* Vectors 0x20-0x2f are reserved for legacy ISA IRQs. |
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* Use vectors 0x30-0xe7 as the default device vector range for ia64. |
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* Platforms may choose to reduce this range in platform_irq_setup, but the |
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* platform range must fall within |
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* [IA64_DEF_FIRST_DEVICE_VECTOR..IA64_DEF_LAST_DEVICE_VECTOR] |
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*/ |
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extern int ia64_first_device_vector; |
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extern int ia64_last_device_vector; |
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#ifdef CONFIG_SMP |
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/* Reserve the lower priority vector than device vectors for "move IRQ" IPI */ |
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#define IA64_IRQ_MOVE_VECTOR 0x30 /* "move IRQ" IPI */ |
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#define IA64_DEF_FIRST_DEVICE_VECTOR 0x31 |
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#else |
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#define IA64_DEF_FIRST_DEVICE_VECTOR 0x30 |
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#endif |
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#define IA64_DEF_LAST_DEVICE_VECTOR 0xe7 |
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#define IA64_FIRST_DEVICE_VECTOR ia64_first_device_vector |
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#define IA64_LAST_DEVICE_VECTOR ia64_last_device_vector |
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#define IA64_MAX_DEVICE_VECTORS (IA64_DEF_LAST_DEVICE_VECTOR - IA64_DEF_FIRST_DEVICE_VECTOR + 1) |
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#define IA64_NUM_DEVICE_VECTORS (IA64_LAST_DEVICE_VECTOR - IA64_FIRST_DEVICE_VECTOR + 1) |
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#define IA64_MCA_RENDEZ_VECTOR 0xe8 /* MCA rendez interrupt */ |
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#define IA64_TIMER_VECTOR 0xef /* use highest-prio group 15 interrupt for timer */ |
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#define IA64_MCA_WAKEUP_VECTOR 0xf0 /* MCA wakeup (must be >MCA_RENDEZ_VECTOR) */ |
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#define IA64_IPI_LOCAL_TLB_FLUSH 0xfc /* SMP flush local TLB */ |
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#define IA64_IPI_RESCHEDULE 0xfd /* SMP reschedule */ |
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#define IA64_IPI_VECTOR 0xfe /* inter-processor interrupt vector */ |
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/* Used for encoding redirected irqs */ |
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#define IA64_IRQ_REDIRECTED (1 << 31) |
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/* IA64 inter-cpu interrupt related definitions */ |
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#define IA64_IPI_DEFAULT_BASE_ADDR 0xfee00000 |
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/* Delivery modes for inter-cpu interrupts */ |
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enum { |
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IA64_IPI_DM_INT = 0x0, /* pend an external interrupt */ |
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IA64_IPI_DM_PMI = 0x2, /* pend a PMI */ |
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IA64_IPI_DM_NMI = 0x4, /* pend an NMI (vector 2) */ |
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IA64_IPI_DM_INIT = 0x5, /* pend an INIT interrupt */ |
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IA64_IPI_DM_EXTINT = 0x7, /* pend an 8259-compatible interrupt. */ |
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}; |
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extern __u8 isa_irq_to_vector_map[16]; |
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#define isa_irq_to_vector(x) isa_irq_to_vector_map[(x)] |
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struct irq_cfg { |
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ia64_vector vector; |
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cpumask_t domain; |
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cpumask_t old_domain; |
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unsigned move_cleanup_count; |
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u8 move_in_progress : 1; |
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}; |
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extern spinlock_t vector_lock; |
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extern struct irq_cfg irq_cfg[NR_IRQS]; |
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#define irq_to_domain(x) irq_cfg[(x)].domain |
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DECLARE_PER_CPU(int[IA64_NUM_VECTORS], vector_irq); |
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extern struct irq_chip irq_type_ia64_lsapic; /* CPU-internal interrupt controller */ |
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#define ia64_register_ipi ia64_native_register_ipi |
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#define assign_irq_vector ia64_native_assign_irq_vector |
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#define free_irq_vector ia64_native_free_irq_vector |
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#define ia64_resend_irq ia64_native_resend_irq |
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extern void ia64_native_register_ipi(void); |
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extern int bind_irq_vector(int irq, int vector, cpumask_t domain); |
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extern int ia64_native_assign_irq_vector (int irq); /* allocate a free vector */ |
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extern void ia64_native_free_irq_vector (int vector); |
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extern int reserve_irq_vector (int vector); |
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extern void __setup_vector_irq(int cpu); |
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extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect); |
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extern void destroy_and_reserve_irq (unsigned int irq); |
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#ifdef CONFIG_SMP |
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extern int irq_prepare_move(int irq, int cpu); |
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extern void irq_complete_move(unsigned int irq); |
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#else |
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static inline int irq_prepare_move(int irq, int cpu) { return 0; } |
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static inline void irq_complete_move(unsigned int irq) {} |
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#endif |
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static inline void ia64_native_resend_irq(unsigned int vector) |
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{ |
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ia64_send_ipi(smp_processor_id(), vector, IA64_IPI_DM_INT, 0); |
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} |
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/* |
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* Next follows the irq descriptor interface. On IA-64, each CPU supports 256 interrupt |
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* vectors. On smaller systems, there is a one-to-one correspondence between interrupt |
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* vectors and the Linux irq numbers. However, larger systems may have multiple interrupt |
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* domains meaning that the translation from vector number to irq number depends on the |
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* interrupt domain that a CPU belongs to. This API abstracts such platform-dependent |
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* differences and provides a uniform means to translate between vector and irq numbers |
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* and to obtain the irq descriptor for a given irq number. |
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*/ |
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/* Extract the IA-64 vector that corresponds to IRQ. */ |
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static inline ia64_vector |
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irq_to_vector (int irq) |
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{ |
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return irq_cfg[irq].vector; |
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} |
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/* |
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* Convert the local IA-64 vector to the corresponding irq number. This translation is |
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* done in the context of the interrupt domain that the currently executing CPU belongs |
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* to. |
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*/ |
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static inline unsigned int |
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local_vector_to_irq (ia64_vector vec) |
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{ |
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return __this_cpu_read(vector_irq[vec]); |
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} |
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#endif /* _ASM_IA64_HW_IRQ_H */
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