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136 lines
2.8 KiB
136 lines
2.8 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd. |
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#include <linux/spinlock.h> |
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#include <asm/cache.h> |
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#include <abi/reg_ops.h> |
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/* for L1-cache */ |
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#define INS_CACHE (1 << 0) |
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#define DATA_CACHE (1 << 1) |
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#define CACHE_INV (1 << 4) |
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#define CACHE_CLR (1 << 5) |
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#define CACHE_OMS (1 << 6) |
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#define CACHE_ITS (1 << 7) |
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#define CACHE_LICF (1 << 31) |
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/* for L2-cache */ |
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#define CR22_LEVEL_SHIFT (1) |
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#define CR22_SET_SHIFT (7) |
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#define CR22_WAY_SHIFT (30) |
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#define CR22_WAY_SHIFT_L2 (29) |
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static DEFINE_SPINLOCK(cache_lock); |
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static inline void cache_op_line(unsigned long i, unsigned int val) |
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{ |
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mtcr("cr22", i); |
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mtcr("cr17", val); |
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} |
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#define CCR2_L2E (1 << 3) |
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static void cache_op_all(unsigned int value, unsigned int l2) |
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{ |
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mtcr("cr17", value | CACHE_CLR); |
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mb(); |
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if (l2 && (mfcr_ccr2() & CCR2_L2E)) { |
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mtcr("cr24", value | CACHE_CLR); |
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mb(); |
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} |
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} |
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static void cache_op_range( |
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unsigned int start, |
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unsigned int end, |
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unsigned int value, |
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unsigned int l2) |
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{ |
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unsigned long i, flags; |
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unsigned int val = value | CACHE_CLR | CACHE_OMS; |
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bool l2_sync; |
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if (unlikely((end - start) >= PAGE_SIZE) || |
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unlikely(start < PAGE_OFFSET) || |
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unlikely(start >= PAGE_OFFSET + LOWMEM_LIMIT)) { |
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cache_op_all(value, l2); |
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return; |
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} |
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if ((mfcr_ccr2() & CCR2_L2E) && l2) |
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l2_sync = 1; |
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else |
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l2_sync = 0; |
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spin_lock_irqsave(&cache_lock, flags); |
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i = start & ~(L1_CACHE_BYTES - 1); |
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for (; i < end; i += L1_CACHE_BYTES) { |
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cache_op_line(i, val); |
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if (l2_sync) { |
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mb(); |
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mtcr("cr24", val); |
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} |
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} |
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spin_unlock_irqrestore(&cache_lock, flags); |
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mb(); |
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} |
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void dcache_wb_line(unsigned long start) |
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{ |
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asm volatile("idly4\n":::"memory"); |
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cache_op_line(start, DATA_CACHE|CACHE_CLR); |
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mb(); |
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} |
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void icache_inv_range(unsigned long start, unsigned long end) |
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{ |
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cache_op_range(start, end, INS_CACHE|CACHE_INV, 0); |
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} |
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void icache_inv_all(void) |
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{ |
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cache_op_all(INS_CACHE|CACHE_INV, 0); |
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} |
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void local_icache_inv_all(void *priv) |
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{ |
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cache_op_all(INS_CACHE|CACHE_INV, 0); |
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} |
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void dcache_wb_range(unsigned long start, unsigned long end) |
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{ |
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cache_op_range(start, end, DATA_CACHE|CACHE_CLR, 0); |
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} |
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void dcache_wbinv_all(void) |
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{ |
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cache_op_all(DATA_CACHE|CACHE_CLR|CACHE_INV, 0); |
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} |
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void cache_wbinv_range(unsigned long start, unsigned long end) |
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{ |
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cache_op_range(start, end, INS_CACHE|DATA_CACHE|CACHE_CLR|CACHE_INV, 0); |
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} |
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EXPORT_SYMBOL(cache_wbinv_range); |
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void cache_wbinv_all(void) |
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{ |
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cache_op_all(INS_CACHE|DATA_CACHE|CACHE_CLR|CACHE_INV, 0); |
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} |
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void dma_wbinv_range(unsigned long start, unsigned long end) |
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{ |
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cache_op_range(start, end, DATA_CACHE|CACHE_CLR|CACHE_INV, 1); |
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} |
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void dma_inv_range(unsigned long start, unsigned long end) |
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{ |
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cache_op_range(start, end, DATA_CACHE|CACHE_CLR|CACHE_INV, 1); |
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} |
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void dma_wb_range(unsigned long start, unsigned long end) |
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{ |
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cache_op_range(start, end, DATA_CACHE|CACHE_CLR|CACHE_INV, 1); |
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}
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