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314 lines
4.8 KiB
314 lines
4.8 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef __ASM_CSKY_ENTRY_H |
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#define __ASM_CSKY_ENTRY_H |
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#include <asm/setup.h> |
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#include <abi/regdef.h> |
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#define LSAVE_PC 8 |
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#define LSAVE_PSR 12 |
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#define LSAVE_A0 24 |
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#define LSAVE_A1 28 |
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#define LSAVE_A2 32 |
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#define LSAVE_A3 36 |
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#define LSAVE_A4 40 |
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#define LSAVE_A5 44 |
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#define KSPTOUSP |
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#define USPTOKSP |
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#define usp cr<14, 1> |
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.macro SAVE_ALL epc_inc |
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subi sp, 152 |
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stw tls, (sp, 0) |
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stw lr, (sp, 4) |
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RD_MEH lr |
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WR_MEH lr |
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mfcr lr, epc |
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movi tls, \epc_inc |
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add lr, tls |
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stw lr, (sp, 8) |
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mfcr lr, epsr |
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stw lr, (sp, 12) |
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btsti lr, 31 |
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bf 1f |
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addi lr, sp, 152 |
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br 2f |
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1: |
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mfcr lr, usp |
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2: |
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stw lr, (sp, 16) |
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stw a0, (sp, 20) |
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stw a0, (sp, 24) |
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stw a1, (sp, 28) |
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stw a2, (sp, 32) |
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stw a3, (sp, 36) |
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addi sp, 40 |
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stm r4-r13, (sp) |
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addi sp, 40 |
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stm r16-r30, (sp) |
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#ifdef CONFIG_CPU_HAS_HILO |
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mfhi lr |
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stw lr, (sp, 60) |
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mflo lr |
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stw lr, (sp, 64) |
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mfcr lr, cr14 |
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stw lr, (sp, 68) |
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#endif |
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subi sp, 80 |
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.endm |
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.macro RESTORE_ALL |
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ldw tls, (sp, 0) |
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ldw lr, (sp, 4) |
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ldw a0, (sp, 8) |
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mtcr a0, epc |
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ldw a0, (sp, 12) |
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mtcr a0, epsr |
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btsti a0, 31 |
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ldw a0, (sp, 16) |
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mtcr a0, usp |
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mtcr a0, ss0 |
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#ifdef CONFIG_CPU_HAS_HILO |
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ldw a0, (sp, 140) |
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mthi a0 |
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ldw a0, (sp, 144) |
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mtlo a0 |
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ldw a0, (sp, 148) |
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mtcr a0, cr14 |
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#endif |
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ldw a0, (sp, 24) |
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ldw a1, (sp, 28) |
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ldw a2, (sp, 32) |
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ldw a3, (sp, 36) |
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addi sp, 40 |
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ldm r4-r13, (sp) |
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addi sp, 40 |
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ldm r16-r30, (sp) |
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addi sp, 72 |
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bf 1f |
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mfcr sp, ss0 |
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1: |
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rte |
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.endm |
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.macro SAVE_REGS_FTRACE |
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subi sp, 152 |
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stw tls, (sp, 0) |
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stw lr, (sp, 4) |
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mfcr lr, psr |
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stw lr, (sp, 12) |
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addi lr, sp, 152 |
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stw lr, (sp, 16) |
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stw a0, (sp, 20) |
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stw a0, (sp, 24) |
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stw a1, (sp, 28) |
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stw a2, (sp, 32) |
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stw a3, (sp, 36) |
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addi sp, 40 |
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stm r4-r13, (sp) |
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addi sp, 40 |
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stm r16-r30, (sp) |
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#ifdef CONFIG_CPU_HAS_HILO |
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mfhi lr |
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stw lr, (sp, 60) |
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mflo lr |
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stw lr, (sp, 64) |
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mfcr lr, cr14 |
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stw lr, (sp, 68) |
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#endif |
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subi sp, 80 |
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.endm |
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.macro RESTORE_REGS_FTRACE |
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ldw tls, (sp, 0) |
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#ifdef CONFIG_CPU_HAS_HILO |
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ldw a0, (sp, 140) |
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mthi a0 |
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ldw a0, (sp, 144) |
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mtlo a0 |
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ldw a0, (sp, 148) |
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mtcr a0, cr14 |
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#endif |
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ldw a0, (sp, 24) |
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ldw a1, (sp, 28) |
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ldw a2, (sp, 32) |
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ldw a3, (sp, 36) |
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addi sp, 40 |
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ldm r4-r13, (sp) |
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addi sp, 40 |
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ldm r16-r30, (sp) |
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addi sp, 72 |
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.endm |
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.macro SAVE_SWITCH_STACK |
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subi sp, 64 |
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stm r4-r11, (sp) |
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stw lr, (sp, 32) |
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stw r16, (sp, 36) |
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stw r17, (sp, 40) |
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stw r26, (sp, 44) |
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stw r27, (sp, 48) |
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stw r28, (sp, 52) |
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stw r29, (sp, 56) |
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stw r30, (sp, 60) |
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#ifdef CONFIG_CPU_HAS_HILO |
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subi sp, 16 |
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mfhi lr |
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stw lr, (sp, 0) |
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mflo lr |
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stw lr, (sp, 4) |
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mfcr lr, cr14 |
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stw lr, (sp, 8) |
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#endif |
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.endm |
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.macro RESTORE_SWITCH_STACK |
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#ifdef CONFIG_CPU_HAS_HILO |
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ldw lr, (sp, 0) |
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mthi lr |
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ldw lr, (sp, 4) |
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mtlo lr |
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ldw lr, (sp, 8) |
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mtcr lr, cr14 |
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addi sp, 16 |
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#endif |
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ldm r4-r11, (sp) |
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ldw lr, (sp, 32) |
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ldw r16, (sp, 36) |
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ldw r17, (sp, 40) |
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ldw r26, (sp, 44) |
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ldw r27, (sp, 48) |
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ldw r28, (sp, 52) |
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ldw r29, (sp, 56) |
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ldw r30, (sp, 60) |
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addi sp, 64 |
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.endm |
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/* MMU registers operators. */ |
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.macro RD_MIR rx |
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mfcr \rx, cr<0, 15> |
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.endm |
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.macro RD_MEH rx |
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mfcr \rx, cr<4, 15> |
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.endm |
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.macro RD_MCIR rx |
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mfcr \rx, cr<8, 15> |
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.endm |
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.macro RD_PGDR rx |
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mfcr \rx, cr<29, 15> |
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.endm |
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.macro RD_PGDR_K rx |
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mfcr \rx, cr<28, 15> |
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.endm |
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.macro WR_MEH rx |
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mtcr \rx, cr<4, 15> |
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.endm |
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.macro WR_MCIR rx |
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mtcr \rx, cr<8, 15> |
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.endm |
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#ifdef CONFIG_PAGE_OFFSET_80000000 |
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#define MSA_SET cr<30, 15> |
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#define MSA_CLR cr<31, 15> |
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#endif |
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#ifdef CONFIG_PAGE_OFFSET_A0000000 |
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#define MSA_SET cr<31, 15> |
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#define MSA_CLR cr<30, 15> |
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#endif |
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.macro SETUP_MMU |
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/* Init psr and enable ee */ |
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lrw r6, DEFAULT_PSR_VALUE |
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mtcr r6, psr |
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psrset ee |
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/* Invalid I/Dcache BTB BHT */ |
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movi r6, 7 |
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lsli r6, 16 |
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addi r6, (1<<4) | 3 |
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mtcr r6, cr17 |
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/* Invalid all TLB */ |
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bgeni r6, 26 |
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mtcr r6, cr<8, 15> /* Set MCIR */ |
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/* Check MMU on/off */ |
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mfcr r6, cr18 |
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btsti r6, 0 |
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bt 1f |
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/* MMU off: setup mapping tlb entry */ |
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movi r6, 0 |
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mtcr r6, cr<6, 15> /* Set MPR with 4K page size */ |
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grs r6, 1f /* Get current pa by PC */ |
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bmaski r7, (PAGE_SHIFT + 1) /* r7 = 0x1fff */ |
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andn r6, r7 |
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mtcr r6, cr<4, 15> /* Set MEH */ |
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mov r8, r6 |
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movi r7, 0x00000006 |
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or r8, r7 |
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mtcr r8, cr<2, 15> /* Set MEL0 */ |
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movi r7, 0x00001006 |
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or r8, r7 |
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mtcr r8, cr<3, 15> /* Set MEL1 */ |
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bgeni r8, 28 |
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mtcr r8, cr<8, 15> /* Set MCIR to write TLB */ |
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br 2f |
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1: |
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/* |
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* MMU on: use origin MSA value from bootloader |
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* |
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* cr<30/31, 15> MSA register format: |
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* 31 - 29 | 28 - 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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* BA Reserved SH WA B SO SEC C D V |
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*/ |
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mfcr r6, MSA_SET /* Get MSA */ |
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2: |
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lsri r6, 29 |
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lsli r6, 29 |
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addi r6, 0x1ce |
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mtcr r6, MSA_SET /* Set MSA */ |
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movi r6, 0 |
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mtcr r6, MSA_CLR /* Clr MSA */ |
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/* enable MMU */ |
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mfcr r6, cr18 |
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bseti r6, 0 |
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mtcr r6, cr18 |
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jmpi 3f /* jump to va */ |
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3: |
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.endm |
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#endif /* __ASM_CSKY_ENTRY_H */
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