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1143 lines
29 KiB
1143 lines
29 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* BPF JIT compiler for ARM64 |
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* |
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* Copyright (C) 2014-2016 Zi Shen Lim <[email protected]> |
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*/ |
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|
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#define pr_fmt(fmt) "bpf_jit: " fmt |
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|
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#include <linux/bitfield.h> |
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#include <linux/bpf.h> |
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#include <linux/filter.h> |
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#include <linux/printk.h> |
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#include <linux/slab.h> |
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|
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#include <asm/byteorder.h> |
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#include <asm/cacheflush.h> |
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#include <asm/debug-monitors.h> |
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#include <asm/set_memory.h> |
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|
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#include "bpf_jit.h" |
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|
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#define TMP_REG_1 (MAX_BPF_JIT_REG + 0) |
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#define TMP_REG_2 (MAX_BPF_JIT_REG + 1) |
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#define TCALL_CNT (MAX_BPF_JIT_REG + 2) |
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#define TMP_REG_3 (MAX_BPF_JIT_REG + 3) |
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|
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/* Map BPF registers to A64 registers */ |
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static const int bpf2a64[] = { |
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/* return value from in-kernel function, and exit value from eBPF */ |
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[BPF_REG_0] = A64_R(7), |
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/* arguments from eBPF program to in-kernel function */ |
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[BPF_REG_1] = A64_R(0), |
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[BPF_REG_2] = A64_R(1), |
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[BPF_REG_3] = A64_R(2), |
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[BPF_REG_4] = A64_R(3), |
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[BPF_REG_5] = A64_R(4), |
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/* callee saved registers that in-kernel function will preserve */ |
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[BPF_REG_6] = A64_R(19), |
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[BPF_REG_7] = A64_R(20), |
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[BPF_REG_8] = A64_R(21), |
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[BPF_REG_9] = A64_R(22), |
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/* read-only frame pointer to access stack */ |
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[BPF_REG_FP] = A64_R(25), |
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/* temporary registers for internal BPF JIT */ |
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[TMP_REG_1] = A64_R(10), |
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[TMP_REG_2] = A64_R(11), |
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[TMP_REG_3] = A64_R(12), |
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/* tail_call_cnt */ |
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[TCALL_CNT] = A64_R(26), |
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/* temporary register for blinding constants */ |
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[BPF_REG_AX] = A64_R(9), |
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}; |
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struct jit_ctx { |
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const struct bpf_prog *prog; |
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int idx; |
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int epilogue_offset; |
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int *offset; |
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int exentry_idx; |
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__le32 *image; |
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u32 stack_size; |
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}; |
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|
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static inline void emit(const u32 insn, struct jit_ctx *ctx) |
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{ |
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if (ctx->image != NULL) |
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ctx->image[ctx->idx] = cpu_to_le32(insn); |
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ctx->idx++; |
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} |
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|
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static inline void emit_a64_mov_i(const int is64, const int reg, |
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const s32 val, struct jit_ctx *ctx) |
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{ |
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u16 hi = val >> 16; |
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u16 lo = val & 0xffff; |
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|
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if (hi & 0x8000) { |
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if (hi == 0xffff) { |
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emit(A64_MOVN(is64, reg, (u16)~lo, 0), ctx); |
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} else { |
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emit(A64_MOVN(is64, reg, (u16)~hi, 16), ctx); |
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if (lo != 0xffff) |
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emit(A64_MOVK(is64, reg, lo, 0), ctx); |
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} |
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} else { |
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emit(A64_MOVZ(is64, reg, lo, 0), ctx); |
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if (hi) |
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emit(A64_MOVK(is64, reg, hi, 16), ctx); |
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} |
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} |
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|
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static int i64_i16_blocks(const u64 val, bool inverse) |
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{ |
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return (((val >> 0) & 0xffff) != (inverse ? 0xffff : 0x0000)) + |
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(((val >> 16) & 0xffff) != (inverse ? 0xffff : 0x0000)) + |
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(((val >> 32) & 0xffff) != (inverse ? 0xffff : 0x0000)) + |
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(((val >> 48) & 0xffff) != (inverse ? 0xffff : 0x0000)); |
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} |
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static inline void emit_a64_mov_i64(const int reg, const u64 val, |
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struct jit_ctx *ctx) |
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{ |
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u64 nrm_tmp = val, rev_tmp = ~val; |
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bool inverse; |
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int shift; |
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|
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if (!(nrm_tmp >> 32)) |
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return emit_a64_mov_i(0, reg, (u32)val, ctx); |
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inverse = i64_i16_blocks(nrm_tmp, true) < i64_i16_blocks(nrm_tmp, false); |
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shift = max(round_down((inverse ? (fls64(rev_tmp) - 1) : |
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(fls64(nrm_tmp) - 1)), 16), 0); |
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if (inverse) |
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emit(A64_MOVN(1, reg, (rev_tmp >> shift) & 0xffff, shift), ctx); |
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else |
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emit(A64_MOVZ(1, reg, (nrm_tmp >> shift) & 0xffff, shift), ctx); |
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shift -= 16; |
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while (shift >= 0) { |
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if (((nrm_tmp >> shift) & 0xffff) != (inverse ? 0xffff : 0x0000)) |
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emit(A64_MOVK(1, reg, (nrm_tmp >> shift) & 0xffff, shift), ctx); |
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shift -= 16; |
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} |
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} |
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|
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/* |
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* Kernel addresses in the vmalloc space use at most 48 bits, and the |
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* remaining bits are guaranteed to be 0x1. So we can compose the address |
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* with a fixed length movn/movk/movk sequence. |
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*/ |
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static inline void emit_addr_mov_i64(const int reg, const u64 val, |
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struct jit_ctx *ctx) |
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{ |
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u64 tmp = val; |
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int shift = 0; |
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|
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emit(A64_MOVN(1, reg, ~tmp & 0xffff, shift), ctx); |
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while (shift < 32) { |
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tmp >>= 16; |
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shift += 16; |
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emit(A64_MOVK(1, reg, tmp & 0xffff, shift), ctx); |
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} |
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} |
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static inline int bpf2a64_offset(int bpf_insn, int off, |
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const struct jit_ctx *ctx) |
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{ |
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/* BPF JMP offset is relative to the next instruction */ |
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bpf_insn++; |
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/* |
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* Whereas arm64 branch instructions encode the offset |
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* from the branch itself, so we must subtract 1 from the |
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* instruction offset. |
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*/ |
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return ctx->offset[bpf_insn + off] - (ctx->offset[bpf_insn] - 1); |
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} |
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|
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static void jit_fill_hole(void *area, unsigned int size) |
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{ |
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__le32 *ptr; |
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/* We are guaranteed to have aligned memory. */ |
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for (ptr = area; size >= sizeof(u32); size -= sizeof(u32)) |
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*ptr++ = cpu_to_le32(AARCH64_BREAK_FAULT); |
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} |
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|
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static inline int epilogue_offset(const struct jit_ctx *ctx) |
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{ |
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int to = ctx->epilogue_offset; |
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int from = ctx->idx; |
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return to - from; |
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} |
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|
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static bool is_addsub_imm(u32 imm) |
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{ |
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/* Either imm12 or shifted imm12. */ |
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return !(imm & ~0xfff) || !(imm & ~0xfff000); |
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} |
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|
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/* Stack must be multiples of 16B */ |
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#define STACK_ALIGN(sz) (((sz) + 15) & ~15) |
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|
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/* Tail call offset to jump into */ |
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#if IS_ENABLED(CONFIG_ARM64_BTI_KERNEL) |
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#define PROLOGUE_OFFSET 8 |
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#else |
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#define PROLOGUE_OFFSET 7 |
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#endif |
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static int build_prologue(struct jit_ctx *ctx, bool ebpf_from_cbpf) |
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{ |
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const struct bpf_prog *prog = ctx->prog; |
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const u8 r6 = bpf2a64[BPF_REG_6]; |
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const u8 r7 = bpf2a64[BPF_REG_7]; |
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const u8 r8 = bpf2a64[BPF_REG_8]; |
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const u8 r9 = bpf2a64[BPF_REG_9]; |
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const u8 fp = bpf2a64[BPF_REG_FP]; |
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const u8 tcc = bpf2a64[TCALL_CNT]; |
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const int idx0 = ctx->idx; |
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int cur_offset; |
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|
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/* |
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* BPF prog stack layout |
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* |
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* high |
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* original A64_SP => 0:+-----+ BPF prologue |
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* |FP/LR| |
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* current A64_FP => -16:+-----+ |
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* | ... | callee saved registers |
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* BPF fp register => -64:+-----+ <= (BPF_FP) |
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* | | |
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* | ... | BPF prog stack |
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* | | |
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* +-----+ <= (BPF_FP - prog->aux->stack_depth) |
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* |RSVD | padding |
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* current A64_SP => +-----+ <= (BPF_FP - ctx->stack_size) |
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* | | |
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* | ... | Function call stack |
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* | | |
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* +-----+ |
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* low |
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* |
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*/ |
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/* BTI landing pad */ |
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if (IS_ENABLED(CONFIG_ARM64_BTI_KERNEL)) |
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emit(A64_BTI_C, ctx); |
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|
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/* Save FP and LR registers to stay align with ARM64 AAPCS */ |
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emit(A64_PUSH(A64_FP, A64_LR, A64_SP), ctx); |
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emit(A64_MOV(1, A64_FP, A64_SP), ctx); |
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|
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/* Save callee-saved registers */ |
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emit(A64_PUSH(r6, r7, A64_SP), ctx); |
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emit(A64_PUSH(r8, r9, A64_SP), ctx); |
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emit(A64_PUSH(fp, tcc, A64_SP), ctx); |
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/* Set up BPF prog stack base register */ |
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emit(A64_MOV(1, fp, A64_SP), ctx); |
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if (!ebpf_from_cbpf) { |
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/* Initialize tail_call_cnt */ |
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emit(A64_MOVZ(1, tcc, 0, 0), ctx); |
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cur_offset = ctx->idx - idx0; |
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if (cur_offset != PROLOGUE_OFFSET) { |
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pr_err_once("PROLOGUE_OFFSET = %d, expected %d!\n", |
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cur_offset, PROLOGUE_OFFSET); |
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return -1; |
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} |
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/* BTI landing pad for the tail call, done with a BR */ |
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if (IS_ENABLED(CONFIG_ARM64_BTI_KERNEL)) |
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emit(A64_BTI_J, ctx); |
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} |
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ctx->stack_size = STACK_ALIGN(prog->aux->stack_depth); |
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/* Set up function call stack */ |
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emit(A64_SUB_I(1, A64_SP, A64_SP, ctx->stack_size), ctx); |
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return 0; |
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} |
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static int out_offset = -1; /* initialized on the first pass of build_body() */ |
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static int emit_bpf_tail_call(struct jit_ctx *ctx) |
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{ |
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/* bpf_tail_call(void *prog_ctx, struct bpf_array *array, u64 index) */ |
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const u8 r2 = bpf2a64[BPF_REG_2]; |
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const u8 r3 = bpf2a64[BPF_REG_3]; |
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const u8 tmp = bpf2a64[TMP_REG_1]; |
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const u8 prg = bpf2a64[TMP_REG_2]; |
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const u8 tcc = bpf2a64[TCALL_CNT]; |
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const int idx0 = ctx->idx; |
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#define cur_offset (ctx->idx - idx0) |
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#define jmp_offset (out_offset - (cur_offset)) |
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size_t off; |
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|
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/* if (index >= array->map.max_entries) |
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* goto out; |
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*/ |
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off = offsetof(struct bpf_array, map.max_entries); |
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emit_a64_mov_i64(tmp, off, ctx); |
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emit(A64_LDR32(tmp, r2, tmp), ctx); |
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emit(A64_MOV(0, r3, r3), ctx); |
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emit(A64_CMP(0, r3, tmp), ctx); |
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emit(A64_B_(A64_COND_CS, jmp_offset), ctx); |
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|
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/* if (tail_call_cnt > MAX_TAIL_CALL_CNT) |
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* goto out; |
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* tail_call_cnt++; |
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*/ |
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emit_a64_mov_i64(tmp, MAX_TAIL_CALL_CNT, ctx); |
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emit(A64_CMP(1, tcc, tmp), ctx); |
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emit(A64_B_(A64_COND_HI, jmp_offset), ctx); |
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emit(A64_ADD_I(1, tcc, tcc, 1), ctx); |
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/* prog = array->ptrs[index]; |
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* if (prog == NULL) |
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* goto out; |
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*/ |
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off = offsetof(struct bpf_array, ptrs); |
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emit_a64_mov_i64(tmp, off, ctx); |
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emit(A64_ADD(1, tmp, r2, tmp), ctx); |
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emit(A64_LSL(1, prg, r3, 3), ctx); |
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emit(A64_LDR64(prg, tmp, prg), ctx); |
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emit(A64_CBZ(1, prg, jmp_offset), ctx); |
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/* goto *(prog->bpf_func + prologue_offset); */ |
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off = offsetof(struct bpf_prog, bpf_func); |
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emit_a64_mov_i64(tmp, off, ctx); |
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emit(A64_LDR64(tmp, prg, tmp), ctx); |
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emit(A64_ADD_I(1, tmp, tmp, sizeof(u32) * PROLOGUE_OFFSET), ctx); |
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emit(A64_ADD_I(1, A64_SP, A64_SP, ctx->stack_size), ctx); |
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emit(A64_BR(tmp), ctx); |
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|
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/* out: */ |
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if (out_offset == -1) |
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out_offset = cur_offset; |
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if (cur_offset != out_offset) { |
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pr_err_once("tail_call out_offset = %d, expected %d!\n", |
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cur_offset, out_offset); |
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return -1; |
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} |
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return 0; |
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#undef cur_offset |
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#undef jmp_offset |
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} |
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|
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static void build_epilogue(struct jit_ctx *ctx) |
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{ |
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const u8 r0 = bpf2a64[BPF_REG_0]; |
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const u8 r6 = bpf2a64[BPF_REG_6]; |
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const u8 r7 = bpf2a64[BPF_REG_7]; |
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const u8 r8 = bpf2a64[BPF_REG_8]; |
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const u8 r9 = bpf2a64[BPF_REG_9]; |
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const u8 fp = bpf2a64[BPF_REG_FP]; |
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|
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/* We're done with BPF stack */ |
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emit(A64_ADD_I(1, A64_SP, A64_SP, ctx->stack_size), ctx); |
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|
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/* Restore fs (x25) and x26 */ |
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emit(A64_POP(fp, A64_R(26), A64_SP), ctx); |
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|
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/* Restore callee-saved register */ |
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emit(A64_POP(r8, r9, A64_SP), ctx); |
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emit(A64_POP(r6, r7, A64_SP), ctx); |
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|
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/* Restore FP/LR registers */ |
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emit(A64_POP(A64_FP, A64_LR, A64_SP), ctx); |
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|
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/* Set return value */ |
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emit(A64_MOV(1, A64_R(0), r0), ctx); |
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|
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emit(A64_RET(A64_LR), ctx); |
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} |
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#define BPF_FIXUP_OFFSET_MASK GENMASK(26, 0) |
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#define BPF_FIXUP_REG_MASK GENMASK(31, 27) |
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|
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int arm64_bpf_fixup_exception(const struct exception_table_entry *ex, |
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struct pt_regs *regs) |
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{ |
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off_t offset = FIELD_GET(BPF_FIXUP_OFFSET_MASK, ex->fixup); |
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int dst_reg = FIELD_GET(BPF_FIXUP_REG_MASK, ex->fixup); |
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|
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regs->regs[dst_reg] = 0; |
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regs->pc = (unsigned long)&ex->fixup - offset; |
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return 1; |
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} |
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|
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/* For accesses to BTF pointers, add an entry to the exception table */ |
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static int add_exception_handler(const struct bpf_insn *insn, |
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struct jit_ctx *ctx, |
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int dst_reg) |
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{ |
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off_t offset; |
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unsigned long pc; |
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struct exception_table_entry *ex; |
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|
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if (!ctx->image) |
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/* First pass */ |
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return 0; |
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|
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if (BPF_MODE(insn->code) != BPF_PROBE_MEM) |
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return 0; |
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|
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if (!ctx->prog->aux->extable || |
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WARN_ON_ONCE(ctx->exentry_idx >= ctx->prog->aux->num_exentries)) |
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return -EINVAL; |
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ex = &ctx->prog->aux->extable[ctx->exentry_idx]; |
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pc = (unsigned long)&ctx->image[ctx->idx - 1]; |
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|
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offset = pc - (long)&ex->insn; |
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if (WARN_ON_ONCE(offset >= 0 || offset < INT_MIN)) |
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return -ERANGE; |
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ex->insn = offset; |
|
|
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/* |
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* Since the extable follows the program, the fixup offset is always |
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* negative and limited to BPF_JIT_REGION_SIZE. Store a positive value |
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* to keep things simple, and put the destination register in the upper |
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* bits. We don't need to worry about buildtime or runtime sort |
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* modifying the upper bits because the table is already sorted, and |
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* isn't part of the main exception table. |
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*/ |
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offset = (long)&ex->fixup - (pc + AARCH64_INSN_SIZE); |
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if (!FIELD_FIT(BPF_FIXUP_OFFSET_MASK, offset)) |
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return -ERANGE; |
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|
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ex->fixup = FIELD_PREP(BPF_FIXUP_OFFSET_MASK, offset) | |
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FIELD_PREP(BPF_FIXUP_REG_MASK, dst_reg); |
|
|
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ctx->exentry_idx++; |
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return 0; |
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} |
|
|
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/* JITs an eBPF instruction. |
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* Returns: |
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* 0 - successfully JITed an 8-byte eBPF instruction. |
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* >0 - successfully JITed a 16-byte eBPF instruction. |
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* <0 - failed to JIT. |
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*/ |
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static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx, |
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bool extra_pass) |
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{ |
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const u8 code = insn->code; |
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const u8 dst = bpf2a64[insn->dst_reg]; |
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const u8 src = bpf2a64[insn->src_reg]; |
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const u8 tmp = bpf2a64[TMP_REG_1]; |
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const u8 tmp2 = bpf2a64[TMP_REG_2]; |
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const u8 tmp3 = bpf2a64[TMP_REG_3]; |
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const s16 off = insn->off; |
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const s32 imm = insn->imm; |
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const int i = insn - ctx->prog->insnsi; |
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const bool is64 = BPF_CLASS(code) == BPF_ALU64 || |
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BPF_CLASS(code) == BPF_JMP; |
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const bool isdw = BPF_SIZE(code) == BPF_DW; |
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u8 jmp_cond, reg; |
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s32 jmp_offset; |
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u32 a64_insn; |
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int ret; |
|
|
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#define check_imm(bits, imm) do { \ |
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if ((((imm) > 0) && ((imm) >> (bits))) || \ |
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(((imm) < 0) && (~(imm) >> (bits)))) { \ |
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pr_info("[%2d] imm=%d(0x%x) out of range\n", \ |
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i, imm, imm); \ |
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return -EINVAL; \ |
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} \ |
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} while (0) |
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#define check_imm19(imm) check_imm(19, imm) |
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#define check_imm26(imm) check_imm(26, imm) |
|
|
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switch (code) { |
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/* dst = src */ |
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case BPF_ALU | BPF_MOV | BPF_X: |
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case BPF_ALU64 | BPF_MOV | BPF_X: |
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emit(A64_MOV(is64, dst, src), ctx); |
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break; |
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/* dst = dst OP src */ |
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case BPF_ALU | BPF_ADD | BPF_X: |
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case BPF_ALU64 | BPF_ADD | BPF_X: |
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emit(A64_ADD(is64, dst, dst, src), ctx); |
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break; |
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case BPF_ALU | BPF_SUB | BPF_X: |
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case BPF_ALU64 | BPF_SUB | BPF_X: |
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emit(A64_SUB(is64, dst, dst, src), ctx); |
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break; |
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case BPF_ALU | BPF_AND | BPF_X: |
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case BPF_ALU64 | BPF_AND | BPF_X: |
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emit(A64_AND(is64, dst, dst, src), ctx); |
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break; |
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case BPF_ALU | BPF_OR | BPF_X: |
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case BPF_ALU64 | BPF_OR | BPF_X: |
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emit(A64_ORR(is64, dst, dst, src), ctx); |
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break; |
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case BPF_ALU | BPF_XOR | BPF_X: |
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case BPF_ALU64 | BPF_XOR | BPF_X: |
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emit(A64_EOR(is64, dst, dst, src), ctx); |
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break; |
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case BPF_ALU | BPF_MUL | BPF_X: |
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case BPF_ALU64 | BPF_MUL | BPF_X: |
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emit(A64_MUL(is64, dst, dst, src), ctx); |
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break; |
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case BPF_ALU | BPF_DIV | BPF_X: |
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case BPF_ALU64 | BPF_DIV | BPF_X: |
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case BPF_ALU | BPF_MOD | BPF_X: |
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case BPF_ALU64 | BPF_MOD | BPF_X: |
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switch (BPF_OP(code)) { |
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case BPF_DIV: |
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emit(A64_UDIV(is64, dst, dst, src), ctx); |
|
break; |
|
case BPF_MOD: |
|
emit(A64_UDIV(is64, tmp, dst, src), ctx); |
|
emit(A64_MSUB(is64, dst, dst, tmp, src), ctx); |
|
break; |
|
} |
|
break; |
|
case BPF_ALU | BPF_LSH | BPF_X: |
|
case BPF_ALU64 | BPF_LSH | BPF_X: |
|
emit(A64_LSLV(is64, dst, dst, src), ctx); |
|
break; |
|
case BPF_ALU | BPF_RSH | BPF_X: |
|
case BPF_ALU64 | BPF_RSH | BPF_X: |
|
emit(A64_LSRV(is64, dst, dst, src), ctx); |
|
break; |
|
case BPF_ALU | BPF_ARSH | BPF_X: |
|
case BPF_ALU64 | BPF_ARSH | BPF_X: |
|
emit(A64_ASRV(is64, dst, dst, src), ctx); |
|
break; |
|
/* dst = -dst */ |
|
case BPF_ALU | BPF_NEG: |
|
case BPF_ALU64 | BPF_NEG: |
|
emit(A64_NEG(is64, dst, dst), ctx); |
|
break; |
|
/* dst = BSWAP##imm(dst) */ |
|
case BPF_ALU | BPF_END | BPF_FROM_LE: |
|
case BPF_ALU | BPF_END | BPF_FROM_BE: |
|
#ifdef CONFIG_CPU_BIG_ENDIAN |
|
if (BPF_SRC(code) == BPF_FROM_BE) |
|
goto emit_bswap_uxt; |
|
#else /* !CONFIG_CPU_BIG_ENDIAN */ |
|
if (BPF_SRC(code) == BPF_FROM_LE) |
|
goto emit_bswap_uxt; |
|
#endif |
|
switch (imm) { |
|
case 16: |
|
emit(A64_REV16(is64, dst, dst), ctx); |
|
/* zero-extend 16 bits into 64 bits */ |
|
emit(A64_UXTH(is64, dst, dst), ctx); |
|
break; |
|
case 32: |
|
emit(A64_REV32(is64, dst, dst), ctx); |
|
/* upper 32 bits already cleared */ |
|
break; |
|
case 64: |
|
emit(A64_REV64(dst, dst), ctx); |
|
break; |
|
} |
|
break; |
|
emit_bswap_uxt: |
|
switch (imm) { |
|
case 16: |
|
/* zero-extend 16 bits into 64 bits */ |
|
emit(A64_UXTH(is64, dst, dst), ctx); |
|
break; |
|
case 32: |
|
/* zero-extend 32 bits into 64 bits */ |
|
emit(A64_UXTW(is64, dst, dst), ctx); |
|
break; |
|
case 64: |
|
/* nop */ |
|
break; |
|
} |
|
break; |
|
/* dst = imm */ |
|
case BPF_ALU | BPF_MOV | BPF_K: |
|
case BPF_ALU64 | BPF_MOV | BPF_K: |
|
emit_a64_mov_i(is64, dst, imm, ctx); |
|
break; |
|
/* dst = dst OP imm */ |
|
case BPF_ALU | BPF_ADD | BPF_K: |
|
case BPF_ALU64 | BPF_ADD | BPF_K: |
|
if (is_addsub_imm(imm)) { |
|
emit(A64_ADD_I(is64, dst, dst, imm), ctx); |
|
} else if (is_addsub_imm(-imm)) { |
|
emit(A64_SUB_I(is64, dst, dst, -imm), ctx); |
|
} else { |
|
emit_a64_mov_i(is64, tmp, imm, ctx); |
|
emit(A64_ADD(is64, dst, dst, tmp), ctx); |
|
} |
|
break; |
|
case BPF_ALU | BPF_SUB | BPF_K: |
|
case BPF_ALU64 | BPF_SUB | BPF_K: |
|
if (is_addsub_imm(imm)) { |
|
emit(A64_SUB_I(is64, dst, dst, imm), ctx); |
|
} else if (is_addsub_imm(-imm)) { |
|
emit(A64_ADD_I(is64, dst, dst, -imm), ctx); |
|
} else { |
|
emit_a64_mov_i(is64, tmp, imm, ctx); |
|
emit(A64_SUB(is64, dst, dst, tmp), ctx); |
|
} |
|
break; |
|
case BPF_ALU | BPF_AND | BPF_K: |
|
case BPF_ALU64 | BPF_AND | BPF_K: |
|
a64_insn = A64_AND_I(is64, dst, dst, imm); |
|
if (a64_insn != AARCH64_BREAK_FAULT) { |
|
emit(a64_insn, ctx); |
|
} else { |
|
emit_a64_mov_i(is64, tmp, imm, ctx); |
|
emit(A64_AND(is64, dst, dst, tmp), ctx); |
|
} |
|
break; |
|
case BPF_ALU | BPF_OR | BPF_K: |
|
case BPF_ALU64 | BPF_OR | BPF_K: |
|
a64_insn = A64_ORR_I(is64, dst, dst, imm); |
|
if (a64_insn != AARCH64_BREAK_FAULT) { |
|
emit(a64_insn, ctx); |
|
} else { |
|
emit_a64_mov_i(is64, tmp, imm, ctx); |
|
emit(A64_ORR(is64, dst, dst, tmp), ctx); |
|
} |
|
break; |
|
case BPF_ALU | BPF_XOR | BPF_K: |
|
case BPF_ALU64 | BPF_XOR | BPF_K: |
|
a64_insn = A64_EOR_I(is64, dst, dst, imm); |
|
if (a64_insn != AARCH64_BREAK_FAULT) { |
|
emit(a64_insn, ctx); |
|
} else { |
|
emit_a64_mov_i(is64, tmp, imm, ctx); |
|
emit(A64_EOR(is64, dst, dst, tmp), ctx); |
|
} |
|
break; |
|
case BPF_ALU | BPF_MUL | BPF_K: |
|
case BPF_ALU64 | BPF_MUL | BPF_K: |
|
emit_a64_mov_i(is64, tmp, imm, ctx); |
|
emit(A64_MUL(is64, dst, dst, tmp), ctx); |
|
break; |
|
case BPF_ALU | BPF_DIV | BPF_K: |
|
case BPF_ALU64 | BPF_DIV | BPF_K: |
|
emit_a64_mov_i(is64, tmp, imm, ctx); |
|
emit(A64_UDIV(is64, dst, dst, tmp), ctx); |
|
break; |
|
case BPF_ALU | BPF_MOD | BPF_K: |
|
case BPF_ALU64 | BPF_MOD | BPF_K: |
|
emit_a64_mov_i(is64, tmp2, imm, ctx); |
|
emit(A64_UDIV(is64, tmp, dst, tmp2), ctx); |
|
emit(A64_MSUB(is64, dst, dst, tmp, tmp2), ctx); |
|
break; |
|
case BPF_ALU | BPF_LSH | BPF_K: |
|
case BPF_ALU64 | BPF_LSH | BPF_K: |
|
emit(A64_LSL(is64, dst, dst, imm), ctx); |
|
break; |
|
case BPF_ALU | BPF_RSH | BPF_K: |
|
case BPF_ALU64 | BPF_RSH | BPF_K: |
|
emit(A64_LSR(is64, dst, dst, imm), ctx); |
|
break; |
|
case BPF_ALU | BPF_ARSH | BPF_K: |
|
case BPF_ALU64 | BPF_ARSH | BPF_K: |
|
emit(A64_ASR(is64, dst, dst, imm), ctx); |
|
break; |
|
|
|
/* JUMP off */ |
|
case BPF_JMP | BPF_JA: |
|
jmp_offset = bpf2a64_offset(i, off, ctx); |
|
check_imm26(jmp_offset); |
|
emit(A64_B(jmp_offset), ctx); |
|
break; |
|
/* IF (dst COND src) JUMP off */ |
|
case BPF_JMP | BPF_JEQ | BPF_X: |
|
case BPF_JMP | BPF_JGT | BPF_X: |
|
case BPF_JMP | BPF_JLT | BPF_X: |
|
case BPF_JMP | BPF_JGE | BPF_X: |
|
case BPF_JMP | BPF_JLE | BPF_X: |
|
case BPF_JMP | BPF_JNE | BPF_X: |
|
case BPF_JMP | BPF_JSGT | BPF_X: |
|
case BPF_JMP | BPF_JSLT | BPF_X: |
|
case BPF_JMP | BPF_JSGE | BPF_X: |
|
case BPF_JMP | BPF_JSLE | BPF_X: |
|
case BPF_JMP32 | BPF_JEQ | BPF_X: |
|
case BPF_JMP32 | BPF_JGT | BPF_X: |
|
case BPF_JMP32 | BPF_JLT | BPF_X: |
|
case BPF_JMP32 | BPF_JGE | BPF_X: |
|
case BPF_JMP32 | BPF_JLE | BPF_X: |
|
case BPF_JMP32 | BPF_JNE | BPF_X: |
|
case BPF_JMP32 | BPF_JSGT | BPF_X: |
|
case BPF_JMP32 | BPF_JSLT | BPF_X: |
|
case BPF_JMP32 | BPF_JSGE | BPF_X: |
|
case BPF_JMP32 | BPF_JSLE | BPF_X: |
|
emit(A64_CMP(is64, dst, src), ctx); |
|
emit_cond_jmp: |
|
jmp_offset = bpf2a64_offset(i, off, ctx); |
|
check_imm19(jmp_offset); |
|
switch (BPF_OP(code)) { |
|
case BPF_JEQ: |
|
jmp_cond = A64_COND_EQ; |
|
break; |
|
case BPF_JGT: |
|
jmp_cond = A64_COND_HI; |
|
break; |
|
case BPF_JLT: |
|
jmp_cond = A64_COND_CC; |
|
break; |
|
case BPF_JGE: |
|
jmp_cond = A64_COND_CS; |
|
break; |
|
case BPF_JLE: |
|
jmp_cond = A64_COND_LS; |
|
break; |
|
case BPF_JSET: |
|
case BPF_JNE: |
|
jmp_cond = A64_COND_NE; |
|
break; |
|
case BPF_JSGT: |
|
jmp_cond = A64_COND_GT; |
|
break; |
|
case BPF_JSLT: |
|
jmp_cond = A64_COND_LT; |
|
break; |
|
case BPF_JSGE: |
|
jmp_cond = A64_COND_GE; |
|
break; |
|
case BPF_JSLE: |
|
jmp_cond = A64_COND_LE; |
|
break; |
|
default: |
|
return -EFAULT; |
|
} |
|
emit(A64_B_(jmp_cond, jmp_offset), ctx); |
|
break; |
|
case BPF_JMP | BPF_JSET | BPF_X: |
|
case BPF_JMP32 | BPF_JSET | BPF_X: |
|
emit(A64_TST(is64, dst, src), ctx); |
|
goto emit_cond_jmp; |
|
/* IF (dst COND imm) JUMP off */ |
|
case BPF_JMP | BPF_JEQ | BPF_K: |
|
case BPF_JMP | BPF_JGT | BPF_K: |
|
case BPF_JMP | BPF_JLT | BPF_K: |
|
case BPF_JMP | BPF_JGE | BPF_K: |
|
case BPF_JMP | BPF_JLE | BPF_K: |
|
case BPF_JMP | BPF_JNE | BPF_K: |
|
case BPF_JMP | BPF_JSGT | BPF_K: |
|
case BPF_JMP | BPF_JSLT | BPF_K: |
|
case BPF_JMP | BPF_JSGE | BPF_K: |
|
case BPF_JMP | BPF_JSLE | BPF_K: |
|
case BPF_JMP32 | BPF_JEQ | BPF_K: |
|
case BPF_JMP32 | BPF_JGT | BPF_K: |
|
case BPF_JMP32 | BPF_JLT | BPF_K: |
|
case BPF_JMP32 | BPF_JGE | BPF_K: |
|
case BPF_JMP32 | BPF_JLE | BPF_K: |
|
case BPF_JMP32 | BPF_JNE | BPF_K: |
|
case BPF_JMP32 | BPF_JSGT | BPF_K: |
|
case BPF_JMP32 | BPF_JSLT | BPF_K: |
|
case BPF_JMP32 | BPF_JSGE | BPF_K: |
|
case BPF_JMP32 | BPF_JSLE | BPF_K: |
|
if (is_addsub_imm(imm)) { |
|
emit(A64_CMP_I(is64, dst, imm), ctx); |
|
} else if (is_addsub_imm(-imm)) { |
|
emit(A64_CMN_I(is64, dst, -imm), ctx); |
|
} else { |
|
emit_a64_mov_i(is64, tmp, imm, ctx); |
|
emit(A64_CMP(is64, dst, tmp), ctx); |
|
} |
|
goto emit_cond_jmp; |
|
case BPF_JMP | BPF_JSET | BPF_K: |
|
case BPF_JMP32 | BPF_JSET | BPF_K: |
|
a64_insn = A64_TST_I(is64, dst, imm); |
|
if (a64_insn != AARCH64_BREAK_FAULT) { |
|
emit(a64_insn, ctx); |
|
} else { |
|
emit_a64_mov_i(is64, tmp, imm, ctx); |
|
emit(A64_TST(is64, dst, tmp), ctx); |
|
} |
|
goto emit_cond_jmp; |
|
/* function call */ |
|
case BPF_JMP | BPF_CALL: |
|
{ |
|
const u8 r0 = bpf2a64[BPF_REG_0]; |
|
bool func_addr_fixed; |
|
u64 func_addr; |
|
|
|
ret = bpf_jit_get_func_addr(ctx->prog, insn, extra_pass, |
|
&func_addr, &func_addr_fixed); |
|
if (ret < 0) |
|
return ret; |
|
emit_addr_mov_i64(tmp, func_addr, ctx); |
|
emit(A64_BLR(tmp), ctx); |
|
emit(A64_MOV(1, r0, A64_R(0)), ctx); |
|
break; |
|
} |
|
/* tail call */ |
|
case BPF_JMP | BPF_TAIL_CALL: |
|
if (emit_bpf_tail_call(ctx)) |
|
return -EFAULT; |
|
break; |
|
/* function return */ |
|
case BPF_JMP | BPF_EXIT: |
|
/* Optimization: when last instruction is EXIT, |
|
simply fallthrough to epilogue. */ |
|
if (i == ctx->prog->len - 1) |
|
break; |
|
jmp_offset = epilogue_offset(ctx); |
|
check_imm26(jmp_offset); |
|
emit(A64_B(jmp_offset), ctx); |
|
break; |
|
|
|
/* dst = imm64 */ |
|
case BPF_LD | BPF_IMM | BPF_DW: |
|
{ |
|
const struct bpf_insn insn1 = insn[1]; |
|
u64 imm64; |
|
|
|
imm64 = (u64)insn1.imm << 32 | (u32)imm; |
|
emit_a64_mov_i64(dst, imm64, ctx); |
|
|
|
return 1; |
|
} |
|
|
|
/* LDX: dst = *(size *)(src + off) */ |
|
case BPF_LDX | BPF_MEM | BPF_W: |
|
case BPF_LDX | BPF_MEM | BPF_H: |
|
case BPF_LDX | BPF_MEM | BPF_B: |
|
case BPF_LDX | BPF_MEM | BPF_DW: |
|
case BPF_LDX | BPF_PROBE_MEM | BPF_DW: |
|
case BPF_LDX | BPF_PROBE_MEM | BPF_W: |
|
case BPF_LDX | BPF_PROBE_MEM | BPF_H: |
|
case BPF_LDX | BPF_PROBE_MEM | BPF_B: |
|
emit_a64_mov_i(1, tmp, off, ctx); |
|
switch (BPF_SIZE(code)) { |
|
case BPF_W: |
|
emit(A64_LDR32(dst, src, tmp), ctx); |
|
break; |
|
case BPF_H: |
|
emit(A64_LDRH(dst, src, tmp), ctx); |
|
break; |
|
case BPF_B: |
|
emit(A64_LDRB(dst, src, tmp), ctx); |
|
break; |
|
case BPF_DW: |
|
emit(A64_LDR64(dst, src, tmp), ctx); |
|
break; |
|
} |
|
|
|
ret = add_exception_handler(insn, ctx, dst); |
|
if (ret) |
|
return ret; |
|
break; |
|
|
|
/* ST: *(size *)(dst + off) = imm */ |
|
case BPF_ST | BPF_MEM | BPF_W: |
|
case BPF_ST | BPF_MEM | BPF_H: |
|
case BPF_ST | BPF_MEM | BPF_B: |
|
case BPF_ST | BPF_MEM | BPF_DW: |
|
/* Load imm to a register then store it */ |
|
emit_a64_mov_i(1, tmp2, off, ctx); |
|
emit_a64_mov_i(1, tmp, imm, ctx); |
|
switch (BPF_SIZE(code)) { |
|
case BPF_W: |
|
emit(A64_STR32(tmp, dst, tmp2), ctx); |
|
break; |
|
case BPF_H: |
|
emit(A64_STRH(tmp, dst, tmp2), ctx); |
|
break; |
|
case BPF_B: |
|
emit(A64_STRB(tmp, dst, tmp2), ctx); |
|
break; |
|
case BPF_DW: |
|
emit(A64_STR64(tmp, dst, tmp2), ctx); |
|
break; |
|
} |
|
break; |
|
|
|
/* STX: *(size *)(dst + off) = src */ |
|
case BPF_STX | BPF_MEM | BPF_W: |
|
case BPF_STX | BPF_MEM | BPF_H: |
|
case BPF_STX | BPF_MEM | BPF_B: |
|
case BPF_STX | BPF_MEM | BPF_DW: |
|
emit_a64_mov_i(1, tmp, off, ctx); |
|
switch (BPF_SIZE(code)) { |
|
case BPF_W: |
|
emit(A64_STR32(src, dst, tmp), ctx); |
|
break; |
|
case BPF_H: |
|
emit(A64_STRH(src, dst, tmp), ctx); |
|
break; |
|
case BPF_B: |
|
emit(A64_STRB(src, dst, tmp), ctx); |
|
break; |
|
case BPF_DW: |
|
emit(A64_STR64(src, dst, tmp), ctx); |
|
break; |
|
} |
|
break; |
|
|
|
case BPF_STX | BPF_ATOMIC | BPF_W: |
|
case BPF_STX | BPF_ATOMIC | BPF_DW: |
|
if (insn->imm != BPF_ADD) { |
|
pr_err_once("unknown atomic op code %02x\n", insn->imm); |
|
return -EINVAL; |
|
} |
|
|
|
/* STX XADD: lock *(u32 *)(dst + off) += src |
|
* and |
|
* STX XADD: lock *(u64 *)(dst + off) += src |
|
*/ |
|
|
|
if (!off) { |
|
reg = dst; |
|
} else { |
|
emit_a64_mov_i(1, tmp, off, ctx); |
|
emit(A64_ADD(1, tmp, tmp, dst), ctx); |
|
reg = tmp; |
|
} |
|
if (cpus_have_cap(ARM64_HAS_LSE_ATOMICS)) { |
|
emit(A64_STADD(isdw, reg, src), ctx); |
|
} else { |
|
emit(A64_LDXR(isdw, tmp2, reg), ctx); |
|
emit(A64_ADD(isdw, tmp2, tmp2, src), ctx); |
|
emit(A64_STXR(isdw, tmp2, reg, tmp3), ctx); |
|
jmp_offset = -3; |
|
check_imm19(jmp_offset); |
|
emit(A64_CBNZ(0, tmp3, jmp_offset), ctx); |
|
} |
|
break; |
|
|
|
default: |
|
pr_err_once("unknown opcode %02x\n", code); |
|
return -EINVAL; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int build_body(struct jit_ctx *ctx, bool extra_pass) |
|
{ |
|
const struct bpf_prog *prog = ctx->prog; |
|
int i; |
|
|
|
/* |
|
* - offset[0] offset of the end of prologue, |
|
* start of the 1st instruction. |
|
* - offset[1] - offset of the end of 1st instruction, |
|
* start of the 2nd instruction |
|
* [....] |
|
* - offset[3] - offset of the end of 3rd instruction, |
|
* start of 4th instruction |
|
*/ |
|
for (i = 0; i < prog->len; i++) { |
|
const struct bpf_insn *insn = &prog->insnsi[i]; |
|
int ret; |
|
|
|
if (ctx->image == NULL) |
|
ctx->offset[i] = ctx->idx; |
|
ret = build_insn(insn, ctx, extra_pass); |
|
if (ret > 0) { |
|
i++; |
|
if (ctx->image == NULL) |
|
ctx->offset[i] = ctx->idx; |
|
continue; |
|
} |
|
if (ret) |
|
return ret; |
|
} |
|
/* |
|
* offset is allocated with prog->len + 1 so fill in |
|
* the last element with the offset after the last |
|
* instruction (end of program) |
|
*/ |
|
if (ctx->image == NULL) |
|
ctx->offset[i] = ctx->idx; |
|
|
|
return 0; |
|
} |
|
|
|
static int validate_code(struct jit_ctx *ctx) |
|
{ |
|
int i; |
|
|
|
for (i = 0; i < ctx->idx; i++) { |
|
u32 a64_insn = le32_to_cpu(ctx->image[i]); |
|
|
|
if (a64_insn == AARCH64_BREAK_FAULT) |
|
return -1; |
|
} |
|
|
|
if (WARN_ON_ONCE(ctx->exentry_idx != ctx->prog->aux->num_exentries)) |
|
return -1; |
|
|
|
return 0; |
|
} |
|
|
|
static inline void bpf_flush_icache(void *start, void *end) |
|
{ |
|
flush_icache_range((unsigned long)start, (unsigned long)end); |
|
} |
|
|
|
struct arm64_jit_data { |
|
struct bpf_binary_header *header; |
|
u8 *image; |
|
struct jit_ctx ctx; |
|
}; |
|
|
|
struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog) |
|
{ |
|
int image_size, prog_size, extable_size; |
|
struct bpf_prog *tmp, *orig_prog = prog; |
|
struct bpf_binary_header *header; |
|
struct arm64_jit_data *jit_data; |
|
bool was_classic = bpf_prog_was_classic(prog); |
|
bool tmp_blinded = false; |
|
bool extra_pass = false; |
|
struct jit_ctx ctx; |
|
u8 *image_ptr; |
|
|
|
if (!prog->jit_requested) |
|
return orig_prog; |
|
|
|
tmp = bpf_jit_blind_constants(prog); |
|
/* If blinding was requested and we failed during blinding, |
|
* we must fall back to the interpreter. |
|
*/ |
|
if (IS_ERR(tmp)) |
|
return orig_prog; |
|
if (tmp != prog) { |
|
tmp_blinded = true; |
|
prog = tmp; |
|
} |
|
|
|
jit_data = prog->aux->jit_data; |
|
if (!jit_data) { |
|
jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL); |
|
if (!jit_data) { |
|
prog = orig_prog; |
|
goto out; |
|
} |
|
prog->aux->jit_data = jit_data; |
|
} |
|
if (jit_data->ctx.offset) { |
|
ctx = jit_data->ctx; |
|
image_ptr = jit_data->image; |
|
header = jit_data->header; |
|
extra_pass = true; |
|
prog_size = sizeof(u32) * ctx.idx; |
|
goto skip_init_ctx; |
|
} |
|
memset(&ctx, 0, sizeof(ctx)); |
|
ctx.prog = prog; |
|
|
|
ctx.offset = kcalloc(prog->len + 1, sizeof(int), GFP_KERNEL); |
|
if (ctx.offset == NULL) { |
|
prog = orig_prog; |
|
goto out_off; |
|
} |
|
|
|
/* 1. Initial fake pass to compute ctx->idx. */ |
|
|
|
/* Fake pass to fill in ctx->offset. */ |
|
if (build_body(&ctx, extra_pass)) { |
|
prog = orig_prog; |
|
goto out_off; |
|
} |
|
|
|
if (build_prologue(&ctx, was_classic)) { |
|
prog = orig_prog; |
|
goto out_off; |
|
} |
|
|
|
ctx.epilogue_offset = ctx.idx; |
|
build_epilogue(&ctx); |
|
|
|
extable_size = prog->aux->num_exentries * |
|
sizeof(struct exception_table_entry); |
|
|
|
/* Now we know the actual image size. */ |
|
prog_size = sizeof(u32) * ctx.idx; |
|
image_size = prog_size + extable_size; |
|
header = bpf_jit_binary_alloc(image_size, &image_ptr, |
|
sizeof(u32), jit_fill_hole); |
|
if (header == NULL) { |
|
prog = orig_prog; |
|
goto out_off; |
|
} |
|
|
|
/* 2. Now, the actual pass. */ |
|
|
|
ctx.image = (__le32 *)image_ptr; |
|
if (extable_size) |
|
prog->aux->extable = (void *)image_ptr + prog_size; |
|
skip_init_ctx: |
|
ctx.idx = 0; |
|
ctx.exentry_idx = 0; |
|
|
|
build_prologue(&ctx, was_classic); |
|
|
|
if (build_body(&ctx, extra_pass)) { |
|
bpf_jit_binary_free(header); |
|
prog = orig_prog; |
|
goto out_off; |
|
} |
|
|
|
build_epilogue(&ctx); |
|
|
|
/* 3. Extra pass to validate JITed code. */ |
|
if (validate_code(&ctx)) { |
|
bpf_jit_binary_free(header); |
|
prog = orig_prog; |
|
goto out_off; |
|
} |
|
|
|
/* And we're done. */ |
|
if (bpf_jit_enable > 1) |
|
bpf_jit_dump(prog->len, prog_size, 2, ctx.image); |
|
|
|
bpf_flush_icache(header, ctx.image + ctx.idx); |
|
|
|
if (!prog->is_func || extra_pass) { |
|
if (extra_pass && ctx.idx != jit_data->ctx.idx) { |
|
pr_err_once("multi-func JIT bug %d != %d\n", |
|
ctx.idx, jit_data->ctx.idx); |
|
bpf_jit_binary_free(header); |
|
prog->bpf_func = NULL; |
|
prog->jited = 0; |
|
goto out_off; |
|
} |
|
bpf_jit_binary_lock_ro(header); |
|
} else { |
|
jit_data->ctx = ctx; |
|
jit_data->image = image_ptr; |
|
jit_data->header = header; |
|
} |
|
prog->bpf_func = (void *)ctx.image; |
|
prog->jited = 1; |
|
prog->jited_len = prog_size; |
|
|
|
if (!prog->is_func || extra_pass) { |
|
bpf_prog_fill_jited_linfo(prog, ctx.offset + 1); |
|
out_off: |
|
kfree(ctx.offset); |
|
kfree(jit_data); |
|
prog->aux->jit_data = NULL; |
|
} |
|
out: |
|
if (tmp_blinded) |
|
bpf_jit_prog_release_other(prog, prog == orig_prog ? |
|
tmp : orig_prog); |
|
return prog; |
|
} |
|
|
|
void *bpf_jit_alloc_exec(unsigned long size) |
|
{ |
|
return __vmalloc_node_range(size, PAGE_SIZE, BPF_JIT_REGION_START, |
|
BPF_JIT_REGION_END, GFP_KERNEL, |
|
PAGE_KERNEL, 0, NUMA_NO_NODE, |
|
__builtin_return_address(0)); |
|
} |
|
|
|
void bpf_jit_free_exec(void *addr) |
|
{ |
|
return vfree(addr); |
|
}
|
|
|