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1008 lines
25 KiB
1008 lines
25 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Based on arch/arm/kernel/traps.c |
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* |
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* Copyright (C) 1995-2009 Russell King |
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* Copyright (C) 2012 ARM Ltd. |
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*/ |
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|
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#include <linux/bug.h> |
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#include <linux/context_tracking.h> |
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#include <linux/signal.h> |
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#include <linux/personality.h> |
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#include <linux/kallsyms.h> |
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#include <linux/kprobes.h> |
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#include <linux/spinlock.h> |
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#include <linux/uaccess.h> |
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#include <linux/hardirq.h> |
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#include <linux/kdebug.h> |
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#include <linux/module.h> |
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#include <linux/kexec.h> |
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#include <linux/delay.h> |
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#include <linux/init.h> |
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#include <linux/sched/signal.h> |
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#include <linux/sched/debug.h> |
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#include <linux/sched/task_stack.h> |
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#include <linux/sizes.h> |
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#include <linux/syscalls.h> |
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#include <linux/mm_types.h> |
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#include <linux/kasan.h> |
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#include <asm/atomic.h> |
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#include <asm/bug.h> |
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#include <asm/cpufeature.h> |
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#include <asm/daifflags.h> |
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#include <asm/debug-monitors.h> |
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#include <asm/esr.h> |
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#include <asm/exception.h> |
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#include <asm/extable.h> |
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#include <asm/insn.h> |
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#include <asm/kprobes.h> |
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#include <asm/traps.h> |
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#include <asm/smp.h> |
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#include <asm/stack_pointer.h> |
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#include <asm/stacktrace.h> |
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#include <asm/system_misc.h> |
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#include <asm/sysreg.h> |
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static const char *handler[] = { |
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"Synchronous Abort", |
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"IRQ", |
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"FIQ", |
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"Error" |
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}; |
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int show_unhandled_signals = 0; |
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static void dump_kernel_instr(const char *lvl, struct pt_regs *regs) |
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{ |
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unsigned long addr = instruction_pointer(regs); |
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char str[sizeof("00000000 ") * 5 + 2 + 1], *p = str; |
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int i; |
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if (user_mode(regs)) |
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return; |
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for (i = -4; i < 1; i++) { |
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unsigned int val, bad; |
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bad = aarch64_insn_read(&((u32 *)addr)[i], &val); |
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if (!bad) |
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p += sprintf(p, i == 0 ? "(%08x) " : "%08x ", val); |
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else { |
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p += sprintf(p, "bad PC value"); |
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break; |
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} |
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} |
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printk("%sCode: %s\n", lvl, str); |
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} |
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#ifdef CONFIG_PREEMPT |
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#define S_PREEMPT " PREEMPT" |
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#elif defined(CONFIG_PREEMPT_RT) |
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#define S_PREEMPT " PREEMPT_RT" |
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#else |
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#define S_PREEMPT "" |
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#endif |
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#define S_SMP " SMP" |
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static int __die(const char *str, int err, struct pt_regs *regs) |
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{ |
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static int die_counter; |
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int ret; |
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pr_emerg("Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n", |
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str, err, ++die_counter); |
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/* trap and error numbers are mostly meaningless on ARM */ |
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ret = notify_die(DIE_OOPS, str, regs, err, 0, SIGSEGV); |
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if (ret == NOTIFY_STOP) |
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return ret; |
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print_modules(); |
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show_regs(regs); |
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dump_kernel_instr(KERN_EMERG, regs); |
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return ret; |
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} |
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static DEFINE_RAW_SPINLOCK(die_lock); |
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/* |
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* This function is protected against re-entrancy. |
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*/ |
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void die(const char *str, struct pt_regs *regs, int err) |
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{ |
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int ret; |
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unsigned long flags; |
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raw_spin_lock_irqsave(&die_lock, flags); |
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oops_enter(); |
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console_verbose(); |
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bust_spinlocks(1); |
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ret = __die(str, err, regs); |
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if (regs && kexec_should_crash(current)) |
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crash_kexec(regs); |
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bust_spinlocks(0); |
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add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); |
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oops_exit(); |
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if (in_interrupt()) |
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panic("%s: Fatal exception in interrupt", str); |
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if (panic_on_oops) |
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panic("%s: Fatal exception", str); |
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raw_spin_unlock_irqrestore(&die_lock, flags); |
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if (ret != NOTIFY_STOP) |
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do_exit(SIGSEGV); |
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} |
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static void arm64_show_signal(int signo, const char *str) |
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{ |
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static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL, |
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DEFAULT_RATELIMIT_BURST); |
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struct task_struct *tsk = current; |
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unsigned int esr = tsk->thread.fault_code; |
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struct pt_regs *regs = task_pt_regs(tsk); |
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/* Leave if the signal won't be shown */ |
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if (!show_unhandled_signals || |
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!unhandled_signal(tsk, signo) || |
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!__ratelimit(&rs)) |
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return; |
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pr_info("%s[%d]: unhandled exception: ", tsk->comm, task_pid_nr(tsk)); |
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if (esr) |
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pr_cont("%s, ESR 0x%08x, ", esr_get_class_string(esr), esr); |
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pr_cont("%s", str); |
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print_vma_addr(KERN_CONT " in ", regs->pc); |
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pr_cont("\n"); |
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__show_regs(regs); |
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} |
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void arm64_force_sig_fault(int signo, int code, unsigned long far, |
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const char *str) |
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{ |
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arm64_show_signal(signo, str); |
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if (signo == SIGKILL) |
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force_sig(SIGKILL); |
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else |
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force_sig_fault(signo, code, (void __user *)far); |
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} |
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void arm64_force_sig_mceerr(int code, unsigned long far, short lsb, |
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const char *str) |
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{ |
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arm64_show_signal(SIGBUS, str); |
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force_sig_mceerr(code, (void __user *)far, lsb); |
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} |
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void arm64_force_sig_ptrace_errno_trap(int errno, unsigned long far, |
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const char *str) |
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{ |
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arm64_show_signal(SIGTRAP, str); |
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force_sig_ptrace_errno_trap(errno, (void __user *)far); |
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} |
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void arm64_notify_die(const char *str, struct pt_regs *regs, |
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int signo, int sicode, unsigned long far, |
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int err) |
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{ |
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if (user_mode(regs)) { |
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WARN_ON(regs != current_pt_regs()); |
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current->thread.fault_address = 0; |
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current->thread.fault_code = err; |
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arm64_force_sig_fault(signo, sicode, far, str); |
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} else { |
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die(str, regs, err); |
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} |
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} |
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#ifdef CONFIG_COMPAT |
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#define PSTATE_IT_1_0_SHIFT 25 |
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#define PSTATE_IT_1_0_MASK (0x3 << PSTATE_IT_1_0_SHIFT) |
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#define PSTATE_IT_7_2_SHIFT 10 |
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#define PSTATE_IT_7_2_MASK (0x3f << PSTATE_IT_7_2_SHIFT) |
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static u32 compat_get_it_state(struct pt_regs *regs) |
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{ |
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u32 it, pstate = regs->pstate; |
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it = (pstate & PSTATE_IT_1_0_MASK) >> PSTATE_IT_1_0_SHIFT; |
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it |= ((pstate & PSTATE_IT_7_2_MASK) >> PSTATE_IT_7_2_SHIFT) << 2; |
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return it; |
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} |
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static void compat_set_it_state(struct pt_regs *regs, u32 it) |
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{ |
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u32 pstate_it; |
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pstate_it = (it << PSTATE_IT_1_0_SHIFT) & PSTATE_IT_1_0_MASK; |
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pstate_it |= ((it >> 2) << PSTATE_IT_7_2_SHIFT) & PSTATE_IT_7_2_MASK; |
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regs->pstate &= ~PSR_AA32_IT_MASK; |
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regs->pstate |= pstate_it; |
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} |
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static void advance_itstate(struct pt_regs *regs) |
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{ |
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u32 it; |
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/* ARM mode */ |
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if (!(regs->pstate & PSR_AA32_T_BIT) || |
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!(regs->pstate & PSR_AA32_IT_MASK)) |
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return; |
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it = compat_get_it_state(regs); |
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/* |
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* If this is the last instruction of the block, wipe the IT |
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* state. Otherwise advance it. |
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*/ |
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if (!(it & 7)) |
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it = 0; |
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else |
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it = (it & 0xe0) | ((it << 1) & 0x1f); |
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compat_set_it_state(regs, it); |
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} |
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#else |
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static void advance_itstate(struct pt_regs *regs) |
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{ |
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} |
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#endif |
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void arm64_skip_faulting_instruction(struct pt_regs *regs, unsigned long size) |
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{ |
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regs->pc += size; |
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/* |
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* If we were single stepping, we want to get the step exception after |
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* we return from the trap. |
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*/ |
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if (user_mode(regs)) |
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user_fastforward_single_step(current); |
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if (compat_user_mode(regs)) |
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advance_itstate(regs); |
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else |
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regs->pstate &= ~PSR_BTYPE_MASK; |
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} |
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static LIST_HEAD(undef_hook); |
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static DEFINE_RAW_SPINLOCK(undef_lock); |
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void register_undef_hook(struct undef_hook *hook) |
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{ |
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unsigned long flags; |
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raw_spin_lock_irqsave(&undef_lock, flags); |
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list_add(&hook->node, &undef_hook); |
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raw_spin_unlock_irqrestore(&undef_lock, flags); |
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} |
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void unregister_undef_hook(struct undef_hook *hook) |
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{ |
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unsigned long flags; |
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raw_spin_lock_irqsave(&undef_lock, flags); |
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list_del(&hook->node); |
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raw_spin_unlock_irqrestore(&undef_lock, flags); |
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} |
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static int call_undef_hook(struct pt_regs *regs) |
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{ |
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struct undef_hook *hook; |
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unsigned long flags; |
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u32 instr; |
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int (*fn)(struct pt_regs *regs, u32 instr) = NULL; |
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void __user *pc = (void __user *)instruction_pointer(regs); |
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if (!user_mode(regs)) { |
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__le32 instr_le; |
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if (get_kernel_nofault(instr_le, (__force __le32 *)pc)) |
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goto exit; |
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instr = le32_to_cpu(instr_le); |
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} else if (compat_thumb_mode(regs)) { |
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/* 16-bit Thumb instruction */ |
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__le16 instr_le; |
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if (get_user(instr_le, (__le16 __user *)pc)) |
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goto exit; |
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instr = le16_to_cpu(instr_le); |
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if (aarch32_insn_is_wide(instr)) { |
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u32 instr2; |
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if (get_user(instr_le, (__le16 __user *)(pc + 2))) |
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goto exit; |
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instr2 = le16_to_cpu(instr_le); |
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instr = (instr << 16) | instr2; |
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} |
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} else { |
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/* 32-bit ARM instruction */ |
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__le32 instr_le; |
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if (get_user(instr_le, (__le32 __user *)pc)) |
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goto exit; |
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instr = le32_to_cpu(instr_le); |
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} |
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raw_spin_lock_irqsave(&undef_lock, flags); |
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list_for_each_entry(hook, &undef_hook, node) |
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if ((instr & hook->instr_mask) == hook->instr_val && |
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(regs->pstate & hook->pstate_mask) == hook->pstate_val) |
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fn = hook->fn; |
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raw_spin_unlock_irqrestore(&undef_lock, flags); |
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exit: |
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return fn ? fn(regs, instr) : 1; |
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} |
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void force_signal_inject(int signal, int code, unsigned long address, unsigned int err) |
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{ |
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const char *desc; |
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struct pt_regs *regs = current_pt_regs(); |
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if (WARN_ON(!user_mode(regs))) |
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return; |
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switch (signal) { |
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case SIGILL: |
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desc = "undefined instruction"; |
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break; |
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case SIGSEGV: |
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desc = "illegal memory access"; |
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break; |
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default: |
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desc = "unknown or unrecoverable error"; |
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break; |
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} |
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/* Force signals we don't understand to SIGKILL */ |
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if (WARN_ON(signal != SIGKILL && |
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siginfo_layout(signal, code) != SIL_FAULT)) { |
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signal = SIGKILL; |
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} |
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arm64_notify_die(desc, regs, signal, code, address, err); |
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} |
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/* |
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* Set up process info to signal segmentation fault - called on access error. |
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*/ |
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void arm64_notify_segfault(unsigned long addr) |
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{ |
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int code; |
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mmap_read_lock(current->mm); |
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if (find_vma(current->mm, untagged_addr(addr)) == NULL) |
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code = SEGV_MAPERR; |
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else |
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code = SEGV_ACCERR; |
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mmap_read_unlock(current->mm); |
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force_signal_inject(SIGSEGV, code, addr, 0); |
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} |
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void do_undefinstr(struct pt_regs *regs) |
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{ |
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/* check for AArch32 breakpoint instructions */ |
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if (!aarch32_break_handler(regs)) |
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return; |
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if (call_undef_hook(regs) == 0) |
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return; |
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BUG_ON(!user_mode(regs)); |
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force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); |
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} |
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NOKPROBE_SYMBOL(do_undefinstr); |
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void do_bti(struct pt_regs *regs) |
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{ |
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BUG_ON(!user_mode(regs)); |
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force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); |
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} |
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NOKPROBE_SYMBOL(do_bti); |
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void do_ptrauth_fault(struct pt_regs *regs, unsigned int esr) |
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{ |
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/* |
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* Unexpected FPAC exception or pointer authentication failure in |
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* the kernel: kill the task before it does any more harm. |
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*/ |
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BUG_ON(!user_mode(regs)); |
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force_signal_inject(SIGILL, ILL_ILLOPN, regs->pc, esr); |
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} |
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NOKPROBE_SYMBOL(do_ptrauth_fault); |
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#define __user_cache_maint(insn, address, res) \ |
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if (address >= user_addr_max()) { \ |
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res = -EFAULT; \ |
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} else { \ |
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uaccess_ttbr0_enable(); \ |
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asm volatile ( \ |
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"1: " insn ", %1\n" \ |
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" mov %w0, #0\n" \ |
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"2:\n" \ |
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" .pushsection .fixup,\"ax\"\n" \ |
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" .align 2\n" \ |
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"3: mov %w0, %w2\n" \ |
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" b 2b\n" \ |
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" .popsection\n" \ |
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_ASM_EXTABLE(1b, 3b) \ |
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: "=r" (res) \ |
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: "r" (address), "i" (-EFAULT)); \ |
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uaccess_ttbr0_disable(); \ |
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} |
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static void user_cache_maint_handler(unsigned int esr, struct pt_regs *regs) |
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{ |
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unsigned long tagged_address, address; |
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int rt = ESR_ELx_SYS64_ISS_RT(esr); |
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int crm = (esr & ESR_ELx_SYS64_ISS_CRM_MASK) >> ESR_ELx_SYS64_ISS_CRM_SHIFT; |
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int ret = 0; |
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tagged_address = pt_regs_read_reg(regs, rt); |
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address = untagged_addr(tagged_address); |
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switch (crm) { |
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case ESR_ELx_SYS64_ISS_CRM_DC_CVAU: /* DC CVAU, gets promoted */ |
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__user_cache_maint("dc civac", address, ret); |
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break; |
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case ESR_ELx_SYS64_ISS_CRM_DC_CVAC: /* DC CVAC, gets promoted */ |
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__user_cache_maint("dc civac", address, ret); |
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break; |
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case ESR_ELx_SYS64_ISS_CRM_DC_CVADP: /* DC CVADP */ |
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__user_cache_maint("sys 3, c7, c13, 1", address, ret); |
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break; |
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case ESR_ELx_SYS64_ISS_CRM_DC_CVAP: /* DC CVAP */ |
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__user_cache_maint("sys 3, c7, c12, 1", address, ret); |
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break; |
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case ESR_ELx_SYS64_ISS_CRM_DC_CIVAC: /* DC CIVAC */ |
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__user_cache_maint("dc civac", address, ret); |
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break; |
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case ESR_ELx_SYS64_ISS_CRM_IC_IVAU: /* IC IVAU */ |
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__user_cache_maint("ic ivau", address, ret); |
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break; |
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default: |
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force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); |
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return; |
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} |
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if (ret) |
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arm64_notify_segfault(tagged_address); |
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else |
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arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); |
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} |
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static void ctr_read_handler(unsigned int esr, struct pt_regs *regs) |
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{ |
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int rt = ESR_ELx_SYS64_ISS_RT(esr); |
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unsigned long val = arm64_ftr_reg_user_value(&arm64_ftr_reg_ctrel0); |
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if (cpus_have_const_cap(ARM64_WORKAROUND_1542419)) { |
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/* Hide DIC so that we can trap the unnecessary maintenance...*/ |
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val &= ~BIT(CTR_DIC_SHIFT); |
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|
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/* ... and fake IminLine to reduce the number of traps. */ |
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val &= ~CTR_IMINLINE_MASK; |
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val |= (PAGE_SHIFT - 2) & CTR_IMINLINE_MASK; |
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} |
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pt_regs_write_reg(regs, rt, val); |
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arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); |
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} |
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static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs) |
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{ |
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int rt = ESR_ELx_SYS64_ISS_RT(esr); |
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pt_regs_write_reg(regs, rt, arch_timer_read_counter()); |
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arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); |
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} |
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static void cntfrq_read_handler(unsigned int esr, struct pt_regs *regs) |
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{ |
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int rt = ESR_ELx_SYS64_ISS_RT(esr); |
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pt_regs_write_reg(regs, rt, arch_timer_get_rate()); |
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arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); |
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} |
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static void mrs_handler(unsigned int esr, struct pt_regs *regs) |
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{ |
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u32 sysreg, rt; |
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rt = ESR_ELx_SYS64_ISS_RT(esr); |
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sysreg = esr_sys64_to_sysreg(esr); |
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if (do_emulate_mrs(regs, sysreg, rt) != 0) |
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force_signal_inject(SIGILL, ILL_ILLOPC, regs->pc, 0); |
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} |
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static void wfi_handler(unsigned int esr, struct pt_regs *regs) |
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{ |
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arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); |
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} |
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struct sys64_hook { |
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unsigned int esr_mask; |
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unsigned int esr_val; |
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void (*handler)(unsigned int esr, struct pt_regs *regs); |
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}; |
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static const struct sys64_hook sys64_hooks[] = { |
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{ |
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.esr_mask = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK, |
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.esr_val = ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL, |
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.handler = user_cache_maint_handler, |
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}, |
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{ |
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/* Trap read access to CTR_EL0 */ |
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.esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, |
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.esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ, |
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.handler = ctr_read_handler, |
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}, |
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{ |
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/* Trap read access to CNTVCT_EL0 */ |
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.esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, |
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.esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT, |
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.handler = cntvct_read_handler, |
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}, |
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{ |
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/* Trap read access to CNTFRQ_EL0 */ |
|
.esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK, |
|
.esr_val = ESR_ELx_SYS64_ISS_SYS_CNTFRQ, |
|
.handler = cntfrq_read_handler, |
|
}, |
|
{ |
|
/* Trap read access to CPUID registers */ |
|
.esr_mask = ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK, |
|
.esr_val = ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL, |
|
.handler = mrs_handler, |
|
}, |
|
{ |
|
/* Trap WFI instructions executed in userspace */ |
|
.esr_mask = ESR_ELx_WFx_MASK, |
|
.esr_val = ESR_ELx_WFx_WFI_VAL, |
|
.handler = wfi_handler, |
|
}, |
|
{}, |
|
}; |
|
|
|
#ifdef CONFIG_COMPAT |
|
static bool cp15_cond_valid(unsigned int esr, struct pt_regs *regs) |
|
{ |
|
int cond; |
|
|
|
/* Only a T32 instruction can trap without CV being set */ |
|
if (!(esr & ESR_ELx_CV)) { |
|
u32 it; |
|
|
|
it = compat_get_it_state(regs); |
|
if (!it) |
|
return true; |
|
|
|
cond = it >> 4; |
|
} else { |
|
cond = (esr & ESR_ELx_COND_MASK) >> ESR_ELx_COND_SHIFT; |
|
} |
|
|
|
return aarch32_opcode_cond_checks[cond](regs->pstate); |
|
} |
|
|
|
static void compat_cntfrq_read_handler(unsigned int esr, struct pt_regs *regs) |
|
{ |
|
int reg = (esr & ESR_ELx_CP15_32_ISS_RT_MASK) >> ESR_ELx_CP15_32_ISS_RT_SHIFT; |
|
|
|
pt_regs_write_reg(regs, reg, arch_timer_get_rate()); |
|
arm64_skip_faulting_instruction(regs, 4); |
|
} |
|
|
|
static const struct sys64_hook cp15_32_hooks[] = { |
|
{ |
|
.esr_mask = ESR_ELx_CP15_32_ISS_SYS_MASK, |
|
.esr_val = ESR_ELx_CP15_32_ISS_SYS_CNTFRQ, |
|
.handler = compat_cntfrq_read_handler, |
|
}, |
|
{}, |
|
}; |
|
|
|
static void compat_cntvct_read_handler(unsigned int esr, struct pt_regs *regs) |
|
{ |
|
int rt = (esr & ESR_ELx_CP15_64_ISS_RT_MASK) >> ESR_ELx_CP15_64_ISS_RT_SHIFT; |
|
int rt2 = (esr & ESR_ELx_CP15_64_ISS_RT2_MASK) >> ESR_ELx_CP15_64_ISS_RT2_SHIFT; |
|
u64 val = arch_timer_read_counter(); |
|
|
|
pt_regs_write_reg(regs, rt, lower_32_bits(val)); |
|
pt_regs_write_reg(regs, rt2, upper_32_bits(val)); |
|
arm64_skip_faulting_instruction(regs, 4); |
|
} |
|
|
|
static const struct sys64_hook cp15_64_hooks[] = { |
|
{ |
|
.esr_mask = ESR_ELx_CP15_64_ISS_SYS_MASK, |
|
.esr_val = ESR_ELx_CP15_64_ISS_SYS_CNTVCT, |
|
.handler = compat_cntvct_read_handler, |
|
}, |
|
{}, |
|
}; |
|
|
|
void do_cp15instr(unsigned int esr, struct pt_regs *regs) |
|
{ |
|
const struct sys64_hook *hook, *hook_base; |
|
|
|
if (!cp15_cond_valid(esr, regs)) { |
|
/* |
|
* There is no T16 variant of a CP access, so we |
|
* always advance PC by 4 bytes. |
|
*/ |
|
arm64_skip_faulting_instruction(regs, 4); |
|
return; |
|
} |
|
|
|
switch (ESR_ELx_EC(esr)) { |
|
case ESR_ELx_EC_CP15_32: |
|
hook_base = cp15_32_hooks; |
|
break; |
|
case ESR_ELx_EC_CP15_64: |
|
hook_base = cp15_64_hooks; |
|
break; |
|
default: |
|
do_undefinstr(regs); |
|
return; |
|
} |
|
|
|
for (hook = hook_base; hook->handler; hook++) |
|
if ((hook->esr_mask & esr) == hook->esr_val) { |
|
hook->handler(esr, regs); |
|
return; |
|
} |
|
|
|
/* |
|
* New cp15 instructions may previously have been undefined at |
|
* EL0. Fall back to our usual undefined instruction handler |
|
* so that we handle these consistently. |
|
*/ |
|
do_undefinstr(regs); |
|
} |
|
NOKPROBE_SYMBOL(do_cp15instr); |
|
#endif |
|
|
|
void do_sysinstr(unsigned int esr, struct pt_regs *regs) |
|
{ |
|
const struct sys64_hook *hook; |
|
|
|
for (hook = sys64_hooks; hook->handler; hook++) |
|
if ((hook->esr_mask & esr) == hook->esr_val) { |
|
hook->handler(esr, regs); |
|
return; |
|
} |
|
|
|
/* |
|
* New SYS instructions may previously have been undefined at EL0. Fall |
|
* back to our usual undefined instruction handler so that we handle |
|
* these consistently. |
|
*/ |
|
do_undefinstr(regs); |
|
} |
|
NOKPROBE_SYMBOL(do_sysinstr); |
|
|
|
static const char *esr_class_str[] = { |
|
[0 ... ESR_ELx_EC_MAX] = "UNRECOGNIZED EC", |
|
[ESR_ELx_EC_UNKNOWN] = "Unknown/Uncategorized", |
|
[ESR_ELx_EC_WFx] = "WFI/WFE", |
|
[ESR_ELx_EC_CP15_32] = "CP15 MCR/MRC", |
|
[ESR_ELx_EC_CP15_64] = "CP15 MCRR/MRRC", |
|
[ESR_ELx_EC_CP14_MR] = "CP14 MCR/MRC", |
|
[ESR_ELx_EC_CP14_LS] = "CP14 LDC/STC", |
|
[ESR_ELx_EC_FP_ASIMD] = "ASIMD", |
|
[ESR_ELx_EC_CP10_ID] = "CP10 MRC/VMRS", |
|
[ESR_ELx_EC_PAC] = "PAC", |
|
[ESR_ELx_EC_CP14_64] = "CP14 MCRR/MRRC", |
|
[ESR_ELx_EC_BTI] = "BTI", |
|
[ESR_ELx_EC_ILL] = "PSTATE.IL", |
|
[ESR_ELx_EC_SVC32] = "SVC (AArch32)", |
|
[ESR_ELx_EC_HVC32] = "HVC (AArch32)", |
|
[ESR_ELx_EC_SMC32] = "SMC (AArch32)", |
|
[ESR_ELx_EC_SVC64] = "SVC (AArch64)", |
|
[ESR_ELx_EC_HVC64] = "HVC (AArch64)", |
|
[ESR_ELx_EC_SMC64] = "SMC (AArch64)", |
|
[ESR_ELx_EC_SYS64] = "MSR/MRS (AArch64)", |
|
[ESR_ELx_EC_SVE] = "SVE", |
|
[ESR_ELx_EC_ERET] = "ERET/ERETAA/ERETAB", |
|
[ESR_ELx_EC_FPAC] = "FPAC", |
|
[ESR_ELx_EC_IMP_DEF] = "EL3 IMP DEF", |
|
[ESR_ELx_EC_IABT_LOW] = "IABT (lower EL)", |
|
[ESR_ELx_EC_IABT_CUR] = "IABT (current EL)", |
|
[ESR_ELx_EC_PC_ALIGN] = "PC Alignment", |
|
[ESR_ELx_EC_DABT_LOW] = "DABT (lower EL)", |
|
[ESR_ELx_EC_DABT_CUR] = "DABT (current EL)", |
|
[ESR_ELx_EC_SP_ALIGN] = "SP Alignment", |
|
[ESR_ELx_EC_FP_EXC32] = "FP (AArch32)", |
|
[ESR_ELx_EC_FP_EXC64] = "FP (AArch64)", |
|
[ESR_ELx_EC_SERROR] = "SError", |
|
[ESR_ELx_EC_BREAKPT_LOW] = "Breakpoint (lower EL)", |
|
[ESR_ELx_EC_BREAKPT_CUR] = "Breakpoint (current EL)", |
|
[ESR_ELx_EC_SOFTSTP_LOW] = "Software Step (lower EL)", |
|
[ESR_ELx_EC_SOFTSTP_CUR] = "Software Step (current EL)", |
|
[ESR_ELx_EC_WATCHPT_LOW] = "Watchpoint (lower EL)", |
|
[ESR_ELx_EC_WATCHPT_CUR] = "Watchpoint (current EL)", |
|
[ESR_ELx_EC_BKPT32] = "BKPT (AArch32)", |
|
[ESR_ELx_EC_VECTOR32] = "Vector catch (AArch32)", |
|
[ESR_ELx_EC_BRK64] = "BRK (AArch64)", |
|
}; |
|
|
|
const char *esr_get_class_string(u32 esr) |
|
{ |
|
return esr_class_str[ESR_ELx_EC(esr)]; |
|
} |
|
|
|
/* |
|
* bad_mode handles the impossible case in the exception vector. This is always |
|
* fatal. |
|
*/ |
|
asmlinkage void notrace bad_mode(struct pt_regs *regs, int reason, unsigned int esr) |
|
{ |
|
arm64_enter_nmi(regs); |
|
|
|
console_verbose(); |
|
|
|
pr_crit("Bad mode in %s handler detected on CPU%d, code 0x%08x -- %s\n", |
|
handler[reason], smp_processor_id(), esr, |
|
esr_get_class_string(esr)); |
|
|
|
__show_regs(regs); |
|
local_daif_mask(); |
|
panic("bad mode"); |
|
} |
|
|
|
/* |
|
* bad_el0_sync handles unexpected, but potentially recoverable synchronous |
|
* exceptions taken from EL0. Unlike bad_mode, this returns. |
|
*/ |
|
void bad_el0_sync(struct pt_regs *regs, int reason, unsigned int esr) |
|
{ |
|
unsigned long pc = instruction_pointer(regs); |
|
|
|
current->thread.fault_address = 0; |
|
current->thread.fault_code = esr; |
|
|
|
arm64_force_sig_fault(SIGILL, ILL_ILLOPC, pc, |
|
"Bad EL0 synchronous exception"); |
|
} |
|
|
|
#ifdef CONFIG_VMAP_STACK |
|
|
|
DEFINE_PER_CPU(unsigned long [OVERFLOW_STACK_SIZE/sizeof(long)], overflow_stack) |
|
__aligned(16); |
|
|
|
asmlinkage void noinstr handle_bad_stack(struct pt_regs *regs) |
|
{ |
|
unsigned long tsk_stk = (unsigned long)current->stack; |
|
unsigned long irq_stk = (unsigned long)this_cpu_read(irq_stack_ptr); |
|
unsigned long ovf_stk = (unsigned long)this_cpu_ptr(overflow_stack); |
|
unsigned int esr = read_sysreg(esr_el1); |
|
unsigned long far = read_sysreg(far_el1); |
|
|
|
arm64_enter_nmi(regs); |
|
|
|
console_verbose(); |
|
pr_emerg("Insufficient stack space to handle exception!"); |
|
|
|
pr_emerg("ESR: 0x%08x -- %s\n", esr, esr_get_class_string(esr)); |
|
pr_emerg("FAR: 0x%016lx\n", far); |
|
|
|
pr_emerg("Task stack: [0x%016lx..0x%016lx]\n", |
|
tsk_stk, tsk_stk + THREAD_SIZE); |
|
pr_emerg("IRQ stack: [0x%016lx..0x%016lx]\n", |
|
irq_stk, irq_stk + IRQ_STACK_SIZE); |
|
pr_emerg("Overflow stack: [0x%016lx..0x%016lx]\n", |
|
ovf_stk, ovf_stk + OVERFLOW_STACK_SIZE); |
|
|
|
__show_regs(regs); |
|
|
|
/* |
|
* We use nmi_panic to limit the potential for recusive overflows, and |
|
* to get a better stack trace. |
|
*/ |
|
nmi_panic(NULL, "kernel stack overflow"); |
|
cpu_park_loop(); |
|
} |
|
#endif |
|
|
|
void __noreturn arm64_serror_panic(struct pt_regs *regs, u32 esr) |
|
{ |
|
console_verbose(); |
|
|
|
pr_crit("SError Interrupt on CPU%d, code 0x%08x -- %s\n", |
|
smp_processor_id(), esr, esr_get_class_string(esr)); |
|
if (regs) |
|
__show_regs(regs); |
|
|
|
nmi_panic(regs, "Asynchronous SError Interrupt"); |
|
|
|
cpu_park_loop(); |
|
unreachable(); |
|
} |
|
|
|
bool arm64_is_fatal_ras_serror(struct pt_regs *regs, unsigned int esr) |
|
{ |
|
u32 aet = arm64_ras_serror_get_severity(esr); |
|
|
|
switch (aet) { |
|
case ESR_ELx_AET_CE: /* corrected error */ |
|
case ESR_ELx_AET_UEO: /* restartable, not yet consumed */ |
|
/* |
|
* The CPU can make progress. We may take UEO again as |
|
* a more severe error. |
|
*/ |
|
return false; |
|
|
|
case ESR_ELx_AET_UEU: /* Uncorrected Unrecoverable */ |
|
case ESR_ELx_AET_UER: /* Uncorrected Recoverable */ |
|
/* |
|
* The CPU can't make progress. The exception may have |
|
* been imprecise. |
|
* |
|
* Neoverse-N1 #1349291 means a non-KVM SError reported as |
|
* Unrecoverable should be treated as Uncontainable. We |
|
* call arm64_serror_panic() in both cases. |
|
*/ |
|
return true; |
|
|
|
case ESR_ELx_AET_UC: /* Uncontainable or Uncategorized error */ |
|
default: |
|
/* Error has been silently propagated */ |
|
arm64_serror_panic(regs, esr); |
|
} |
|
} |
|
|
|
asmlinkage void noinstr do_serror(struct pt_regs *regs, unsigned int esr) |
|
{ |
|
arm64_enter_nmi(regs); |
|
|
|
/* non-RAS errors are not containable */ |
|
if (!arm64_is_ras_serror(esr) || arm64_is_fatal_ras_serror(regs, esr)) |
|
arm64_serror_panic(regs, esr); |
|
|
|
arm64_exit_nmi(regs); |
|
} |
|
|
|
/* GENERIC_BUG traps */ |
|
|
|
int is_valid_bugaddr(unsigned long addr) |
|
{ |
|
/* |
|
* bug_handler() only called for BRK #BUG_BRK_IMM. |
|
* So the answer is trivial -- any spurious instances with no |
|
* bug table entry will be rejected by report_bug() and passed |
|
* back to the debug-monitors code and handled as a fatal |
|
* unexpected debug exception. |
|
*/ |
|
return 1; |
|
} |
|
|
|
static int bug_handler(struct pt_regs *regs, unsigned int esr) |
|
{ |
|
switch (report_bug(regs->pc, regs)) { |
|
case BUG_TRAP_TYPE_BUG: |
|
die("Oops - BUG", regs, 0); |
|
break; |
|
|
|
case BUG_TRAP_TYPE_WARN: |
|
break; |
|
|
|
default: |
|
/* unknown/unrecognised bug trap type */ |
|
return DBG_HOOK_ERROR; |
|
} |
|
|
|
/* If thread survives, skip over the BUG instruction and continue: */ |
|
arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); |
|
return DBG_HOOK_HANDLED; |
|
} |
|
|
|
static struct break_hook bug_break_hook = { |
|
.fn = bug_handler, |
|
.imm = BUG_BRK_IMM, |
|
}; |
|
|
|
static int reserved_fault_handler(struct pt_regs *regs, unsigned int esr) |
|
{ |
|
pr_err("%s generated an invalid instruction at %pS!\n", |
|
in_bpf_jit(regs) ? "BPF JIT" : "Kernel text patching", |
|
(void *)instruction_pointer(regs)); |
|
|
|
/* We cannot handle this */ |
|
return DBG_HOOK_ERROR; |
|
} |
|
|
|
static struct break_hook fault_break_hook = { |
|
.fn = reserved_fault_handler, |
|
.imm = FAULT_BRK_IMM, |
|
}; |
|
|
|
#ifdef CONFIG_KASAN_SW_TAGS |
|
|
|
#define KASAN_ESR_RECOVER 0x20 |
|
#define KASAN_ESR_WRITE 0x10 |
|
#define KASAN_ESR_SIZE_MASK 0x0f |
|
#define KASAN_ESR_SIZE(esr) (1 << ((esr) & KASAN_ESR_SIZE_MASK)) |
|
|
|
static int kasan_handler(struct pt_regs *regs, unsigned int esr) |
|
{ |
|
bool recover = esr & KASAN_ESR_RECOVER; |
|
bool write = esr & KASAN_ESR_WRITE; |
|
size_t size = KASAN_ESR_SIZE(esr); |
|
u64 addr = regs->regs[0]; |
|
u64 pc = regs->pc; |
|
|
|
kasan_report(addr, size, write, pc); |
|
|
|
/* |
|
* The instrumentation allows to control whether we can proceed after |
|
* a crash was detected. This is done by passing the -recover flag to |
|
* the compiler. Disabling recovery allows to generate more compact |
|
* code. |
|
* |
|
* Unfortunately disabling recovery doesn't work for the kernel right |
|
* now. KASAN reporting is disabled in some contexts (for example when |
|
* the allocator accesses slab object metadata; this is controlled by |
|
* current->kasan_depth). All these accesses are detected by the tool, |
|
* even though the reports for them are not printed. |
|
* |
|
* This is something that might be fixed at some point in the future. |
|
*/ |
|
if (!recover) |
|
die("Oops - KASAN", regs, 0); |
|
|
|
/* If thread survives, skip over the brk instruction and continue: */ |
|
arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); |
|
return DBG_HOOK_HANDLED; |
|
} |
|
|
|
static struct break_hook kasan_break_hook = { |
|
.fn = kasan_handler, |
|
.imm = KASAN_BRK_IMM, |
|
.mask = KASAN_BRK_MASK, |
|
}; |
|
#endif |
|
|
|
/* |
|
* Initial handler for AArch64 BRK exceptions |
|
* This handler only used until debug_traps_init(). |
|
*/ |
|
int __init early_brk64(unsigned long addr, unsigned int esr, |
|
struct pt_regs *regs) |
|
{ |
|
#ifdef CONFIG_KASAN_SW_TAGS |
|
unsigned int comment = esr & ESR_ELx_BRK64_ISS_COMMENT_MASK; |
|
|
|
if ((comment & ~KASAN_BRK_MASK) == KASAN_BRK_IMM) |
|
return kasan_handler(regs, esr) != DBG_HOOK_HANDLED; |
|
#endif |
|
return bug_handler(regs, esr) != DBG_HOOK_HANDLED; |
|
} |
|
|
|
void __init trap_init(void) |
|
{ |
|
register_kernel_break_hook(&bug_break_hook); |
|
register_kernel_break_hook(&fault_break_hook); |
|
#ifdef CONFIG_KASAN_SW_TAGS |
|
register_kernel_break_hook(&kasan_break_hook); |
|
#endif |
|
debug_traps_init(); |
|
}
|
|
|