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310 lines
7.3 KiB
310 lines
7.3 KiB
/* |
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* Spreadtrum Whale2 platform peripherals |
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* |
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* Copyright (C) 2016, Spreadtrum Communications Inc. |
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* |
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
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*/ |
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#include <dt-bindings/clock/sprd,sc9860-clk.h> |
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/ { |
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interrupt-parent = <&gic>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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soc: soc { |
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compatible = "simple-bus"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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ap_ahb_regs: syscon@20210000 { |
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compatible = "syscon"; |
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reg = <0 0x20210000 0 0x10000>; |
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}; |
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pmu_regs: syscon@402b0000 { |
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compatible = "syscon"; |
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reg = <0 0x402b0000 0 0x10000>; |
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}; |
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aon_regs: syscon@402e0000 { |
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compatible = "syscon"; |
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reg = <0 0x402e0000 0 0x10000>; |
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}; |
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ana_regs: syscon@40400000 { |
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compatible = "syscon"; |
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reg = <0 0x40400000 0 0x10000>; |
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}; |
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agcp_regs: syscon@415e0000 { |
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compatible = "syscon"; |
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reg = <0 0x415e0000 0 0x1000000>; |
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}; |
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vsp_regs: syscon@61100000 { |
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compatible = "syscon"; |
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reg = <0 0x61100000 0 0x10000>; |
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}; |
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cam_regs: syscon@62100000 { |
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compatible = "syscon"; |
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reg = <0 0x62100000 0 0x10000>; |
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}; |
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disp_regs: syscon@63100000 { |
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compatible = "syscon"; |
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reg = <0 0x63100000 0 0x10000>; |
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}; |
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ap_apb_regs: syscon@70b00000 { |
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compatible = "syscon"; |
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reg = <0 0x70b00000 0 0x40000>; |
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}; |
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ap-apb { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0 0x0 0x70000000 0x10000000>; |
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uart0: serial@0 { |
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compatible = "sprd,sc9860-uart", |
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"sprd,sc9836-uart"; |
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reg = <0x0 0x100>; |
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
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clock-names = "enable", "uart", "source"; |
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clocks = <&apapb_gate CLK_UART0_EB>, |
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<&ap_clk CLK_UART0>, <&ext_26m>; |
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status = "disabled"; |
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}; |
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uart1: serial@100000 { |
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compatible = "sprd,sc9860-uart", |
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"sprd,sc9836-uart"; |
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reg = <0x100000 0x100>; |
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
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clock-names = "enable", "uart", "source"; |
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clocks = <&apapb_gate CLK_UART1_EB>, |
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<&ap_clk CLK_UART1>, <&ext_26m>; |
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status = "disabled"; |
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}; |
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uart2: serial@200000 { |
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compatible = "sprd,sc9860-uart", |
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"sprd,sc9836-uart"; |
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reg = <0x200000 0x100>; |
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
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clock-names = "enable", "uart", "source"; |
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clocks = <&apapb_gate CLK_UART2_EB>, |
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<&ap_clk CLK_UART2>, <&ext_26m>; |
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status = "disabled"; |
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}; |
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uart3: serial@300000 { |
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compatible = "sprd,sc9860-uart", |
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"sprd,sc9836-uart"; |
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reg = <0x300000 0x100>; |
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
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clock-names = "enable", "uart", "source"; |
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clocks = <&apapb_gate CLK_UART3_EB>, |
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<&ap_clk CLK_UART3>, <&ext_26m>; |
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status = "disabled"; |
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}; |
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}; |
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ap-ahb { |
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compatible = "simple-bus"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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ap_dma: dma-controller@20100000 { |
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compatible = "sprd,sc9860-dma"; |
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reg = <0 0x20100000 0 0x4000>; |
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
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#dma-cells = <1>; |
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#dma-channels = <32>; |
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clock-names = "enable"; |
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clocks = <&apahb_gate CLK_DMA_EB>; |
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}; |
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sdio3: sdio@50430000 { |
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compatible = "sprd,sdhci-r11"; |
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reg = <0 0x50430000 0 0x1000>; |
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
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clock-names = "sdio", "enable", "2x_enable"; |
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clocks = <&aon_prediv CLK_EMMC_2X>, |
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<&apahb_gate CLK_EMMC_EB>, |
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<&aon_gate CLK_EMMC_2X_EN>; |
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assigned-clocks = <&aon_prediv CLK_EMMC_2X>; |
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assigned-clock-parents = <&clk_l0_409m6>; |
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sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>; |
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sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>; |
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sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>; |
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sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 0x2e 0x2e>; |
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vmmc-supply = <&vddemmccore>; |
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bus-width = <8>; |
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non-removable; |
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no-sdio; |
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no-sd; |
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cap-mmc-hw-reset; |
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mmc-hs400-enhanced-strobe; |
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mmc-hs400-1_8v; |
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mmc-hs200-1_8v; |
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mmc-ddr-1_8v; |
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}; |
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}; |
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aon { |
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compatible = "simple-bus"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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adi_bus: spi@40030000 { |
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compatible = "sprd,sc9860-adi"; |
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reg = <0 0x40030000 0 0x10000>; |
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hwlocks = <&hwlock 0>; |
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hwlock-names = "adi"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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}; |
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timer@40050000 { |
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compatible = "sprd,sc9860-timer"; |
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reg = <0 0x40050000 0 0x20>; |
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&ext_32k>; |
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}; |
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timer@40050020 { |
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compatible = "sprd,sc9860-suspend-timer"; |
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reg = <0 0x40050020 0 0x20>; |
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clocks = <&ext_32k>; |
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}; |
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hwlock: hwspinlock@40500000 { |
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compatible = "sprd,hwspinlock-r3p0"; |
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reg = <0 0x40500000 0 0x1000>; |
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#hwlock-cells = <1>; |
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clock-names = "enable"; |
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clocks = <&aon_gate CLK_SPLK_EB>; |
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}; |
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eic_debounce: gpio@40210000 { |
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compatible = "sprd,sc9860-eic-debounce"; |
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reg = <0 0x40210000 0 0x80>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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eic_latch: gpio@40210080 { |
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compatible = "sprd,sc9860-eic-latch"; |
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reg = <0 0x40210080 0 0x20>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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eic_async: gpio@402100a0 { |
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compatible = "sprd,sc9860-eic-async"; |
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reg = <0 0x402100a0 0 0x20>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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eic_sync: gpio@402100c0 { |
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compatible = "sprd,sc9860-eic-sync"; |
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reg = <0 0x402100c0 0 0x20>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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ap_gpio: gpio@40280000 { |
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compatible = "sprd,sc9860-gpio"; |
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reg = <0 0x40280000 0 0x1000>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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pin_controller: pinctrl@402a0000 { |
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compatible = "sprd,sc9860-pinctrl"; |
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reg = <0 0x402a0000 0 0x10000>; |
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}; |
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watchdog@40310000 { |
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compatible = "sprd,sp9860-wdt"; |
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reg = <0 0x40310000 0 0x1000>; |
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
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timeout-sec = <12>; |
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clock-names = "enable", "rtc_enable"; |
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clocks = <&aon_gate CLK_APCPU_WDG_EB>, |
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<&aon_gate CLK_AP_WDG_RTC_EB>; |
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}; |
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}; |
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agcp { |
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compatible = "simple-bus"; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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agcp_dma: dma-controller@41580000 { |
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compatible = "sprd,sc9860-dma"; |
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reg = <0 0x41580000 0 0x4000>; |
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#dma-cells = <1>; |
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#dma-channels = <32>; |
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clock-names = "enable", "ashb_eb"; |
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clocks = <&agcp_gate CLK_AGCP_DMAAP_EB>, |
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<&agcp_gate CLK_AGCP_AP_ASHB_EB>; |
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}; |
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}; |
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}; |
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ext_32k: ext_32k { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <32768>; |
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clock-output-names = "ext-32k"; |
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}; |
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ext_26m: ext_26m { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <26000000>; |
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clock-output-names = "ext-26m"; |
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}; |
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ext_rco_100m: ext_rco_100m { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <100000000>; |
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clock-output-names = "ext-rco-100m"; |
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}; |
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clk_l0_409m6: clk_l0_409m6 { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <409600000>; |
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clock-output-names = "ext-409m6"; |
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}; |
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};
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