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229 lines
4.6 KiB
229 lines
4.6 KiB
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) |
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/* |
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* Realtek RTD16xx SoC family |
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* |
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* Copyright (c) 2019 Realtek Semiconductor Corp. |
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* Copyright (c) 2019 Andreas Färber |
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*/ |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/interrupt-controller/irq.h> |
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/ { |
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interrupt-parent = <&gic>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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reserved-memory { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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rpc_comm: rpc@2f000 { |
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reg = <0x2f000 0x1000>; |
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}; |
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rpc_ringbuf: rpc@1ffe000 { |
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reg = <0x1ffe000 0x4000>; |
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}; |
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tee: tee@10100000 { |
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reg = <0x10100000 0xf00000>; |
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no-map; |
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}; |
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}; |
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cpus { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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cpu0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a55"; |
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reg = <0x0>; |
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enable-method = "psci"; |
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next-level-cache = <&l2>; |
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}; |
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cpu1: cpu@100 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a55"; |
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reg = <0x100>; |
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enable-method = "psci"; |
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next-level-cache = <&l3>; |
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}; |
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cpu2: cpu@200 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a55"; |
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reg = <0x200>; |
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enable-method = "psci"; |
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next-level-cache = <&l3>; |
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}; |
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cpu3: cpu@300 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a55"; |
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reg = <0x300>; |
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enable-method = "psci"; |
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next-level-cache = <&l3>; |
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}; |
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cpu4: cpu@400 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a55"; |
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reg = <0x400>; |
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enable-method = "psci"; |
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next-level-cache = <&l3>; |
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}; |
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cpu5: cpu@500 { |
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device_type = "cpu"; |
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compatible = "arm,cortex-a55"; |
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reg = <0x500>; |
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enable-method = "psci"; |
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next-level-cache = <&l3>; |
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}; |
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l2: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&l3>; |
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}; |
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l3: l3-cache { |
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compatible = "cache"; |
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}; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
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}; |
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arm_pmu: pmu { |
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compatible = "arm,armv8-pmuv3"; |
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; |
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, |
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<&cpu3>, <&cpu4>, <&cpu5>; |
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}; |
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psci { |
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compatible = "arm,psci-1.0"; |
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method = "smc"; |
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}; |
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osc27M: osc { |
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compatible = "fixed-clock"; |
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clock-frequency = <27000000>; |
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clock-output-names = "osc27M"; |
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#clock-cells = <0>; |
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}; |
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soc { |
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compatible = "simple-bus"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0x00000000 0x00000000 0x0002e000>, /* boot ROM */ |
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<0x98000000 0x98000000 0x68000000>; |
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rbus: bus@98000000 { |
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compatible = "simple-bus"; |
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reg = <0x98000000 0x200000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0x0 0x98000000 0x200000>; |
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crt: syscon@0 { |
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compatible = "syscon", "simple-mfd"; |
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reg = <0x0 0x1000>; |
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reg-io-width = <4>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0x0 0x0 0x1000>; |
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}; |
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iso: syscon@7000 { |
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compatible = "syscon", "simple-mfd"; |
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reg = <0x7000 0x1000>; |
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reg-io-width = <4>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0x0 0x7000 0x1000>; |
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}; |
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sb2: syscon@1a000 { |
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compatible = "syscon", "simple-mfd"; |
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reg = <0x1a000 0x1000>; |
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reg-io-width = <4>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0x0 0x1a000 0x1000>; |
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}; |
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misc: syscon@1b000 { |
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compatible = "syscon", "simple-mfd"; |
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reg = <0x1b000 0x1000>; |
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reg-io-width = <4>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0x0 0x1b000 0x1000>; |
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}; |
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scpu_wrapper: syscon@1d000 { |
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compatible = "syscon", "simple-mfd"; |
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reg = <0x1d000 0x1000>; |
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reg-io-width = <4>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges = <0x0 0x1d000 0x1000>; |
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}; |
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}; |
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gic: interrupt-controller@ff100000 { |
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compatible = "arm,gic-v3"; |
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reg = <0xff100000 0x10000>, |
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<0xff140000 0xc0000>; |
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-controller; |
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#interrupt-cells = <3>; |
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}; |
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}; |
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}; |
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&iso { |
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uart0: serial0@800 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x800 0x400>; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
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clock-frequency = <27000000>; |
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status = "disabled"; |
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}; |
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}; |
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&misc { |
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uart1: serial1@200 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x200 0x400>; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
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clock-frequency = <432000000>; |
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status = "disabled"; |
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}; |
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uart2: serial2@400 { |
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compatible = "snps,dw-apb-uart"; |
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reg = <0x400 0x400>; |
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reg-shift = <2>; |
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reg-io-width = <4>; |
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
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clock-frequency = <432000000>; |
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status = "disabled"; |
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}; |
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};
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